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b9249c461c
This is a hand-written implementation that should have fairly complete
coverage for the base integer instruction set ("i"), and for the atomic
("a") and integer multiplication+division ("m") extensions. It also
covers 32-bit & 64-bit targets.
The unittest coverage is a bit weak atm, but should get better.
87 lines
2.4 KiB
C
87 lines
2.4 KiB
C
/* RISC-V simulator.
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Copyright (C) 2005-2021 Free Software Foundation, Inc.
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Contributed by Mike Frysinger.
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This file is part of simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef SIM_MAIN_H
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#define SIM_MAIN_H
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#include "sim-basics.h"
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#include "machs.h"
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#include "sim-base.h"
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struct _sim_cpu {
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union {
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unsigned_word regs[32];
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struct {
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/* These are the ABI names. */
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unsigned_word zero, ra, sp, gp, tp;
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unsigned_word t0, t1, t2;
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unsigned_word s0, s1;
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unsigned_word a0, a1, a2, a3, a4, a5, a6, a7;
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unsigned_word s2, s3, s4, s5, s6, s7, s8, s9, s10, s11;
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unsigned_word t3, t4, t5, t6;
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};
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};
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union {
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unsigned_word fpregs[32];
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struct {
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/* These are the ABI names. */
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unsigned_word ft0, ft1, ft2, ft3, ft4, ft5, ft6, ft7;
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unsigned_word fs0, fs1;
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unsigned_word fa0, fa1, fa2, fa3, fa4, fa5, fa6, fa7;
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unsigned_word fs2, fs3, fs4, fs5, fs6, fs7, fs8, fs9, fs10, fs11;
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unsigned_word ft8, ft9, ft10, ft11;
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};
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};
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sim_cia pc;
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struct {
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#define DECLARE_CSR(name, ...) unsigned_word name;
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#include "opcode/riscv-opc.h"
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#undef DECLARE_CSR
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} csr;
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sim_cpu_base base;
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};
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struct atomic_mem_reserved_list;
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struct atomic_mem_reserved_list {
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struct atomic_mem_reserved_list *next;
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address_word addr;
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};
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struct sim_state {
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sim_cpu *cpu[MAX_NR_PROCESSORS];
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struct atomic_mem_reserved_list *amo_reserved_list;
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/* ... simulator specific members ... */
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sim_state_base base;
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};
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extern void step_once (SIM_CPU *);
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extern void initialize_cpu (SIM_DESC, SIM_CPU *, int);
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extern void initialize_env (SIM_DESC, const char * const *argv,
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const char * const *env);
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#define DEFAULT_MEM_SIZE (64 * 1024 * 1024)
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#define RISCV_XLEN(cpu) MACH_WORD_BITSIZE (CPU_MACH (cpu))
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#endif
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