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https://sourceware.org/git/binutils-gdb.git
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9239bbd3a6
bfd/ PR ld/20030 * elf32-arm.c (is_thumb2_vldm): Account for T1 (DP) encoding. (stm32l4xx_need_create_replacing_stub): Rename ambiguous nb_regs to nb_words. (create_instruction_vldmia): Add is_dp to disambiguate SP/DP encoding. (create_instruction_vldmdb): Likewise. (stm32l4xx_create_replacing_stub_vldm): is_dp detects DP encoding, uses it to re-encode. ld/ PR ld/20030 * testsuite/ld-arm/arm-elf.exp: Run new stm32l4xx-fix-vldm-dp tests. Fix misnamed stm32l4xx-fix-all. * testsuite/ld-arm/stm32l4xx-fix-vldm-dp.s: New tests for multiple loads with DP registers. * testsuite/ld-arm/stm32l4xx-fix-vldm-dp.d: New reference file. * testsuite/ld-arm/stm32l4xx-fix-vldm.s: Add missing comment. * testsuite/ld-arm/stm32l4xx-fix-all.s: Add tests for multiple loads with DP registers. * testsuite/ld-arm/stm32l4xx-fix-all.d: Update reference.
50 lines
1.5 KiB
Makefile
50 lines
1.5 KiB
Makefile
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.*: file format elf32-littlearm.*
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Disassembly of section \.text:
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00008000 <__stm32l4xx_veneer_0>:
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8000: ecba 1b08 vldmia sl!, {d1-d4}
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8004: ecba 5b08 vldmia sl!, {d5-d8}
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8008: ecba 9b08 vldmia sl!, {d9-d12}
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800c: ecba db06 vldmia sl!, {d13-d15}
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8010: f1aa 0a78 sub\.w sl, sl, #120 ; 0x78
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8014: f000 b826 b\.w 8064 <__stm32l4xx_veneer_0_r>
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00008018 <__stm32l4xx_veneer_1>:
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8018: ecb7 5b08 vldmia r7!, {d5-d8}
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801c: ecb7 9b08 vldmia r7!, {d9-d12}
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8020: ecb7 db06 vldmia r7!, {d13-d15}
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8024: f000 b820 b\.w 8068 <__stm32l4xx_veneer_1_r>
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8028: f7f0 a000 udf\.w #0
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802c: f7f0 a000 udf\.w #0
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00008030 <__stm32l4xx_veneer_2>:
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8030: ecbd 1b08 vpop {d1-d4}
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8034: ecbd 5b02 vpop {d5}
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8038: f000 b818 b\.w 806c <__stm32l4xx_veneer_2_r>
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803c: f7f0 a000 udf\.w #0
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8040: f7f0 a000 udf\.w #0
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8044: f7f0 a000 udf\.w #0
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00008048 <__stm32l4xx_veneer_3>:
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8048: ed3c 1b08 vldmdb ip!, {d1-d4}
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804c: ed3c 5b08 vldmdb ip!, {d5-d8}
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8050: ed3c 9b08 vldmdb ip!, {d9-d12}
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8054: ed3c db06 vldmdb ip!, {d13-d15}
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8058: f000 b80a b\.w 8070 <__stm32l4xx_veneer_3_r>
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805c: f7f0 a000 udf\.w #0
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00008060 <_start>:
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8060: f7ff bfce b\.w 8000 <__stm32l4xx_veneer_0>
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00008064 <__stm32l4xx_veneer_0_r>:
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8064: f7ff bfd8 b\.w 8018 <__stm32l4xx_veneer_1>
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00008068 <__stm32l4xx_veneer_1_r>:
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8068: f7ff bfe2 b\.w 8030 <__stm32l4xx_veneer_2>
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0000806c <__stm32l4xx_veneer_2_r>:
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806c: f7ff bfec b\.w 8048 <__stm32l4xx_veneer_3>
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