mirror of
https://sourceware.org/git/binutils-gdb.git
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1942a04836
bfd/
* elfnn-riscv.c: Indent, labels and GNU coding standards tidy,
also aligned the code.
gas/
* config/tc-riscv.c: Indent and GNU coding standards tidy,
also aligned the code.
* config/tc-riscv.h: Likewise.
include/
* opcode/riscv.h: Indent and GNU coding standards tidy,
also aligned the code.
opcodes/
* riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
(riscv_fpr_names_abi): Likewise.
(riscv_opcodes): Likewise.
(riscv_insn_types): Likewise.
503 lines
17 KiB
C
503 lines
17 KiB
C
/* riscv.h. RISC-V opcode list for GDB, the GNU debugger.
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Copyright (C) 2011-2021 Free Software Foundation, Inc.
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Contributed by Andrew Waterman
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This file is part of GDB, GAS, and the GNU binutils.
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GDB, GAS, and the GNU binutils are free software; you can redistribute
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them and/or modify them under the terms of the GNU General Public
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License as published by the Free Software Foundation; either version
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3, or (at your option) any later version.
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GDB, GAS, and the GNU binutils are distributed in the hope that they
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will be useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; see the file COPYING3. If not,
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see <http://www.gnu.org/licenses/>. */
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#ifndef _RISCV_H_
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#define _RISCV_H_
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#include "riscv-opc.h"
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#include <stdlib.h>
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#include <stdint.h>
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typedef uint64_t insn_t;
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static inline unsigned int riscv_insn_length (insn_t insn)
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{
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if ((insn & 0x3) != 0x3) /* RVC instructions. */
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return 2;
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if ((insn & 0x1f) != 0x1f) /* 32-bit instructions. */
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return 4;
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if ((insn & 0x3f) == 0x1f) /* 48-bit instructions. */
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return 6;
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if ((insn & 0x7f) == 0x3f) /* 64-bit instructions. */
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return 8;
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/* Longer instructions not supported at the moment. */
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return 2;
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}
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static const char * const riscv_rm[8] =
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{
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"rne", "rtz", "rdn", "rup", "rmm", 0, 0, "dyn"
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};
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static const char * const riscv_pred_succ[16] =
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{
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0, "w", "r", "rw", "o", "ow", "or", "orw",
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"i", "iw", "ir", "irw", "io", "iow", "ior", "iorw"
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};
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#define RVC_JUMP_BITS 11
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#define RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN)
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#define RVC_BRANCH_BITS 8
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#define RVC_BRANCH_REACH ((1ULL << RVC_BRANCH_BITS) * RISCV_BRANCH_ALIGN)
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#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1))
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#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
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#define EXTRACT_ITYPE_IMM(x) \
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(RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12))
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#define EXTRACT_STYPE_IMM(x) \
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(RV_X(x, 7, 5) | (RV_X(x, 25, 7) << 5) | (RV_IMM_SIGN(x) << 12))
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#define EXTRACT_SBTYPE_IMM(x) \
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((RV_X(x, 8, 4) << 1) | (RV_X(x, 25, 6) << 5) | (RV_X(x, 7, 1) << 11) | (RV_IMM_SIGN(x) << 12))
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#define EXTRACT_UTYPE_IMM(x) \
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((RV_X(x, 12, 20) << 12) | (RV_IMM_SIGN(x) << 32))
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#define EXTRACT_UJTYPE_IMM(x) \
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((RV_X(x, 21, 10) << 1) | (RV_X(x, 20, 1) << 11) | (RV_X(x, 12, 8) << 12) | (RV_IMM_SIGN(x) << 20))
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#define EXTRACT_RVC_IMM(x) \
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(RV_X(x, 2, 5) | (-RV_X(x, 12, 1) << 5))
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#define EXTRACT_RVC_LUI_IMM(x) \
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(EXTRACT_RVC_IMM (x) << RISCV_IMM_BITS)
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#define EXTRACT_RVC_SIMM3(x) \
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(RV_X(x, 10, 2) | (-RV_X(x, 12, 1) << 2))
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#define EXTRACT_RVC_UIMM8(x) \
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(RV_X(x, 5, 8))
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#define EXTRACT_RVC_ADDI4SPN_IMM(x) \
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((RV_X(x, 6, 1) << 2) | (RV_X(x, 5, 1) << 3) | (RV_X(x, 11, 2) << 4) | (RV_X(x, 7, 4) << 6))
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#define EXTRACT_RVC_ADDI16SP_IMM(x) \
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((RV_X(x, 6, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 1) << 6) | (RV_X(x, 3, 2) << 7) | (-RV_X(x, 12, 1) << 9))
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#define EXTRACT_RVC_LW_IMM(x) \
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((RV_X(x, 6, 1) << 2) | (RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 1) << 6))
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#define EXTRACT_RVC_LD_IMM(x) \
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((RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 2) << 6))
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#define EXTRACT_RVC_LWSP_IMM(x) \
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((RV_X(x, 4, 3) << 2) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 2) << 6))
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#define EXTRACT_RVC_LDSP_IMM(x) \
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((RV_X(x, 5, 2) << 3) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 3) << 6))
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#define EXTRACT_RVC_SWSP_IMM(x) \
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((RV_X(x, 9, 4) << 2) | (RV_X(x, 7, 2) << 6))
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#define EXTRACT_RVC_SDSP_IMM(x) \
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((RV_X(x, 10, 3) << 3) | (RV_X(x, 7, 3) << 6))
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#define EXTRACT_RVC_B_IMM(x) \
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((RV_X(x, 3, 2) << 1) | (RV_X(x, 10, 2) << 3) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 2) << 6) | (-RV_X(x, 12, 1) << 8))
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#define EXTRACT_RVC_J_IMM(x) \
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((RV_X(x, 3, 3) << 1) | (RV_X(x, 11, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 9, 2) << 8) | (RV_X(x, 8, 1) << 10) | (-RV_X(x, 12, 1) << 11))
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#define ENCODE_ITYPE_IMM(x) \
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(RV_X(x, 0, 12) << 20)
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#define ENCODE_STYPE_IMM(x) \
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((RV_X(x, 0, 5) << 7) | (RV_X(x, 5, 7) << 25))
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#define ENCODE_SBTYPE_IMM(x) \
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((RV_X(x, 1, 4) << 8) | (RV_X(x, 5, 6) << 25) | (RV_X(x, 11, 1) << 7) | (RV_X(x, 12, 1) << 31))
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#define ENCODE_UTYPE_IMM(x) \
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(RV_X(x, 12, 20) << 12)
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#define ENCODE_UJTYPE_IMM(x) \
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((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31))
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#define ENCODE_RVC_IMM(x) \
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((RV_X(x, 0, 5) << 2) | (RV_X(x, 5, 1) << 12))
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#define ENCODE_RVC_LUI_IMM(x) \
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ENCODE_RVC_IMM ((x) >> RISCV_IMM_BITS)
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#define ENCODE_RVC_SIMM3(x) \
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(RV_X(x, 0, 3) << 10)
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#define ENCODE_RVC_UIMM8(x) \
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(RV_X(x, 0, 8) << 5)
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#define ENCODE_RVC_ADDI4SPN_IMM(x) \
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((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 1) << 5) | (RV_X(x, 4, 2) << 11) | (RV_X(x, 6, 4) << 7))
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#define ENCODE_RVC_ADDI16SP_IMM(x) \
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((RV_X(x, 4, 1) << 6) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 5) | (RV_X(x, 7, 2) << 3) | (RV_X(x, 9, 1) << 12))
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#define ENCODE_RVC_LW_IMM(x) \
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((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 1) << 5))
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#define ENCODE_RVC_LD_IMM(x) \
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((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 2) << 5))
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#define ENCODE_RVC_LWSP_IMM(x) \
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((RV_X(x, 2, 3) << 4) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 2) << 2))
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#define ENCODE_RVC_LDSP_IMM(x) \
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((RV_X(x, 3, 2) << 5) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 3) << 2))
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#define ENCODE_RVC_SWSP_IMM(x) \
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((RV_X(x, 2, 4) << 9) | (RV_X(x, 6, 2) << 7))
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#define ENCODE_RVC_SDSP_IMM(x) \
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((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 3) << 7))
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#define ENCODE_RVC_B_IMM(x) \
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((RV_X(x, 1, 2) << 3) | (RV_X(x, 3, 2) << 10) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 2) << 5) | (RV_X(x, 8, 1) << 12))
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#define ENCODE_RVC_J_IMM(x) \
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((RV_X(x, 1, 3) << 3) | (RV_X(x, 4, 1) << 11) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 8, 2) << 9) | (RV_X(x, 10, 1) << 8) | (RV_X(x, 11, 1) << 12))
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#define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
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#define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
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#define VALID_SBTYPE_IMM(x) (EXTRACT_SBTYPE_IMM(ENCODE_SBTYPE_IMM(x)) == (x))
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#define VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x))
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#define VALID_UJTYPE_IMM(x) (EXTRACT_UJTYPE_IMM(ENCODE_UJTYPE_IMM(x)) == (x))
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#define VALID_RVC_IMM(x) (EXTRACT_RVC_IMM(ENCODE_RVC_IMM(x)) == (x))
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#define VALID_RVC_LUI_IMM(x) (ENCODE_RVC_LUI_IMM(x) != 0 && EXTRACT_RVC_LUI_IMM(ENCODE_RVC_LUI_IMM(x)) == (x))
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#define VALID_RVC_SIMM3(x) (EXTRACT_RVC_SIMM3(ENCODE_RVC_SIMM3(x)) == (x))
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#define VALID_RVC_UIMM8(x) (EXTRACT_RVC_UIMM8(ENCODE_RVC_UIMM8(x)) == (x))
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#define VALID_RVC_ADDI4SPN_IMM(x) (EXTRACT_RVC_ADDI4SPN_IMM(ENCODE_RVC_ADDI4SPN_IMM(x)) == (x))
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#define VALID_RVC_ADDI16SP_IMM(x) (EXTRACT_RVC_ADDI16SP_IMM(ENCODE_RVC_ADDI16SP_IMM(x)) == (x))
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#define VALID_RVC_LW_IMM(x) (EXTRACT_RVC_LW_IMM(ENCODE_RVC_LW_IMM(x)) == (x))
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#define VALID_RVC_LD_IMM(x) (EXTRACT_RVC_LD_IMM(ENCODE_RVC_LD_IMM(x)) == (x))
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#define VALID_RVC_LWSP_IMM(x) (EXTRACT_RVC_LWSP_IMM(ENCODE_RVC_LWSP_IMM(x)) == (x))
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#define VALID_RVC_LDSP_IMM(x) (EXTRACT_RVC_LDSP_IMM(ENCODE_RVC_LDSP_IMM(x)) == (x))
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#define VALID_RVC_SWSP_IMM(x) (EXTRACT_RVC_SWSP_IMM(ENCODE_RVC_SWSP_IMM(x)) == (x))
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#define VALID_RVC_SDSP_IMM(x) (EXTRACT_RVC_SDSP_IMM(ENCODE_RVC_SDSP_IMM(x)) == (x))
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#define VALID_RVC_B_IMM(x) (EXTRACT_RVC_B_IMM(ENCODE_RVC_B_IMM(x)) == (x))
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#define VALID_RVC_J_IMM(x) (EXTRACT_RVC_J_IMM(ENCODE_RVC_J_IMM(x)) == (x))
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#define RISCV_RTYPE(insn, rd, rs1, rs2) \
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((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2))
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#define RISCV_ITYPE(insn, rd, rs1, imm) \
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((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ENCODE_ITYPE_IMM(imm))
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#define RISCV_STYPE(insn, rs1, rs2, imm) \
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((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_STYPE_IMM(imm))
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#define RISCV_SBTYPE(insn, rs1, rs2, target) \
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((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_SBTYPE_IMM(target))
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#define RISCV_UTYPE(insn, rd, bigimm) \
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((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UTYPE_IMM(bigimm))
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#define RISCV_UJTYPE(insn, rd, target) \
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((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UJTYPE_IMM(target))
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#define RISCV_NOP RISCV_ITYPE(ADDI, 0, 0, 0)
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#define RVC_NOP MATCH_C_ADDI
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#define RISCV_CONST_HIGH_PART(VALUE) \
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(((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
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#define RISCV_CONST_LOW_PART(VALUE) ((VALUE) - RISCV_CONST_HIGH_PART (VALUE))
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#define RISCV_PCREL_HIGH_PART(VALUE, PC) RISCV_CONST_HIGH_PART((VALUE) - (PC))
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#define RISCV_PCREL_LOW_PART(VALUE, PC) RISCV_CONST_LOW_PART((VALUE) - (PC))
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#define RISCV_JUMP_BITS RISCV_BIGIMM_BITS
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#define RISCV_JUMP_ALIGN_BITS 1
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#define RISCV_JUMP_ALIGN (1 << RISCV_JUMP_ALIGN_BITS)
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#define RISCV_JUMP_REACH ((1ULL << RISCV_JUMP_BITS) * RISCV_JUMP_ALIGN)
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#define RISCV_IMM_BITS 12
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#define RISCV_BIGIMM_BITS (32 - RISCV_IMM_BITS)
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#define RISCV_IMM_REACH (1LL << RISCV_IMM_BITS)
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#define RISCV_BIGIMM_REACH (1LL << RISCV_BIGIMM_BITS)
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#define RISCV_RVC_IMM_REACH (1LL << 6)
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#define RISCV_BRANCH_BITS RISCV_IMM_BITS
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#define RISCV_BRANCH_ALIGN_BITS RISCV_JUMP_ALIGN_BITS
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#define RISCV_BRANCH_ALIGN (1 << RISCV_BRANCH_ALIGN_BITS)
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#define RISCV_BRANCH_REACH (RISCV_IMM_REACH * RISCV_BRANCH_ALIGN)
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/* RV fields. */
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#define OP_MASK_OP 0x7f
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#define OP_SH_OP 0
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#define OP_MASK_RS2 0x1f
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#define OP_SH_RS2 20
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#define OP_MASK_RS1 0x1f
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#define OP_SH_RS1 15
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#define OP_MASK_RS3 0x1fU
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#define OP_SH_RS3 27
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#define OP_MASK_RD 0x1f
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#define OP_SH_RD 7
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#define OP_MASK_SHAMT 0x3f
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#define OP_SH_SHAMT 20
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#define OP_MASK_SHAMTW 0x1f
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#define OP_SH_SHAMTW 20
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#define OP_MASK_RM 0x7
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#define OP_SH_RM 12
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#define OP_MASK_PRED 0xf
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#define OP_SH_PRED 24
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#define OP_MASK_SUCC 0xf
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#define OP_SH_SUCC 20
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#define OP_MASK_AQ 0x1
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#define OP_SH_AQ 26
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#define OP_MASK_RL 0x1
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#define OP_SH_RL 25
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#define OP_MASK_CUSTOM_IMM 0x7fU
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#define OP_SH_CUSTOM_IMM 25
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#define OP_MASK_CSR 0xfffU
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#define OP_SH_CSR 20
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#define OP_MASK_FUNCT3 0x7
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#define OP_SH_FUNCT3 12
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#define OP_MASK_FUNCT7 0x7fU
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#define OP_SH_FUNCT7 25
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#define OP_MASK_FUNCT2 0x3
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#define OP_SH_FUNCT2 25
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/* RVC fields. */
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#define OP_MASK_OP2 0x3
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#define OP_SH_OP2 0
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#define OP_MASK_CRS2 0x1f
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#define OP_SH_CRS2 2
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#define OP_MASK_CRS1S 0x7
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#define OP_SH_CRS1S 7
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#define OP_MASK_CRS2S 0x7
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#define OP_SH_CRS2S 2
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#define OP_MASK_CFUNCT6 0x3f
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#define OP_SH_CFUNCT6 10
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#define OP_MASK_CFUNCT4 0xf
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#define OP_SH_CFUNCT4 12
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#define OP_MASK_CFUNCT3 0x7
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#define OP_SH_CFUNCT3 13
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#define OP_MASK_CFUNCT2 0x3
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#define OP_SH_CFUNCT2 5
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/* ABI names for selected x-registers. */
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#define X_RA 1
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#define X_SP 2
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#define X_GP 3
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#define X_TP 4
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#define X_T0 5
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#define X_T1 6
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#define X_T2 7
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#define X_T3 28
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#define NGPR 32
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#define NFPR 32
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/* These fake label defines are use by both the assembler, and
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libopcodes. The assembler uses this when it needs to generate a fake
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label, and libopcodes uses it to hide the fake labels in its output. */
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#define RISCV_FAKE_LABEL_NAME ".L0 "
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#define RISCV_FAKE_LABEL_CHAR ' '
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/* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
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VALUE << SHIFT. VALUE is evaluated exactly once. */
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#define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
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(STRUCT) = (((STRUCT) & ~((insn_t)(MASK) << (SHIFT))) \
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| ((insn_t)((VALUE) & (MASK)) << (SHIFT)))
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/* Extract bits MASK << SHIFT from STRUCT and shift them right
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SHIFT places. */
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#define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
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(((STRUCT) >> (SHIFT)) & (MASK))
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/* Extract the operand given by FIELD from integer INSN. */
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#define EXTRACT_OPERAND(FIELD, INSN) \
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EXTRACT_BITS ((INSN), OP_MASK_##FIELD, OP_SH_##FIELD)
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/* The maximal number of subset can be required. */
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#define MAX_SUBSET_NUM 4
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/* All RISC-V instructions belong to at least one of these classes. */
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enum riscv_insn_class
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{
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INSN_CLASS_NONE,
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|
INSN_CLASS_I,
|
|
INSN_CLASS_C,
|
|
INSN_CLASS_A,
|
|
INSN_CLASS_M,
|
|
INSN_CLASS_F,
|
|
INSN_CLASS_D,
|
|
INSN_CLASS_Q,
|
|
INSN_CLASS_F_AND_C,
|
|
INSN_CLASS_D_AND_C,
|
|
INSN_CLASS_ZICSR,
|
|
INSN_CLASS_ZIFENCEI,
|
|
INSN_CLASS_ZIHINTPAUSE,
|
|
INSN_CLASS_ZBA,
|
|
INSN_CLASS_ZBB,
|
|
INSN_CLASS_ZBC,
|
|
INSN_CLASS_ZBA_OR_ZBB,
|
|
};
|
|
|
|
/* This structure holds information for a particular instruction. */
|
|
struct riscv_opcode
|
|
{
|
|
/* The name of the instruction. */
|
|
const char *name;
|
|
|
|
/* The requirement of xlen for the instruction, 0 if no requirement. */
|
|
unsigned xlen_requirement;
|
|
|
|
/* Class to which this instruction belongs. Used to decide whether or
|
|
not this instruction is legal in the current -march context. */
|
|
enum riscv_insn_class insn_class;
|
|
|
|
/* A string describing the arguments for this instruction. */
|
|
const char *args;
|
|
|
|
/* The basic opcode for the instruction. When assembling, this
|
|
opcode is modified by the arguments to produce the actual opcode
|
|
that is used. If pinfo is INSN_MACRO, then this is 0. */
|
|
insn_t match;
|
|
|
|
/* If pinfo is not INSN_MACRO, then this is a bit mask for the
|
|
relevant portions of the opcode when disassembling. If the
|
|
actual opcode anded with the match field equals the opcode field,
|
|
then we have found the correct instruction. If pinfo is
|
|
INSN_MACRO, then this field is the macro identifier. */
|
|
insn_t mask;
|
|
|
|
/* A function to determine if a word corresponds to this instruction.
|
|
Usually, this computes ((word & mask) == match). */
|
|
int (*match_func) (const struct riscv_opcode *op, insn_t word);
|
|
|
|
/* For a macro, this is INSN_MACRO. Otherwise, it is a collection
|
|
of bits describing the instruction, notably any relevant hazard
|
|
information. */
|
|
unsigned long pinfo;
|
|
};
|
|
|
|
/* The current supported ISA spec versions. */
|
|
enum riscv_isa_spec_class
|
|
{
|
|
ISA_SPEC_CLASS_NONE,
|
|
|
|
ISA_SPEC_CLASS_2P2,
|
|
ISA_SPEC_CLASS_20190608,
|
|
ISA_SPEC_CLASS_20191213,
|
|
ISA_SPEC_CLASS_DRAFT
|
|
};
|
|
|
|
#define RISCV_UNKNOWN_VERSION -1
|
|
|
|
/* This structure holds version information for specific ISA. */
|
|
struct riscv_ext_version
|
|
{
|
|
const char *name;
|
|
enum riscv_isa_spec_class isa_spec_class;
|
|
int major_version;
|
|
int minor_version;
|
|
};
|
|
|
|
/* All RISC-V CSR belong to one of these classes. */
|
|
enum riscv_csr_class
|
|
{
|
|
CSR_CLASS_NONE,
|
|
|
|
CSR_CLASS_I,
|
|
CSR_CLASS_I_32, /* RV32 only. */
|
|
CSR_CLASS_F, /* F extension only. */
|
|
CSR_CLASS_DEBUG /* Debug CSR. */
|
|
};
|
|
|
|
/* The current supported privilege spec versions. */
|
|
enum riscv_priv_spec_class
|
|
{
|
|
PRIV_SPEC_CLASS_NONE,
|
|
|
|
PRIV_SPEC_CLASS_1P9P1,
|
|
PRIV_SPEC_CLASS_1P10,
|
|
PRIV_SPEC_CLASS_1P11,
|
|
PRIV_SPEC_CLASS_DRAFT
|
|
};
|
|
|
|
/* This structure holds all restricted conditions for a CSR. */
|
|
struct riscv_csr_extra
|
|
{
|
|
/* Class to which this CSR belongs. Used to decide whether or
|
|
not this CSR is legal in the current -march context. */
|
|
enum riscv_csr_class csr_class;
|
|
|
|
/* CSR may have differnet numbers in the previous priv spec. */
|
|
unsigned address;
|
|
|
|
/* Record the CSR is defined/valid in which versions. */
|
|
enum riscv_priv_spec_class define_version;
|
|
|
|
/* Record the CSR is aborted/invalid from which versions. If it isn't
|
|
aborted in the current version, then it should be CSR_CLASS_VDRAFT. */
|
|
enum riscv_priv_spec_class abort_version;
|
|
|
|
/* The CSR may have more than one setting. */
|
|
struct riscv_csr_extra *next;
|
|
};
|
|
|
|
/* Instruction is a simple alias (e.g. "mv" for "addi"). */
|
|
#define INSN_ALIAS 0x00000001
|
|
|
|
/* These are for setting insn_info fields.
|
|
|
|
Nonbranch is the default. Noninsn is used only if there is no match.
|
|
There are no condjsr or dref2 instructions. So that leaves condbranch,
|
|
branch, jsr, and dref that we need to handle here, encoded in 3 bits. */
|
|
#define INSN_TYPE 0x0000000e
|
|
|
|
/* Instruction is an unconditional branch. */
|
|
#define INSN_BRANCH 0x00000002
|
|
/* Instruction is a conditional branch. */
|
|
#define INSN_CONDBRANCH 0x00000004
|
|
/* Instruction is a jump to subroutine. */
|
|
#define INSN_JSR 0x00000006
|
|
/* Instruction is a data reference. */
|
|
#define INSN_DREF 0x00000008
|
|
|
|
/* We have 5 data reference sizes, which we can encode in 3 bits. */
|
|
#define INSN_DATA_SIZE 0x00000070
|
|
#define INSN_DATA_SIZE_SHIFT 4
|
|
#define INSN_1_BYTE 0x00000010
|
|
#define INSN_2_BYTE 0x00000020
|
|
#define INSN_4_BYTE 0x00000030
|
|
#define INSN_8_BYTE 0x00000040
|
|
#define INSN_16_BYTE 0x00000050
|
|
|
|
/* Instruction is actually a macro. It should be ignored by the
|
|
disassembler, and requires special treatment by the assembler. */
|
|
#define INSN_MACRO 0xffffffff
|
|
|
|
/* This is a list of macro expanded instructions. */
|
|
enum
|
|
{
|
|
M_LA,
|
|
M_LLA,
|
|
M_LA_TLS_GD,
|
|
M_LA_TLS_IE,
|
|
M_LB,
|
|
M_LBU,
|
|
M_LH,
|
|
M_LHU,
|
|
M_LW,
|
|
M_LWU,
|
|
M_LD,
|
|
M_SB,
|
|
M_SH,
|
|
M_SW,
|
|
M_SD,
|
|
M_FLW,
|
|
M_FLD,
|
|
M_FLQ,
|
|
M_FSW,
|
|
M_FSD,
|
|
M_FSQ,
|
|
M_CALL,
|
|
M_J,
|
|
M_LI,
|
|
M_ZEXTH,
|
|
M_ZEXTW,
|
|
M_SEXTB,
|
|
M_SEXTH,
|
|
M_NUM_MACROS
|
|
};
|
|
|
|
|
|
extern const char * const riscv_gpr_names_numeric[NGPR];
|
|
extern const char * const riscv_gpr_names_abi[NGPR];
|
|
extern const char * const riscv_fpr_names_numeric[NFPR];
|
|
extern const char * const riscv_fpr_names_abi[NFPR];
|
|
|
|
extern const struct riscv_opcode riscv_opcodes[];
|
|
extern const struct riscv_opcode riscv_insn_types[];
|
|
extern const struct riscv_ext_version riscv_ext_version_table[];
|
|
|
|
extern int
|
|
riscv_get_isa_spec_class (const char *, enum riscv_isa_spec_class *);
|
|
|
|
#endif /* _RISCV_H_ */
|