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ChangeLog: Add target riscv to --enable-gprofng.
2024-07-04 Yixuan Chen <chenyixuan@iscas.ac.cn>
* configure: Add riscv.
* configure.ac: Add riscv.
gprofng/ChangeLog: Minimal support gprofng for riscv.
2024-07-04 Yixuan Chen <chenyixuan@iscas.ac.cn>
* gprofng/common/core_pcbe.c (core_pcbe_init): Add RISC-V vendor conditon.
(defined): Add riscv.
* gprofng/common/cpuid.c (defined): Add risc-v hwprobe.
* gprofng/common/gp-defs.h (TOK_A_RISCV): Add riscv.
(defined): Add riscv.
(ARCH_RISCV): Add riscv.
* gprofng/common/hwc_cpus.h: Add RISC-V vendor.
* gprofng/common/hwcfuncs.h (HW_INTERVAL_TYPE): Remove useless defination.
* gprofng/configure: Add riscv.
* gprofng/configure.ac: Add riscv.
* gprofng/libcollector/hwprofile.h (ARCH): Add RISC-V register.
(CONTEXT_PC): Add RISC-V register.
(CONTEXT_FP): Add RISC-V register.
(CONTEXT_SP): Add RISC-V register.
(SETFUNCTIONCONTEXT):
* gprofng/libcollector/libcol_util.c (__collector_util_init): Fix libc open condition.
* gprofng/libcollector/libcol_util.h (ARCH): Add RISC-V.
* gprofng/libcollector/unwind.c (ARCH): Add RISC-V register.
(GET_PC): Add RISC-V register.
(GET_SP): Add RISC-V register.
(GET_FP): Add RISC-V register.
(FILL_CONTEXT):
* gprofng/src/DbeSession.cc (ARCH): Add RISC-V.
* gprofng/src/Disasm.cc (Disasm::disasm_open): Add RISC-V.
* gprofng/src/Experiment.cc (Experiment::ExperimentHandler::startElement): Add RISC-V.
* gprofng/src/checks.cc (ARCH): Add RISC-V.
* gprofng/src/collctrl.cc (defined): Set risc-v cpu frequency to 1000MHz as default for now, will fix when I find a better method to get cpu frequency.
(read_cpuinfo): Add "mvendorid" condition according to risc-v /proc/cpuinfo file content.
* gprofng/src/dbe_types.h (enum Platform_t): Add RISC-V.
100 lines
3.3 KiB
C
100 lines
3.3 KiB
C
/* Copyright (C) 2021-2024 Free Software Foundation, Inc.
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Contributed by Oracle.
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This file is part of GNU Binutils.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#ifndef _HWPROFILE_H
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#define _HWPROFILE_H
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#include <data_pckts.h>
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typedef struct Hwcntr_packet
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{ /* HW counter profiling packet */
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Common_packet comm;
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uint32_t tag; /* hw counter index, register */
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uint64_t interval; /* overflow value */
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} Hwcntr_packet;
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typedef struct MHwcntr_packet
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{ /* extended (superset) Hwcntr_packet */
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Common_packet comm;
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uint32_t tag; /* hw counter index, register */
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uint64_t interval; /* overflow value */
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Vaddr_type ea_vaddr; /* virtual addr causing HWC event */
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Vaddr_type pc_vaddr; /* candidate eventPC */
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uint64_t ea_paddr; /* physical address for ea_vaddr */
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uint64_t pc_paddr; /* physical address for pc_vaddr */
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uint64_t ea_pagesz; /* pagesz (bytes) for ea_paddr */
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uint64_t pc_pagesz; /* pagesz (bytes) for pc_paddr */
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uint32_t ea_lgrp; /* latency group of ea_paddr */
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uint32_t pc_lgrp; /* latency group of pc_paddr */
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uint32_t lgrp_lwp; /* locality group of lwp */
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uint32_t lgrp_ps; /* locality group of process */
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uint64_t latency; /* latency in cycles (sampling only) */
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uint64_t data_source; /* data source (sampling only) */
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} MHwcntr_packet;
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#if ARCH(SPARC)
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#define CONTEXT_PC MC_PC
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#define CONTEXT_SP MC_O6
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#define CONTEXT_FP MC_O7
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#define SETFUNCTIONCONTEXT(ucp,funcp) \
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(ucp)->uc_mcontext.gregs[CONTEXT_PC] = (greg_t)(funcp); \
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(ucp)->uc_mcontext.gregs[CONTEXT_SP] = 0; \
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(ucp)->uc_mcontext.gregs[CONTEXT_FP] = 0;
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#elif ARCH(Intel)
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#include <sys/reg.h>
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#if WSIZE(64)
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#define CONTEXT_PC REG_RIP
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#define CONTEXT_FP REG_RBP
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#define CONTEXT_SP REG_RSP
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#elif WSIZE(32)
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#define CONTEXT_PC REG_EIP
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#define CONTEXT_FP REG_EBP
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#define CONTEXT_SP REG_ESP
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#endif /* WSIZE() */
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#define SETFUNCTIONCONTEXT(ucp,funcp) \
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(ucp)->uc_mcontext.gregs[CONTEXT_PC] = (intptr_t)(funcp); \
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(ucp)->uc_mcontext.gregs[CONTEXT_SP] = 0; \
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(ucp)->uc_mcontext.gregs[CONTEXT_FP] = 0;
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#elif ARCH(Aarch64)
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#define CONTEXT_PC 15
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#define CONTEXT_FP 14
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#define CONTEXT_SP 13
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#define SETFUNCTIONCONTEXT(ucp,funcp) \
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(ucp)->uc_mcontext.regs[CONTEXT_PC] = (greg_t)(funcp); \
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(ucp)->uc_mcontext.regs[CONTEXT_SP] = 0; \
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(ucp)->uc_mcontext.regs[CONTEXT_FP] = 0;
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#elif ARCH(RISCV)
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#define CONTEXT_PC REG_PC
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#define CONTEXT_FP 8
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#define CONTEXT_SP 2
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#define SETFUNCTIONCONTEXT(ucp,funcp) \
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(ucp)->uc_mcontext.__gregs[CONTEXT_PC] = (greg_t)(funcp); \
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(ucp)->uc_mcontext.__gregs[CONTEXT_FP] = 0; \
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(ucp)->uc_mcontext.__gregs[CONTEXT_SP] = 0;
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#endif /* ARCH() */
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#endif
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