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ChangeLog: Add target riscv to --enable-gprofng.
2024-07-04 Yixuan Chen <chenyixuan@iscas.ac.cn>
* configure: Add riscv.
* configure.ac: Add riscv.
gprofng/ChangeLog: Minimal support gprofng for riscv.
2024-07-04 Yixuan Chen <chenyixuan@iscas.ac.cn>
* gprofng/common/core_pcbe.c (core_pcbe_init): Add RISC-V vendor conditon.
(defined): Add riscv.
* gprofng/common/cpuid.c (defined): Add risc-v hwprobe.
* gprofng/common/gp-defs.h (TOK_A_RISCV): Add riscv.
(defined): Add riscv.
(ARCH_RISCV): Add riscv.
* gprofng/common/hwc_cpus.h: Add RISC-V vendor.
* gprofng/common/hwcfuncs.h (HW_INTERVAL_TYPE): Remove useless defination.
* gprofng/configure: Add riscv.
* gprofng/configure.ac: Add riscv.
* gprofng/libcollector/hwprofile.h (ARCH): Add RISC-V register.
(CONTEXT_PC): Add RISC-V register.
(CONTEXT_FP): Add RISC-V register.
(CONTEXT_SP): Add RISC-V register.
(SETFUNCTIONCONTEXT):
* gprofng/libcollector/libcol_util.c (__collector_util_init): Fix libc open condition.
* gprofng/libcollector/libcol_util.h (ARCH): Add RISC-V.
* gprofng/libcollector/unwind.c (ARCH): Add RISC-V register.
(GET_PC): Add RISC-V register.
(GET_SP): Add RISC-V register.
(GET_FP): Add RISC-V register.
(FILL_CONTEXT):
* gprofng/src/DbeSession.cc (ARCH): Add RISC-V.
* gprofng/src/Disasm.cc (Disasm::disasm_open): Add RISC-V.
* gprofng/src/Experiment.cc (Experiment::ExperimentHandler::startElement): Add RISC-V.
* gprofng/src/checks.cc (ARCH): Add RISC-V.
* gprofng/src/collctrl.cc (defined): Set risc-v cpu frequency to 1000MHz as default for now, will fix when I find a better method to get cpu frequency.
(read_cpuinfo): Add "mvendorid" condition according to risc-v /proc/cpuinfo file content.
* gprofng/src/dbe_types.h (enum Platform_t): Add RISC-V.
76 lines
2.2 KiB
C
76 lines
2.2 KiB
C
/* Copyright (C) 2021-2024 Free Software Foundation, Inc.
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Contributed by Oracle.
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This file is part of GNU Binutils.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#ifndef _GP_DEFS_H_
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#define _GP_DEFS_H_
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/* Define the ARCH and WSIZE predicates */
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/*
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* The way we define and use predicates is similar to the
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* standard #assert with one important exception:
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* if an argument of a predicate is not known the result
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* is 'false' and we want a compile time error to avoid
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* silent results from typos like ARCH(INTEL), COMPILER(gnu),
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* etc.
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*/
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#define ARCH(x) TOK_A_##x(ARCH)
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#define TOK_A_Aarch64(x) x##_Aarch64
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#define TOK_A_RISCV(x) x##_RISCV
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#define TOK_A_SPARC(x) x##_SPARC
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#define TOK_A_Intel(x) x##_Intel
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#define WSIZE(x) TOK_W_##x(WSIZE)
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#define TOK_W_32(x) x##_32
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#define TOK_W_64(x) x##_64
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#if defined(sparc) || defined(__sparcv9)
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#define ARCH_SPARC 1
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#elif defined(__i386__) || defined(__x86_64)
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#define ARCH_Intel 1
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#elif defined(__aarch64__)
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#define ARCH_Aarch64 1
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#elif defined(__riscv)
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#define ARCH_RISCV 1
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#else
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#error "Undefined platform"
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#endif
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#if defined(__sparcv9) || defined(__x86_64) || defined(__aarch64__) || defined(__riscv)
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#define WSIZE_64 1
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#else
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#define WSIZE_32 1
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#endif
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#ifndef ATTRIBUTE_FALLTHROUGH
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# if (GCC_VERSION >= 7000)
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# define ATTRIBUTE_FALLTHROUGH __attribute__ ((__fallthrough__))
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# else
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# define ATTRIBUTE_FALLTHROUGH /* Fall through */
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# endif
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#endif
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#if defined(__MUSL_LIBC)
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#define ino64_t ino_t
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#define off64_t off_t
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#define fpos64_t fpos_t
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#endif
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#endif
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