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While the concept of a core instruction relates to the idea of instructions that are available irrespective of the presence of architectural extensions, this concept breaks down with the introduction of the Morello architecture. Rather, what is observed in Morello is that when PSTATE.C64 == 1, the A64C_INSN variant becomes the ONLY valid aarch64_opcode variant, with the CORE_INSN variant becoming illegal. Therefore, some way of ruling out the use of such CORE_INSNs is needed. Similarly, some A64C_INSN instructions are only valid for PSTATE.C64 == 1 and are not valid when compiling for Morello A64 mode. At the assembly level, the CORE_INSN and A64C_INSN variants share the same mnemonic, differing only by whether they are passed a general- purpose register argument or its capability counterpart, e.g. * CORE_INSN: adr x0, #0 * A64C_INSN: adr c0, #0 This makes the prospect of combining both insn variants in binutils into a single insn entry in aarch64_opcode_table[], resolving the appropriate operand code (e.g. AARCH64_OPND_Can versus AARCH64_OPND_Rn) at compile time by analyzing the -march and -mabi flags. This approach falls short when dealing with instructions such as `bl' where the core and morello instructions share the same mnemonic but have distinct encodings. A more flexible approach is therefore presented here. Special restrictions to instructions are encoded in the FLAGS field, which can then be used in checks carried out in `md_assemble'. This fixes two issues: 1. Wrong fix suggestions in `output_operand_error_record': - attempting to assemble `adr w0, #0' at present, for example, results in a suggestion that `w0' be changed to `x0' as opposed to `c0'. 2. Purecap only instructions being accepted when assembling without the C64 extension: - `adr c0, #0' is currently accepted when assembling for Hybrid mode. This patch defines the F_NONC64 and F_C64ONLY flags for labellig these instructions in aarch64_opcode.flags, such that unavailable instructions could be identified by cross-referencing this field along with whether C64 is set in the `cpu_variant' aarch64_feature_set variable. When the conditions set by the flag is not met by `cpu_variant', the instruction can be attributed a AARCH64_OPDE_SYNTAX_ERROR, allowing for correct error handling in md_assemble. ChangeLog: * include/opcode/aarch64.h (F_NONC64): New flag. * include/opcode/aarch64.h (F_C64ONLY): Likewise. opcodes/ChangeLog: * aarch64-tbl.h (aarch64_opcode_table): Add F_NONC64 and F_C64ONLY to relevant aarch64_opcodes gas/ChangeLog: * config/tc-aarch64.c (validate_opcode_for_feature): New. (md_assemble): Use `validate_opcode_for_feature' in template selection. * gas/testsuite/gas/aarch64/morello-exclude.l: New testcase. * gas/testsuite/gas/aarch64/morello-exclude.s: Likewise. * gas/testsuite/gas/aarch64/morello-exclude.l: Likewise. * gas/testsuite/gas/aarch64/morello_insn.s: Fix hybrid codegen. |
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| .. | ||
| aarch64.h | ||
| alpha.h | ||
| arc-attrs.h | ||
| arc-func.h | ||
| arc.h | ||
| arm.h | ||
| avr.h | ||
| bfin.h | ||
| cgen.h | ||
| ChangeLog-0415 | ||
| ChangeLog-9103 | ||
| convex.h | ||
| cr16.h | ||
| cris.h | ||
| crx.h | ||
| csky.h | ||
| d10v.h | ||
| d30v.h | ||
| dlx.h | ||
| ft32.h | ||
| h8300.h | ||
| hppa.h | ||
| i386.h | ||
| ia64.h | ||
| m68hc11.h | ||
| m68k.h | ||
| metag.h | ||
| mips.h | ||
| mmix.h | ||
| mn10200.h | ||
| mn10300.h | ||
| moxie.h | ||
| msp430-decode.h | ||
| msp430.h | ||
| nds32.h | ||
| nfp.h | ||
| nios2.h | ||
| nios2r1.h | ||
| nios2r2.h | ||
| np1.h | ||
| ns32k.h | ||
| pdp11.h | ||
| pj.h | ||
| pn.h | ||
| ppc.h | ||
| pru.h | ||
| pyr.h | ||
| riscv-opc.h | ||
| riscv.h | ||
| rl78.h | ||
| rx.h | ||
| s12z.h | ||
| s390.h | ||
| score-datadep.h | ||
| score-inst.h | ||
| sparc.h | ||
| spu-insns.h | ||
| spu.h | ||
| tic4x.h | ||
| tic6x-control-registers.h | ||
| tic6x-insn-formats.h | ||
| tic6x-opcode-table.h | ||
| tic6x.h | ||
| tic30.h | ||
| tic54x.h | ||
| tilegx.h | ||
| tilepro.h | ||
| v850.h | ||
| vax.h | ||
| visium.h | ||
| wasm.h | ||
| xgate.h | ||