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8f46711443
The idea of this change is simple: Populate a data structure, namely "disasm_option_and_arg_t" from "include/dis-asm.h", to encompass the disassembly options and their possible arguments. This will make it easier to manage or extend those options by adapting entries in a data structure, "arc_options". There will be lesser need to hard-code the options in the code itself. Moreover, ARC GDB will use this population function, "disassembler_options_arc ()", to enable the "set disassembler-option" for ARC targets. The gdb change will be in a separate patch though. The changes in this patch can be divided into: 1) Introduction of "disassembler_options_arc ()" that will return a "disasm_option_and_arg_t" structure representing the disassembly options and their likely arguments. 2) New data type "arc_options_arg_t" and new data "arc_options". These are the internals for keeping track of options and arguments entries that can easily be extended. 3) To print the options, the "print_arc_disassembler_options ()" has been adjusted to use this dynamically built structure instead of having them hard-coded inside. To see this in effect, one can look into the output of: $ ./binutils/objdump --help ... The following ARC specific disassembler options are... ... include/ChangeLog: * dis-asm.h (disassembler_options_arc): New prototype. opcodes/ChangeLog: * arc-dis.c (arc_option_arg_t): New enumeration. (arc_options): New variable. (disassembler_options_arc): New function. (print_arc_disassembler_options): Reimplement in terms of "disassembler_options_arc".
1635 lines
42 KiB
C
1635 lines
42 KiB
C
/* Instruction printing code for the ARC.
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Copyright (C) 1994-2021 Free Software Foundation, Inc.
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Contributed by Claudiu Zissulescu (claziss@synopsys.com)
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This file is part of libopcodes.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include "sysdep.h"
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#include <stdio.h>
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#include <assert.h>
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#include "dis-asm.h"
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#include "opcode/arc.h"
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#include "elf/arc.h"
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#include "arc-dis.h"
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#include "arc-ext.h"
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#include "elf-bfd.h"
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#include "libiberty.h"
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#include "opintl.h"
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/* Structure used to iterate over, and extract the values for, operands of
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an opcode. */
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struct arc_operand_iterator
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{
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/* The complete instruction value to extract operands from. */
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unsigned long long insn;
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/* The LIMM if this is being tracked separately. This field is only
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valid if we find the LIMM operand in the operand list. */
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unsigned limm;
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/* The opcode this iterator is operating on. */
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const struct arc_opcode *opcode;
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/* The index into the opcodes operand index list. */
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const unsigned char *opidx;
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};
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/* A private data used by ARC decoder. */
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struct arc_disassemble_info
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{
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/* The current disassembled arc opcode. */
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const struct arc_opcode *opcode;
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/* Instruction length w/o limm field. */
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unsigned insn_len;
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/* TRUE if we have limm. */
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bool limm_p;
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/* LIMM value, if exists. */
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unsigned limm;
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/* Condition code, if exists. */
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unsigned condition_code;
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/* Writeback mode. */
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unsigned writeback_mode;
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/* Number of operands. */
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unsigned operands_count;
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struct arc_insn_operand operands[MAX_INSN_ARGS];
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};
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/* Globals variables. */
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static const char * const regnames[64] =
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{
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
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"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
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"r24", "r25", "gp", "fp", "sp", "ilink", "r30", "blink",
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"r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
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"r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
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"r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
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"r56", "r57", "r58", "r59", "lp_count", "reserved", "LIMM", "pcl"
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};
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static const char * const addrtypenames[ARC_NUM_ADDRTYPES] =
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{
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"bd", "jid", "lbd", "mbd", "sd", "sm", "xa", "xd",
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"cd", "cbd", "cjid", "clbd", "cm", "csd", "cxa", "cxd"
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};
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static int addrtypenames_max = ARC_NUM_ADDRTYPES - 1;
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static const char * const addrtypeunknown = "unknown";
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/* This structure keeps track which instruction class(es)
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should be ignored durring disassembling. */
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typedef struct skipclass
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{
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insn_class_t insn_class;
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insn_subclass_t subclass;
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struct skipclass *nxt;
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} skipclass_t, *linkclass;
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/* Intial classes of instructions to be consider first when
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disassembling. */
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static linkclass decodelist = NULL;
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/* ISA mask value enforced via disassembler info options. ARC_OPCODE_NONE
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value means that no CPU is enforced. */
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static unsigned enforced_isa_mask = ARC_OPCODE_NONE;
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/* True if we want to print using only hex numbers. */
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static bool print_hex = false;
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/* Macros section. */
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#ifdef DEBUG
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# define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
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#else
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# define pr_debug(fmt, args...)
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#endif
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#define ARRANGE_ENDIAN(info, buf) \
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(info->endian == BFD_ENDIAN_LITTLE ? bfd_getm32 (bfd_getl32 (buf)) \
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: bfd_getb32 (buf))
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#define BITS(word,s,e) (((word) >> (s)) & ((1ull << ((e) - (s)) << 1) - 1))
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#define OPCODE_32BIT_INSN(word) (BITS ((word), 27, 31))
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/* Functions implementation. */
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/* Initialize private data. */
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static bool
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init_arc_disasm_info (struct disassemble_info *info)
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{
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struct arc_disassemble_info *arc_infop
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= calloc (sizeof (*arc_infop), 1);
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if (arc_infop == NULL)
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return false;
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info->private_data = arc_infop;
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return true;
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}
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/* Add a new element to the decode list. */
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static void
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add_to_decodelist (insn_class_t insn_class,
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insn_subclass_t subclass)
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{
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linkclass t = (linkclass) xmalloc (sizeof (skipclass_t));
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t->insn_class = insn_class;
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t->subclass = subclass;
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t->nxt = decodelist;
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decodelist = t;
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}
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/* Return TRUE if we need to skip the opcode from being
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disassembled. */
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static bool
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skip_this_opcode (const struct arc_opcode *opcode)
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{
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linkclass t = decodelist;
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/* Check opcode for major 0x06, return if it is not in. */
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if (arc_opcode_len (opcode) == 4
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&& (OPCODE_32BIT_INSN (opcode->opcode) != 0x06
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/* Can be an APEX extensions. */
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&& OPCODE_32BIT_INSN (opcode->opcode) != 0x07))
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return false;
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/* or not a known truble class. */
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switch (opcode->insn_class)
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{
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case FLOAT:
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case DSP:
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case ARITH:
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case MPY:
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break;
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default:
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return false;
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}
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while (t != NULL)
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{
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if ((t->insn_class == opcode->insn_class)
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&& (t->subclass == opcode->subclass))
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return false;
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t = t->nxt;
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}
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return true;
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}
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static bfd_vma
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bfd_getm32 (unsigned int data)
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{
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bfd_vma value = 0;
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value = ((data & 0xff00) | (data & 0xff)) << 16;
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value |= ((data & 0xff0000) | (data & 0xff000000)) >> 16;
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return value;
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}
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static bool
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special_flag_p (const char *opname,
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const char *flgname)
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{
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const struct arc_flag_special *flg_spec;
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unsigned i, j, flgidx;
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for (i = 0; i < arc_num_flag_special; i++)
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{
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flg_spec = &arc_flag_special_cases[i];
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if (strcmp (opname, flg_spec->name))
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continue;
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/* Found potential special case instruction. */
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for (j=0;; ++j)
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{
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flgidx = flg_spec->flags[j];
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if (flgidx == 0)
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break; /* End of the array. */
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if (strcmp (flgname, arc_flag_operands[flgidx].name) == 0)
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return true;
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}
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}
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return false;
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}
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/* Find opcode from ARC_TABLE given the instruction described by INSN and
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INSNLEN. The ISA_MASK restricts the possible matches in ARC_TABLE. */
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static const struct arc_opcode *
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find_format_from_table (struct disassemble_info *info,
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const struct arc_opcode *arc_table,
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unsigned long long insn,
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unsigned int insn_len,
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unsigned isa_mask,
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bool *has_limm,
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bool overlaps)
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{
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unsigned int i = 0;
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const struct arc_opcode *opcode = NULL;
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const struct arc_opcode *t_op = NULL;
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const unsigned char *opidx;
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const unsigned char *flgidx;
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bool warn_p = false;
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do
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{
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bool invalid = false;
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opcode = &arc_table[i++];
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if (!(opcode->cpu & isa_mask))
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continue;
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if (arc_opcode_len (opcode) != (int) insn_len)
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continue;
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if ((insn & opcode->mask) != opcode->opcode)
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continue;
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*has_limm = false;
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/* Possible candidate, check the operands. */
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for (opidx = opcode->operands; *opidx; opidx++)
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{
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int value, limmind;
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const struct arc_operand *operand = &arc_operands[*opidx];
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if (operand->flags & ARC_OPERAND_FAKE)
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continue;
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if (operand->extract)
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value = (*operand->extract) (insn, &invalid);
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else
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value = (insn >> operand->shift) & ((1ull << operand->bits) - 1);
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/* Check for LIMM indicator. If it is there, then make sure
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we pick the right format. */
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limmind = (isa_mask & ARC_OPCODE_ARCV2) ? 0x1E : 0x3E;
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if (operand->flags & ARC_OPERAND_IR
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&& !(operand->flags & ARC_OPERAND_LIMM))
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{
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if ((value == 0x3E && insn_len == 4)
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|| (value == limmind && insn_len == 2))
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{
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invalid = true;
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break;
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}
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}
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if (operand->flags & ARC_OPERAND_LIMM
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&& !(operand->flags & ARC_OPERAND_DUPLICATE))
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*has_limm = true;
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}
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/* Check the flags. */
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for (flgidx = opcode->flags; *flgidx; flgidx++)
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{
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/* Get a valid flag class. */
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const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
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const unsigned *flgopridx;
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int foundA = 0, foundB = 0;
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unsigned int value;
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/* Check first the extensions. */
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if (cl_flags->flag_class & F_CLASS_EXTEND)
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{
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value = (insn & 0x1F);
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if (arcExtMap_condCodeName (value))
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continue;
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}
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/* Check for the implicit flags. */
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if (cl_flags->flag_class & F_CLASS_IMPLICIT)
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continue;
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for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
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{
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const struct arc_flag_operand *flg_operand =
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&arc_flag_operands[*flgopridx];
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value = (insn >> flg_operand->shift)
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& ((1 << flg_operand->bits) - 1);
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if (value == flg_operand->code)
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foundA = 1;
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if (value)
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foundB = 1;
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}
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if (!foundA && foundB)
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{
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invalid = true;
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break;
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}
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}
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if (invalid)
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continue;
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if (insn_len == 4
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&& overlaps)
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{
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warn_p = true;
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t_op = opcode;
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if (skip_this_opcode (opcode))
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continue;
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}
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/* The instruction is valid. */
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return opcode;
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}
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while (opcode->mask);
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if (warn_p)
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{
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info->fprintf_func (info->stream,
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_("\nWarning: disassembly may be wrong due to "
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"guessed opcode class choice.\n"
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"Use -M<class[,class]> to select the correct "
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"opcode class(es).\n\t\t\t\t"));
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return t_op;
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}
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return NULL;
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}
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/* Find opcode for INSN, trying various different sources. The instruction
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length in INSN_LEN will be updated if the instruction requires a LIMM
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extension.
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A pointer to the opcode is placed into OPCODE_RESULT, and ITER is
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initialised, ready to iterate over the operands of the found opcode. If
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the found opcode requires a LIMM then the LIMM value will be loaded into a
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field of ITER.
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This function returns TRUE in almost all cases, FALSE is reserved to
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indicate an error (failing to find an opcode is not an error) a returned
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result of FALSE would indicate that the disassembler can't continue.
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If no matching opcode is found then the returned result will be TRUE, the
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value placed into OPCODE_RESULT will be NULL, ITER will be undefined, and
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INSN_LEN will be unchanged.
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If a matching opcode is found, then the returned result will be TRUE, the
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opcode pointer is placed into OPCODE_RESULT, INSN_LEN will be increased by
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4 if the instruction requires a LIMM, and the LIMM value will have been
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loaded into a field of ITER. Finally, ITER will have been initialised so
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that calls to OPERAND_ITERATOR_NEXT will iterate over the opcode's
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operands. */
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static bool
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find_format (bfd_vma memaddr,
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unsigned long long insn,
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unsigned int * insn_len,
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unsigned isa_mask,
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struct disassemble_info * info,
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const struct arc_opcode ** opcode_result,
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struct arc_operand_iterator * iter)
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{
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const struct arc_opcode *opcode = NULL;
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bool needs_limm = false;
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const extInstruction_t *einsn, *i;
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unsigned limm = 0;
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struct arc_disassemble_info *arc_infop = info->private_data;
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/* First, try the extension instructions. */
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if (*insn_len == 4)
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{
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einsn = arcExtMap_insn (OPCODE_32BIT_INSN (insn), insn);
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for (i = einsn; (i != NULL) && (opcode == NULL); i = i->next)
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{
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const char *errmsg = NULL;
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opcode = arcExtMap_genOpcode (i, isa_mask, &errmsg);
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if (opcode == NULL)
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{
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(*info->fprintf_func) (info->stream,
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_("An error occurred while generating the "
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"extension instruction operations"));
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*opcode_result = NULL;
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return false;
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}
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opcode = find_format_from_table (info, opcode, insn, *insn_len,
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isa_mask, &needs_limm, false);
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}
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}
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/* Then, try finding the first match in the opcode table. */
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if (opcode == NULL)
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opcode = find_format_from_table (info, arc_opcodes, insn, *insn_len,
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isa_mask, &needs_limm, true);
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if (opcode != NULL && needs_limm)
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{
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bfd_byte buffer[4];
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int status;
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status = (*info->read_memory_func) (memaddr + *insn_len, buffer,
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4, info);
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if (status != 0)
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{
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opcode = NULL;
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}
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else
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{
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limm = ARRANGE_ENDIAN (info, buffer);
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*insn_len += 4;
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}
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}
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if (opcode != NULL)
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{
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iter->insn = insn;
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iter->limm = limm;
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iter->opcode = opcode;
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iter->opidx = opcode->operands;
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}
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*opcode_result = opcode;
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/* Update private data. */
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arc_infop->opcode = opcode;
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arc_infop->limm = limm;
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arc_infop->limm_p = needs_limm;
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return true;
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}
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|
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static void
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print_flags (const struct arc_opcode *opcode,
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unsigned long long *insn,
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struct disassemble_info *info)
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|
{
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const unsigned char *flgidx;
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unsigned int value;
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struct arc_disassemble_info *arc_infop = info->private_data;
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/* Now extract and print the flags. */
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for (flgidx = opcode->flags; *flgidx; flgidx++)
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{
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/* Get a valid flag class. */
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const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
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const unsigned *flgopridx;
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|
|
/* Check first the extensions. */
|
|
if (cl_flags->flag_class & F_CLASS_EXTEND)
|
|
{
|
|
const char *name;
|
|
value = (insn[0] & 0x1F);
|
|
|
|
name = arcExtMap_condCodeName (value);
|
|
if (name)
|
|
{
|
|
(*info->fprintf_func) (info->stream, ".%s", name);
|
|
continue;
|
|
}
|
|
}
|
|
|
|
for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
|
|
{
|
|
const struct arc_flag_operand *flg_operand =
|
|
&arc_flag_operands[*flgopridx];
|
|
|
|
/* Implicit flags are only used for the insn decoder. */
|
|
if (cl_flags->flag_class & F_CLASS_IMPLICIT)
|
|
{
|
|
if (cl_flags->flag_class & F_CLASS_COND)
|
|
arc_infop->condition_code = flg_operand->code;
|
|
else if (cl_flags->flag_class & F_CLASS_WB)
|
|
arc_infop->writeback_mode = flg_operand->code;
|
|
else if (cl_flags->flag_class & F_CLASS_ZZ)
|
|
info->data_size = flg_operand->code;
|
|
continue;
|
|
}
|
|
|
|
if (!flg_operand->favail)
|
|
continue;
|
|
|
|
value = (insn[0] >> flg_operand->shift)
|
|
& ((1 << flg_operand->bits) - 1);
|
|
if (value == flg_operand->code)
|
|
{
|
|
/* FIXME!: print correctly nt/t flag. */
|
|
if (!special_flag_p (opcode->name, flg_operand->name))
|
|
(*info->fprintf_func) (info->stream, ".");
|
|
else if (info->insn_type == dis_dref)
|
|
{
|
|
switch (flg_operand->name[0])
|
|
{
|
|
case 'b':
|
|
info->data_size = 1;
|
|
break;
|
|
case 'h':
|
|
case 'w':
|
|
info->data_size = 2;
|
|
break;
|
|
default:
|
|
info->data_size = 4;
|
|
break;
|
|
}
|
|
}
|
|
if (flg_operand->name[0] == 'd'
|
|
&& flg_operand->name[1] == 0)
|
|
info->branch_delay_insns = 1;
|
|
|
|
/* Check if it is a conditional flag. */
|
|
if (cl_flags->flag_class & F_CLASS_COND)
|
|
{
|
|
if (info->insn_type == dis_jsr)
|
|
info->insn_type = dis_condjsr;
|
|
else if (info->insn_type == dis_branch)
|
|
info->insn_type = dis_condbranch;
|
|
arc_infop->condition_code = flg_operand->code;
|
|
}
|
|
|
|
/* Check for the write back modes. */
|
|
if (cl_flags->flag_class & F_CLASS_WB)
|
|
arc_infop->writeback_mode = flg_operand->code;
|
|
|
|
(*info->fprintf_func) (info->stream, "%s", flg_operand->name);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
static const char *
|
|
get_auxreg (const struct arc_opcode *opcode,
|
|
int value,
|
|
unsigned isa_mask)
|
|
{
|
|
const char *name;
|
|
unsigned int i;
|
|
const struct arc_aux_reg *auxr = &arc_aux_regs[0];
|
|
|
|
if (opcode->insn_class != AUXREG)
|
|
return NULL;
|
|
|
|
name = arcExtMap_auxRegName (value);
|
|
if (name)
|
|
return name;
|
|
|
|
for (i = 0; i < arc_num_aux_regs; i++, auxr++)
|
|
{
|
|
if (!(auxr->cpu & isa_mask))
|
|
continue;
|
|
|
|
if (auxr->subclass != NONE)
|
|
return NULL;
|
|
|
|
if (auxr->address == value)
|
|
return auxr->name;
|
|
}
|
|
return NULL;
|
|
}
|
|
|
|
/* Convert a value representing an address type to a string used to refer to
|
|
the address type in assembly code. */
|
|
|
|
static const char *
|
|
get_addrtype (int value)
|
|
{
|
|
if (value < 0 || value > addrtypenames_max)
|
|
return addrtypeunknown;
|
|
|
|
return addrtypenames[value];
|
|
}
|
|
|
|
/* Calculate the instruction length for an instruction starting with MSB
|
|
and LSB, the most and least significant byte. The ISA_MASK is used to
|
|
filter the instructions considered to only those that are part of the
|
|
current architecture.
|
|
|
|
The instruction lengths are calculated from the ARC_OPCODE table, and
|
|
cached for later use. */
|
|
|
|
static unsigned int
|
|
arc_insn_length (bfd_byte msb, bfd_byte lsb, struct disassemble_info *info)
|
|
{
|
|
bfd_byte major_opcode = msb >> 3;
|
|
|
|
switch (info->mach)
|
|
{
|
|
case bfd_mach_arc_arc700:
|
|
/* The nps400 extension set requires this special casing of the
|
|
instruction length calculation. Right now this is not causing any
|
|
problems as none of the known extensions overlap in opcode space,
|
|
but, if they ever do then we might need to start carrying
|
|
information around in the elf about which extensions are in use. */
|
|
if (major_opcode == 0xb)
|
|
{
|
|
bfd_byte minor_opcode = lsb & 0x1f;
|
|
|
|
if (minor_opcode < 4)
|
|
return 6;
|
|
else if (minor_opcode == 0x10 || minor_opcode == 0x11)
|
|
return 8;
|
|
}
|
|
if (major_opcode == 0xa)
|
|
{
|
|
return 8;
|
|
}
|
|
/* Fall through. */
|
|
case bfd_mach_arc_arc600:
|
|
return (major_opcode > 0xb) ? 2 : 4;
|
|
break;
|
|
|
|
case bfd_mach_arc_arcv2:
|
|
return (major_opcode > 0x7) ? 2 : 4;
|
|
break;
|
|
|
|
default:
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
/* Extract and return the value of OPERAND from the instruction whose value
|
|
is held in the array INSN. */
|
|
|
|
static int
|
|
extract_operand_value (const struct arc_operand *operand,
|
|
unsigned long long insn,
|
|
unsigned limm)
|
|
{
|
|
int value;
|
|
|
|
/* Read the limm operand, if required. */
|
|
if (operand->flags & ARC_OPERAND_LIMM)
|
|
/* The second part of the instruction value will have been loaded as
|
|
part of the find_format call made earlier. */
|
|
value = limm;
|
|
else
|
|
{
|
|
if (operand->extract)
|
|
value = (*operand->extract) (insn, (bool *) NULL);
|
|
else
|
|
{
|
|
if (operand->flags & ARC_OPERAND_ALIGNED32)
|
|
{
|
|
value = (insn >> operand->shift)
|
|
& ((1 << (operand->bits - 2)) - 1);
|
|
value = value << 2;
|
|
}
|
|
else
|
|
{
|
|
value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
|
|
}
|
|
if (operand->flags & ARC_OPERAND_SIGNED)
|
|
{
|
|
int signbit = 1 << (operand->bits - 1);
|
|
value = (value ^ signbit) - signbit;
|
|
}
|
|
}
|
|
}
|
|
|
|
return value;
|
|
}
|
|
|
|
/* Find the next operand, and the operands value from ITER. Return TRUE if
|
|
there is another operand, otherwise return FALSE. If there is an
|
|
operand returned then the operand is placed into OPERAND, and the value
|
|
into VALUE. If there is no operand returned then OPERAND and VALUE are
|
|
unchanged. */
|
|
|
|
static bool
|
|
operand_iterator_next (struct arc_operand_iterator *iter,
|
|
const struct arc_operand **operand,
|
|
int *value)
|
|
{
|
|
if (*iter->opidx == 0)
|
|
{
|
|
*operand = NULL;
|
|
return false;
|
|
}
|
|
|
|
*operand = &arc_operands[*iter->opidx];
|
|
*value = extract_operand_value (*operand, iter->insn, iter->limm);
|
|
iter->opidx++;
|
|
|
|
return true;
|
|
}
|
|
|
|
/* Helper for parsing the options. */
|
|
|
|
static void
|
|
parse_option (const char *option)
|
|
{
|
|
if (disassembler_options_cmp (option, "dsp") == 0)
|
|
add_to_decodelist (DSP, NONE);
|
|
|
|
else if (disassembler_options_cmp (option, "spfp") == 0)
|
|
add_to_decodelist (FLOAT, SPX);
|
|
|
|
else if (disassembler_options_cmp (option, "dpfp") == 0)
|
|
add_to_decodelist (FLOAT, DPX);
|
|
|
|
else if (disassembler_options_cmp (option, "quarkse_em") == 0)
|
|
{
|
|
add_to_decodelist (FLOAT, DPX);
|
|
add_to_decodelist (FLOAT, SPX);
|
|
add_to_decodelist (FLOAT, QUARKSE1);
|
|
add_to_decodelist (FLOAT, QUARKSE2);
|
|
}
|
|
|
|
else if (disassembler_options_cmp (option, "fpuda") == 0)
|
|
add_to_decodelist (FLOAT, DPA);
|
|
|
|
else if (disassembler_options_cmp (option, "nps400") == 0)
|
|
{
|
|
add_to_decodelist (ACL, NPS400);
|
|
add_to_decodelist (ARITH, NPS400);
|
|
add_to_decodelist (BITOP, NPS400);
|
|
add_to_decodelist (BMU, NPS400);
|
|
add_to_decodelist (CONTROL, NPS400);
|
|
add_to_decodelist (DMA, NPS400);
|
|
add_to_decodelist (DPI, NPS400);
|
|
add_to_decodelist (MEMORY, NPS400);
|
|
add_to_decodelist (MISC, NPS400);
|
|
add_to_decodelist (NET, NPS400);
|
|
add_to_decodelist (PMU, NPS400);
|
|
add_to_decodelist (PROTOCOL_DECODE, NPS400);
|
|
add_to_decodelist (ULTRAIP, NPS400);
|
|
}
|
|
|
|
else if (disassembler_options_cmp (option, "fpus") == 0)
|
|
{
|
|
add_to_decodelist (FLOAT, SP);
|
|
add_to_decodelist (FLOAT, CVT);
|
|
}
|
|
|
|
else if (disassembler_options_cmp (option, "fpud") == 0)
|
|
{
|
|
add_to_decodelist (FLOAT, DP);
|
|
add_to_decodelist (FLOAT, CVT);
|
|
}
|
|
else if (startswith (option, "hex"))
|
|
print_hex = true;
|
|
else
|
|
/* xgettext:c-format */
|
|
opcodes_error_handler (_("unrecognised disassembler option: %s"), option);
|
|
}
|
|
|
|
#define ARC_CPU_TYPE_A6xx(NAME,EXTRA) \
|
|
{ #NAME, ARC_OPCODE_ARC600, "ARC600" }
|
|
#define ARC_CPU_TYPE_A7xx(NAME,EXTRA) \
|
|
{ #NAME, ARC_OPCODE_ARC700, "ARC700" }
|
|
#define ARC_CPU_TYPE_AV2EM(NAME,EXTRA) \
|
|
{ #NAME, ARC_OPCODE_ARCv2EM, "ARC EM" }
|
|
#define ARC_CPU_TYPE_AV2HS(NAME,EXTRA) \
|
|
{ #NAME, ARC_OPCODE_ARCv2HS, "ARC HS" }
|
|
#define ARC_CPU_TYPE_NONE \
|
|
{ 0, 0, 0 }
|
|
|
|
/* A table of CPU names and opcode sets. */
|
|
static const struct cpu_type
|
|
{
|
|
const char *name;
|
|
unsigned flags;
|
|
const char *isa;
|
|
}
|
|
cpu_types[] =
|
|
{
|
|
#include "elf/arc-cpu.def"
|
|
};
|
|
|
|
/* Helper for parsing the CPU options. Accept any of the ARC architectures
|
|
values. OPTION should be a value passed to cpu=. */
|
|
|
|
static unsigned
|
|
parse_cpu_option (const char *option)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; cpu_types[i].name; ++i)
|
|
{
|
|
if (!disassembler_options_cmp (cpu_types[i].name, option))
|
|
{
|
|
return cpu_types[i].flags;
|
|
}
|
|
}
|
|
|
|
/* xgettext:c-format */
|
|
opcodes_error_handler (_("unrecognised disassembler CPU option: %s"), option);
|
|
return ARC_OPCODE_NONE;
|
|
}
|
|
|
|
/* Go over the options list and parse it. */
|
|
|
|
static void
|
|
parse_disassembler_options (const char *options)
|
|
{
|
|
const char *option;
|
|
|
|
if (options == NULL)
|
|
return;
|
|
|
|
/* Disassembler might be reused for difference CPU's, and cpu option set for
|
|
the first one shouldn't be applied to second (which might not have
|
|
explicit cpu in its options. Therefore it is required to reset enforced
|
|
CPU when new options are being parsed. */
|
|
enforced_isa_mask = ARC_OPCODE_NONE;
|
|
|
|
FOR_EACH_DISASSEMBLER_OPTION (option, options)
|
|
{
|
|
/* A CPU option? Cannot use STRING_COMMA_LEN because strncmp is also a
|
|
preprocessor macro. */
|
|
if (strncmp (option, "cpu=", 4) == 0)
|
|
/* Strip leading `cpu=`. */
|
|
enforced_isa_mask = parse_cpu_option (option + 4);
|
|
else
|
|
parse_option (option);
|
|
}
|
|
}
|
|
|
|
/* Return the instruction type for an instruction described by OPCODE. */
|
|
|
|
static enum dis_insn_type
|
|
arc_opcode_to_insn_type (const struct arc_opcode *opcode)
|
|
{
|
|
enum dis_insn_type insn_type;
|
|
|
|
switch (opcode->insn_class)
|
|
{
|
|
case BRANCH:
|
|
case BBIT0:
|
|
case BBIT1:
|
|
case BI:
|
|
case BIH:
|
|
case BRCC:
|
|
case EI:
|
|
case JLI:
|
|
case JUMP:
|
|
case LOOP:
|
|
if (!strncmp (opcode->name, "bl", 2)
|
|
|| !strncmp (opcode->name, "jl", 2))
|
|
{
|
|
if (opcode->subclass == COND)
|
|
insn_type = dis_condjsr;
|
|
else
|
|
insn_type = dis_jsr;
|
|
}
|
|
else
|
|
{
|
|
if (opcode->subclass == COND)
|
|
insn_type = dis_condbranch;
|
|
else
|
|
insn_type = dis_branch;
|
|
}
|
|
break;
|
|
case LOAD:
|
|
case STORE:
|
|
case MEMORY:
|
|
case ENTER:
|
|
case PUSH:
|
|
case POP:
|
|
insn_type = dis_dref;
|
|
break;
|
|
case LEAVE:
|
|
insn_type = dis_branch;
|
|
break;
|
|
default:
|
|
insn_type = dis_nonbranch;
|
|
break;
|
|
}
|
|
|
|
return insn_type;
|
|
}
|
|
|
|
/* Disassemble ARC instructions. */
|
|
|
|
static int
|
|
print_insn_arc (bfd_vma memaddr,
|
|
struct disassemble_info *info)
|
|
{
|
|
bfd_byte buffer[8];
|
|
unsigned int highbyte, lowbyte;
|
|
int status;
|
|
unsigned int insn_len;
|
|
unsigned long long insn = 0;
|
|
unsigned isa_mask = ARC_OPCODE_NONE;
|
|
const struct arc_opcode *opcode;
|
|
bool need_comma;
|
|
bool open_braket;
|
|
int size;
|
|
const struct arc_operand *operand;
|
|
int value, vpcl;
|
|
struct arc_operand_iterator iter;
|
|
struct arc_disassemble_info *arc_infop;
|
|
bool rpcl = false, rset = false;
|
|
|
|
if (info->disassembler_options)
|
|
{
|
|
parse_disassembler_options (info->disassembler_options);
|
|
|
|
/* Avoid repeated parsing of the options. */
|
|
info->disassembler_options = NULL;
|
|
}
|
|
|
|
if (info->private_data == NULL && !init_arc_disasm_info (info))
|
|
return -1;
|
|
|
|
memset (&iter, 0, sizeof (iter));
|
|
highbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 1 : 0);
|
|
lowbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 0 : 1);
|
|
|
|
/* Figure out CPU type, unless it was enforced via disassembler options. */
|
|
if (enforced_isa_mask == ARC_OPCODE_NONE)
|
|
{
|
|
Elf_Internal_Ehdr *header = NULL;
|
|
|
|
if (info->section && info->section->owner)
|
|
header = elf_elfheader (info->section->owner);
|
|
|
|
switch (info->mach)
|
|
{
|
|
case bfd_mach_arc_arc700:
|
|
isa_mask = ARC_OPCODE_ARC700;
|
|
break;
|
|
|
|
case bfd_mach_arc_arc600:
|
|
isa_mask = ARC_OPCODE_ARC600;
|
|
break;
|
|
|
|
case bfd_mach_arc_arcv2:
|
|
default:
|
|
isa_mask = ARC_OPCODE_ARCv2EM;
|
|
/* TODO: Perhaps remove definition of header since it is only used at
|
|
this location. */
|
|
if (header != NULL
|
|
&& (header->e_flags & EF_ARC_MACH_MSK) == EF_ARC_CPU_ARCV2HS)
|
|
isa_mask = ARC_OPCODE_ARCv2HS;
|
|
break;
|
|
}
|
|
}
|
|
else
|
|
isa_mask = enforced_isa_mask;
|
|
|
|
if (isa_mask == ARC_OPCODE_ARCv2HS)
|
|
{
|
|
/* FPU instructions are not extensions for HS. */
|
|
add_to_decodelist (FLOAT, SP);
|
|
add_to_decodelist (FLOAT, DP);
|
|
add_to_decodelist (FLOAT, CVT);
|
|
}
|
|
|
|
/* This variable may be set by the instruction decoder. It suggests
|
|
the number of bytes objdump should display on a single line. If
|
|
the instruction decoder sets this, it should always set it to
|
|
the same value in order to get reasonable looking output. */
|
|
info->bytes_per_line = 8;
|
|
|
|
/* In the next lines, we set two info variables control the way
|
|
objdump displays the raw data. For example, if bytes_per_line is
|
|
8 and bytes_per_chunk is 4, the output will look like this:
|
|
00: 00000000 00000000
|
|
with the chunks displayed according to "display_endian". */
|
|
if (info->section
|
|
&& !(info->section->flags & SEC_CODE))
|
|
{
|
|
/* This is not a CODE section. */
|
|
switch (info->section->size)
|
|
{
|
|
case 1:
|
|
case 2:
|
|
case 4:
|
|
size = info->section->size;
|
|
break;
|
|
default:
|
|
size = (info->section->size & 0x01) ? 1 : 4;
|
|
break;
|
|
}
|
|
info->bytes_per_chunk = 1;
|
|
info->display_endian = info->endian;
|
|
}
|
|
else
|
|
{
|
|
size = 2;
|
|
info->bytes_per_chunk = 2;
|
|
info->display_endian = info->endian;
|
|
}
|
|
|
|
/* Read the insn into a host word. */
|
|
status = (*info->read_memory_func) (memaddr, buffer, size, info);
|
|
|
|
if (status != 0)
|
|
{
|
|
(*info->memory_error_func) (status, memaddr, info);
|
|
return -1;
|
|
}
|
|
|
|
if (info->section
|
|
&& !(info->section->flags & SEC_CODE))
|
|
{
|
|
/* Data section. */
|
|
unsigned long data;
|
|
|
|
data = bfd_get_bits (buffer, size * 8,
|
|
info->display_endian == BFD_ENDIAN_BIG);
|
|
switch (size)
|
|
{
|
|
case 1:
|
|
(*info->fprintf_func) (info->stream, ".byte\t0x%02lx", data);
|
|
break;
|
|
case 2:
|
|
(*info->fprintf_func) (info->stream, ".short\t0x%04lx", data);
|
|
break;
|
|
case 4:
|
|
(*info->fprintf_func) (info->stream, ".word\t0x%08lx", data);
|
|
break;
|
|
default:
|
|
return -1;
|
|
}
|
|
return size;
|
|
}
|
|
|
|
insn_len = arc_insn_length (buffer[highbyte], buffer[lowbyte], info);
|
|
pr_debug ("instruction length = %d bytes\n", insn_len);
|
|
if (insn_len == 0)
|
|
return -1;
|
|
|
|
arc_infop = info->private_data;
|
|
arc_infop->insn_len = insn_len;
|
|
|
|
switch (insn_len)
|
|
{
|
|
case 2:
|
|
insn = (buffer[highbyte] << 8) | buffer[lowbyte];
|
|
break;
|
|
|
|
case 4:
|
|
{
|
|
/* This is a long instruction: Read the remaning 2 bytes. */
|
|
status = (*info->read_memory_func) (memaddr + 2, &buffer[2], 2, info);
|
|
if (status != 0)
|
|
{
|
|
(*info->memory_error_func) (status, memaddr + 2, info);
|
|
return -1;
|
|
}
|
|
insn = (unsigned long long) ARRANGE_ENDIAN (info, buffer);
|
|
}
|
|
break;
|
|
|
|
case 6:
|
|
{
|
|
status = (*info->read_memory_func) (memaddr + 2, &buffer[2], 4, info);
|
|
if (status != 0)
|
|
{
|
|
(*info->memory_error_func) (status, memaddr + 2, info);
|
|
return -1;
|
|
}
|
|
insn = (unsigned long long) ARRANGE_ENDIAN (info, &buffer[2]);
|
|
insn |= ((unsigned long long) buffer[highbyte] << 40)
|
|
| ((unsigned long long) buffer[lowbyte] << 32);
|
|
}
|
|
break;
|
|
|
|
case 8:
|
|
{
|
|
status = (*info->read_memory_func) (memaddr + 2, &buffer[2], 6, info);
|
|
if (status != 0)
|
|
{
|
|
(*info->memory_error_func) (status, memaddr + 2, info);
|
|
return -1;
|
|
}
|
|
insn =
|
|
((((unsigned long long) ARRANGE_ENDIAN (info, buffer)) << 32)
|
|
| ((unsigned long long) ARRANGE_ENDIAN (info, &buffer[4])));
|
|
}
|
|
break;
|
|
|
|
default:
|
|
/* There is no instruction whose length is not 2, 4, 6, or 8. */
|
|
return -1;
|
|
}
|
|
|
|
pr_debug ("instruction value = %llx\n", insn);
|
|
|
|
/* Set some defaults for the insn info. */
|
|
info->insn_info_valid = 1;
|
|
info->branch_delay_insns = 0;
|
|
info->data_size = 4;
|
|
info->insn_type = dis_nonbranch;
|
|
info->target = 0;
|
|
info->target2 = 0;
|
|
|
|
/* FIXME to be moved in dissasemble_init_for_target. */
|
|
info->disassembler_needs_relocs = true;
|
|
|
|
/* Find the first match in the opcode table. */
|
|
if (!find_format (memaddr, insn, &insn_len, isa_mask, info, &opcode, &iter))
|
|
return -1;
|
|
|
|
if (!opcode)
|
|
{
|
|
switch (insn_len)
|
|
{
|
|
case 2:
|
|
(*info->fprintf_func) (info->stream, ".shor\t%#04llx",
|
|
insn & 0xffff);
|
|
break;
|
|
|
|
case 4:
|
|
(*info->fprintf_func) (info->stream, ".word\t%#08llx",
|
|
insn & 0xffffffff);
|
|
break;
|
|
|
|
case 6:
|
|
(*info->fprintf_func) (info->stream, ".long\t%#08llx",
|
|
insn & 0xffffffff);
|
|
(*info->fprintf_func) (info->stream, ".long\t%#04llx",
|
|
(insn >> 32) & 0xffff);
|
|
break;
|
|
|
|
case 8:
|
|
(*info->fprintf_func) (info->stream, ".long\t%#08llx",
|
|
insn & 0xffffffff);
|
|
(*info->fprintf_func) (info->stream, ".long\t%#08llx",
|
|
insn >> 32);
|
|
break;
|
|
|
|
default:
|
|
return -1;
|
|
}
|
|
|
|
info->insn_type = dis_noninsn;
|
|
return insn_len;
|
|
}
|
|
|
|
/* Print the mnemonic. */
|
|
(*info->fprintf_func) (info->stream, "%s", opcode->name);
|
|
|
|
/* Preselect the insn class. */
|
|
info->insn_type = arc_opcode_to_insn_type (opcode);
|
|
|
|
pr_debug ("%s: 0x%08llx\n", opcode->name, opcode->opcode);
|
|
|
|
print_flags (opcode, &insn, info);
|
|
|
|
if (opcode->operands[0] != 0)
|
|
(*info->fprintf_func) (info->stream, "\t");
|
|
|
|
need_comma = false;
|
|
open_braket = false;
|
|
arc_infop->operands_count = 0;
|
|
|
|
/* Now extract and print the operands. */
|
|
operand = NULL;
|
|
vpcl = 0;
|
|
while (operand_iterator_next (&iter, &operand, &value))
|
|
{
|
|
if (open_braket && (operand->flags & ARC_OPERAND_BRAKET))
|
|
{
|
|
(*info->fprintf_func) (info->stream, "]");
|
|
open_braket = false;
|
|
continue;
|
|
}
|
|
|
|
/* Only take input from real operands. */
|
|
if (ARC_OPERAND_IS_FAKE (operand))
|
|
continue;
|
|
|
|
if ((operand->flags & ARC_OPERAND_IGNORE)
|
|
&& (operand->flags & ARC_OPERAND_IR)
|
|
&& value == -1)
|
|
continue;
|
|
|
|
if (operand->flags & ARC_OPERAND_COLON)
|
|
{
|
|
(*info->fprintf_func) (info->stream, ":");
|
|
continue;
|
|
}
|
|
|
|
if (need_comma)
|
|
(*info->fprintf_func) (info->stream, ",");
|
|
|
|
if (!open_braket && (operand->flags & ARC_OPERAND_BRAKET))
|
|
{
|
|
(*info->fprintf_func) (info->stream, "[");
|
|
open_braket = true;
|
|
need_comma = false;
|
|
continue;
|
|
}
|
|
|
|
need_comma = true;
|
|
|
|
if (operand->flags & ARC_OPERAND_PCREL)
|
|
{
|
|
rpcl = true;
|
|
vpcl = value;
|
|
rset = true;
|
|
|
|
info->target = (bfd_vma) (memaddr & ~3) + value;
|
|
}
|
|
else if (!(operand->flags & ARC_OPERAND_IR))
|
|
{
|
|
vpcl = value;
|
|
rset = true;
|
|
}
|
|
|
|
/* Print the operand as directed by the flags. */
|
|
if (operand->flags & ARC_OPERAND_IR)
|
|
{
|
|
const char *rname;
|
|
|
|
assert (value >=0 && value < 64);
|
|
rname = arcExtMap_coreRegName (value);
|
|
if (!rname)
|
|
rname = regnames[value];
|
|
(*info->fprintf_func) (info->stream, "%s", rname);
|
|
|
|
/* Check if we have a double register to print. */
|
|
if (operand->flags & ARC_OPERAND_TRUNCATE)
|
|
{
|
|
if ((value & 0x01) == 0)
|
|
{
|
|
rname = arcExtMap_coreRegName (value + 1);
|
|
if (!rname)
|
|
rname = regnames[value + 1];
|
|
}
|
|
else
|
|
rname = _("\nWarning: illegal use of double register "
|
|
"pair.\n");
|
|
(*info->fprintf_func) (info->stream, "%s", rname);
|
|
}
|
|
if (value == 63)
|
|
rpcl = true;
|
|
else
|
|
rpcl = false;
|
|
}
|
|
else if (operand->flags & ARC_OPERAND_LIMM)
|
|
{
|
|
const char *rname = get_auxreg (opcode, value, isa_mask);
|
|
|
|
if (rname && open_braket)
|
|
(*info->fprintf_func) (info->stream, "%s", rname);
|
|
else
|
|
{
|
|
(*info->fprintf_func) (info->stream, "%#x", value);
|
|
if (info->insn_type == dis_branch
|
|
|| info->insn_type == dis_jsr)
|
|
info->target = (bfd_vma) value;
|
|
}
|
|
}
|
|
else if (operand->flags & ARC_OPERAND_SIGNED)
|
|
{
|
|
const char *rname = get_auxreg (opcode, value, isa_mask);
|
|
if (rname && open_braket)
|
|
(*info->fprintf_func) (info->stream, "%s", rname);
|
|
else
|
|
{
|
|
if (print_hex)
|
|
(*info->fprintf_func) (info->stream, "%#x", value);
|
|
else
|
|
(*info->fprintf_func) (info->stream, "%d", value);
|
|
}
|
|
}
|
|
else if (operand->flags & ARC_OPERAND_ADDRTYPE)
|
|
{
|
|
const char *addrtype = get_addrtype (value);
|
|
(*info->fprintf_func) (info->stream, "%s", addrtype);
|
|
/* A colon follow an address type. */
|
|
need_comma = false;
|
|
}
|
|
else
|
|
{
|
|
if (operand->flags & ARC_OPERAND_TRUNCATE
|
|
&& !(operand->flags & ARC_OPERAND_ALIGNED32)
|
|
&& !(operand->flags & ARC_OPERAND_ALIGNED16)
|
|
&& value >= 0 && value <= 14)
|
|
{
|
|
/* Leave/Enter mnemonics. */
|
|
switch (value)
|
|
{
|
|
case 0:
|
|
need_comma = false;
|
|
break;
|
|
case 1:
|
|
(*info->fprintf_func) (info->stream, "r13");
|
|
break;
|
|
default:
|
|
(*info->fprintf_func) (info->stream, "r13-%s",
|
|
regnames[13 + value - 1]);
|
|
break;
|
|
}
|
|
rpcl = false;
|
|
rset = false;
|
|
}
|
|
else
|
|
{
|
|
const char *rname = get_auxreg (opcode, value, isa_mask);
|
|
if (rname && open_braket)
|
|
(*info->fprintf_func) (info->stream, "%s", rname);
|
|
else
|
|
(*info->fprintf_func) (info->stream, "%#x", value);
|
|
}
|
|
}
|
|
|
|
if (operand->flags & ARC_OPERAND_LIMM)
|
|
{
|
|
arc_infop->operands[arc_infop->operands_count].kind
|
|
= ARC_OPERAND_KIND_LIMM;
|
|
/* It is not important to have exactly the LIMM indicator
|
|
here. */
|
|
arc_infop->operands[arc_infop->operands_count].value = 63;
|
|
}
|
|
else
|
|
{
|
|
arc_infop->operands[arc_infop->operands_count].value = value;
|
|
arc_infop->operands[arc_infop->operands_count].kind
|
|
= (operand->flags & ARC_OPERAND_IR
|
|
? ARC_OPERAND_KIND_REG
|
|
: ARC_OPERAND_KIND_SHIMM);
|
|
}
|
|
arc_infop->operands_count ++;
|
|
}
|
|
|
|
/* Pretty print extra info for pc-relative operands. */
|
|
if (rpcl && rset)
|
|
{
|
|
if (info->flags & INSN_HAS_RELOC)
|
|
/* If the instruction has a reloc associated with it, then the
|
|
offset field in the instruction will actually be the addend
|
|
for the reloc. (We are using REL type relocs). In such
|
|
cases, we can ignore the pc when computing addresses, since
|
|
the addend is not currently pc-relative. */
|
|
memaddr = 0;
|
|
|
|
(*info->fprintf_func) (info->stream, "\t;");
|
|
(*info->print_address_func) ((memaddr & ~3) + vpcl, info);
|
|
}
|
|
|
|
return insn_len;
|
|
}
|
|
|
|
|
|
disassembler_ftype
|
|
arc_get_disassembler (bfd *abfd)
|
|
{
|
|
/* BFD my be absent, if opcodes is invoked from the debugger that
|
|
has connected to remote target and doesn't have an ELF file. */
|
|
if (abfd != NULL)
|
|
{
|
|
/* Read the extension insns and registers, if any. */
|
|
build_ARC_extmap (abfd);
|
|
#ifdef DEBUG
|
|
dump_ARC_extmap ();
|
|
#endif
|
|
}
|
|
|
|
return print_insn_arc;
|
|
}
|
|
|
|
/* Indices into option argument vector for options that do require
|
|
an argument. Use ARC_OPTION_ARG_NONE for options that don't
|
|
expect an argument. */
|
|
typedef enum
|
|
{
|
|
ARC_OPTION_ARG_NONE = -1,
|
|
ARC_OPTION_ARG_ARCH,
|
|
ARC_OPTION_ARG_SIZE
|
|
} arc_option_arg_t;
|
|
|
|
/* Valid ARC disassembler options. */
|
|
static struct
|
|
{
|
|
const char *name;
|
|
const char *description;
|
|
arc_option_arg_t arg;
|
|
} arc_options[] =
|
|
{
|
|
{ "cpu=", N_("Enforce the designated architecture while decoding."),
|
|
ARC_OPTION_ARG_ARCH },
|
|
{ "dsp", N_("Recognize DSP instructions."),
|
|
ARC_OPTION_ARG_NONE },
|
|
{ "spfp", N_("Recognize FPX SP instructions."),
|
|
ARC_OPTION_ARG_NONE },
|
|
{ "dpfp", N_("Recognize FPX DP instructions."),
|
|
ARC_OPTION_ARG_NONE },
|
|
{ "quarkse_em", N_("Recognize FPU QuarkSE-EM instructions."),
|
|
ARC_OPTION_ARG_NONE },
|
|
{ "fpuda", N_("Recognize double assist FPU instructions."),
|
|
ARC_OPTION_ARG_NONE },
|
|
{ "fpus", N_("Recognize single precision FPU instructions."),
|
|
ARC_OPTION_ARG_NONE },
|
|
{ "fpud", N_("Recognize double precision FPU instructions."),
|
|
ARC_OPTION_ARG_NONE },
|
|
{ "nps400", N_("Recognize NPS400 instructions."),
|
|
ARC_OPTION_ARG_NONE },
|
|
{ "hex", N_("Use only hexadecimal number to print immediates."),
|
|
ARC_OPTION_ARG_NONE }
|
|
};
|
|
|
|
/* Populate the structure for representing ARC's disassembly options.
|
|
Such a dynamic initialization is desired, because it makes the maintenance
|
|
easier and also gdb uses this to enable the "disassembler-option". */
|
|
|
|
const disasm_options_and_args_t *
|
|
disassembler_options_arc (void)
|
|
{
|
|
static disasm_options_and_args_t *opts_and_args;
|
|
|
|
if (opts_and_args == NULL)
|
|
{
|
|
disasm_option_arg_t *args;
|
|
disasm_options_t *opts;
|
|
size_t i;
|
|
const size_t nr_of_options = ARRAY_SIZE (arc_options);
|
|
/* There is a null element at the end of CPU_TYPES, therefore
|
|
NR_OF_CPUS is actually 1 more and that is desired here too. */
|
|
const size_t nr_of_cpus = ARRAY_SIZE (cpu_types);
|
|
|
|
opts_and_args = XNEW (disasm_options_and_args_t);
|
|
opts_and_args->args
|
|
= XNEWVEC (disasm_option_arg_t, ARC_OPTION_ARG_SIZE + 1);
|
|
opts_and_args->options.name
|
|
= XNEWVEC (const char *, nr_of_options + 1);
|
|
opts_and_args->options.description
|
|
= XNEWVEC (const char *, nr_of_options + 1);
|
|
opts_and_args->options.arg
|
|
= XNEWVEC (const disasm_option_arg_t *, nr_of_options + 1);
|
|
|
|
/* Populate the arguments for "cpu=" option. */
|
|
args = opts_and_args->args;
|
|
args[ARC_OPTION_ARG_ARCH].name = "ARCH";
|
|
args[ARC_OPTION_ARG_ARCH].values = XNEWVEC (const char *, nr_of_cpus);
|
|
for (i = 0; i < nr_of_cpus; ++i)
|
|
args[ARC_OPTION_ARG_ARCH].values[i] = cpu_types[i].name;
|
|
args[ARC_OPTION_ARG_SIZE].name = NULL;
|
|
args[ARC_OPTION_ARG_SIZE].values = NULL;
|
|
|
|
/* Populate the options. */
|
|
opts = &opts_and_args->options;
|
|
for (i = 0; i < nr_of_options; ++i)
|
|
{
|
|
opts->name[i] = arc_options[i].name;
|
|
opts->description[i] = arc_options[i].description;
|
|
if (arc_options[i].arg != ARC_OPTION_ARG_NONE)
|
|
opts->arg[i] = &args[arc_options[i].arg];
|
|
else
|
|
opts->arg[i] = NULL;
|
|
}
|
|
opts->name[nr_of_options] = NULL;
|
|
opts->description[nr_of_options] = NULL;
|
|
opts->arg[nr_of_options] = NULL;
|
|
}
|
|
|
|
return opts_and_args;
|
|
}
|
|
|
|
|
|
void
|
|
print_arc_disassembler_options (FILE *stream)
|
|
{
|
|
const disasm_options_and_args_t *opts_and_args;
|
|
const disasm_option_arg_t *args;
|
|
const disasm_options_t *opts;
|
|
size_t i, j;
|
|
size_t max_len = 0;
|
|
|
|
opts_and_args = disassembler_options_arc ();
|
|
opts = &opts_and_args->options;
|
|
args = opts_and_args->args;
|
|
|
|
fprintf (stream, _("\nThe following ARC specific disassembler options are"
|
|
" supported for use \nwith the -M switch (multiple"
|
|
" options should be separated by commas):\n"));
|
|
|
|
/* Find the maximum length for printing options (and their arg name). */
|
|
for (i = 0; opts->name[i] != NULL; ++i)
|
|
{
|
|
size_t len = strlen (opts->name[i]);
|
|
len += (opts->arg[i]) ? strlen (opts->arg[i]->name) : 0;
|
|
max_len = (len > max_len) ? len : max_len;
|
|
}
|
|
|
|
/* Print the options, their arg and description, if any. */
|
|
for (i = 0, ++max_len; opts->name[i] != NULL; ++i)
|
|
{
|
|
fprintf (stream, " %s", opts->name[i]);
|
|
if (opts->arg[i] != NULL)
|
|
fprintf (stream, "%s", opts->arg[i]->name);
|
|
if (opts->description[i] != NULL)
|
|
{
|
|
size_t len = strlen (opts->name[i]);
|
|
len += (opts->arg[i]) ? strlen (opts->arg[i]->name) : 0;
|
|
fprintf (stream,
|
|
"%*c %s", (int) (max_len - len), ' ', opts->description[i]);
|
|
}
|
|
fprintf (stream, _("\n"));
|
|
}
|
|
|
|
/* Print the possible values of an argument. */
|
|
for (i = 0; args[i].name != NULL; ++i)
|
|
{
|
|
size_t len = 3;
|
|
fprintf (stream, _("\n\
|
|
For the options above, the following values are supported for \"%s\":\n "),
|
|
args[i].name);
|
|
for (j = 0; args[i].values[j] != NULL; ++j)
|
|
{
|
|
fprintf (stream, " %s", args[i].values[j]);
|
|
len += strlen (args[i].values[j]) + 1;
|
|
/* reset line if printed too long. */
|
|
if (len >= 78)
|
|
{
|
|
fprintf (stream, _("\n "));
|
|
len = 3;
|
|
}
|
|
}
|
|
fprintf (stream, _("\n"));
|
|
}
|
|
|
|
fprintf (stream, _("\n"));
|
|
}
|
|
|
|
void arc_insn_decode (bfd_vma addr,
|
|
struct disassemble_info *info,
|
|
disassembler_ftype disasm_func,
|
|
struct arc_instruction *insn)
|
|
{
|
|
const struct arc_opcode *opcode;
|
|
struct arc_disassemble_info *arc_infop;
|
|
|
|
/* Ensure that insn would be in the reset state. */
|
|
memset (insn, 0, sizeof (struct arc_instruction));
|
|
|
|
/* There was an error when disassembling, for example memory read error. */
|
|
if (disasm_func (addr, info) < 0)
|
|
{
|
|
insn->valid = false;
|
|
return;
|
|
}
|
|
|
|
assert (info->private_data != NULL);
|
|
arc_infop = info->private_data;
|
|
|
|
insn->length = arc_infop->insn_len;;
|
|
insn->address = addr;
|
|
|
|
/* Quick exit if memory at this address is not an instruction. */
|
|
if (info->insn_type == dis_noninsn)
|
|
{
|
|
insn->valid = false;
|
|
return;
|
|
}
|
|
|
|
insn->valid = true;
|
|
|
|
opcode = (const struct arc_opcode *) arc_infop->opcode;
|
|
insn->insn_class = opcode->insn_class;
|
|
insn->limm_value = arc_infop->limm;
|
|
insn->limm_p = arc_infop->limm_p;
|
|
|
|
insn->is_control_flow = (info->insn_type == dis_branch
|
|
|| info->insn_type == dis_condbranch
|
|
|| info->insn_type == dis_jsr
|
|
|| info->insn_type == dis_condjsr);
|
|
|
|
insn->has_delay_slot = info->branch_delay_insns;
|
|
insn->writeback_mode
|
|
= (enum arc_ldst_writeback_mode) arc_infop->writeback_mode;
|
|
insn->data_size_mode = info->data_size;
|
|
insn->condition_code = arc_infop->condition_code;
|
|
memcpy (insn->operands, arc_infop->operands,
|
|
sizeof (struct arc_insn_operand) * MAX_INSN_ARGS);
|
|
insn->operands_count = arc_infop->operands_count;
|
|
}
|
|
|
|
/* Local variables:
|
|
eval: (c-set-style "gnu")
|
|
indent-tabs-mode: t
|
|
End: */
|