mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-11-21 01:12:32 +08:00
1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
618 lines
8.0 KiB
PHP
618 lines
8.0 KiB
PHP
# Support macros for the sh assembly test cases.
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.equ no_dsp, 0
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.equ yes_dsp, 1
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.section .rodata
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.align 2
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_pass: .string "pass\n"
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_fail: .string "fail\n"
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_stack: .fill 128, 4, 0
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stackt:
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.macro push reg
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mov.l \reg, @-r15
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.endm
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.macro pop reg
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mov.l @r15+, \reg
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.endm
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.macro start
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.text
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.align 1
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.global start
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start: mov.l stackp, r15
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bra main
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nop
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.align 2
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stackp: .long stackt
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mpass:
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mov #4, r4
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mov #1, r5
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mov.l ppass, r6
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mov #5, r7
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trapa #34
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rts
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nop
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mfail:
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mov #4, r4
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mov #1, r5
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mov.l pfail, r6
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mov #5, r7
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trapa #34
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mov #1, r5
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mexit:
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mov #1, r4
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mov #0, r6
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mov #0, r7
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trapa #34
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.align 2
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ppass: .long _pass
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pfail: .long _fail
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mtesta5:
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push r0
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mov.l a5a5, r0
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cmp/eq r1, r0
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bf mfail
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cmp/eq r2, r0
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bf mfail
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cmp/eq r3, r0
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bf mfail
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cmp/eq r4, r0
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bf mfail
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cmp/eq r5, r0
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bf mfail
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cmp/eq r6, r0
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bf mfail
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cmp/eq r7, r0
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bf mfail
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cmp/eq r8, r0
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bf mfail
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cmp/eq r9, r0
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bf mfail
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cmp/eq r10, r0
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bf mfail
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cmp/eq r11, r0
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bf mfail
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cmp/eq r12, r0
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bf mfail
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cmp/eq r13, r0
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bf mfail
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cmp/eq r14, r0
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bf mfail
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# restore and check r0
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pop r0
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cmp/eq r0, r1
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bf mfail
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# pass
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rts
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nop
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.if (sim_cpu == no_dsp)
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mtesta5_fp:
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push r0
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flds fr0, fpul
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sts fpul, r0
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push r0
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mov.l a5a5, r0
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lds r0, fpul
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fsts fpul, fr0
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fcmp/eq fr1, fr0
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bf mfail
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fcmp/eq fr2, fr0
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bf mfail
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fcmp/eq fr3, fr0
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bf mfail
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fcmp/eq fr4, fr0
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bf mfail
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fcmp/eq fr5, fr0
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bf mfail
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fcmp/eq fr6, fr0
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bf mfail
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fcmp/eq fr7, fr0
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bf mfail
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fcmp/eq fr8, fr0
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bf mfail
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fcmp/eq fr9, fr0
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bf mfail
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fcmp/eq fr10, fr0
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bf mfail
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fcmp/eq fr11, fr0
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bf mfail
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fcmp/eq fr12, fr0
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bf mfail
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fcmp/eq fr13, fr0
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bf mfail
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fcmp/eq fr14, fr0
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bf mfail
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fcmp/eq fr15, fr0
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bf mfail
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# restore and check fr0
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pop r0
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lds r0, fpul
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fsts fpul, fr0
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fcmp/eq fr0, fr1
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bf mfail
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# restore r0 and pass
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pop r0
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rts
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nop
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.endif
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mseta5:
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mov.l a5a5, r0
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mov.l a5a5, r1
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mov.l a5a5, r2
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mov.l a5a5, r3
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mov.l a5a5, r4
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mov.l a5a5, r5
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mov.l a5a5, r6
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mov.l a5a5, r7
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mov.l a5a5, r8
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mov.l a5a5, r9
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mov.l a5a5, r10
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mov.l a5a5, r11
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mov.l a5a5, r12
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mov.l a5a5, r13
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mov.l a5a5, r14
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rts
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nop
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.if (sim_cpu == no_dsp)
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mseta5_fp:
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push r0
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mov.l a5a5, r0
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lds r0, fpul
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fsts fpul, fr0
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fsts fpul, fr1
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fsts fpul, fr2
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fsts fpul, fr3
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fsts fpul, fr4
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fsts fpul, fr5
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fsts fpul, fr6
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fsts fpul, fr7
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fsts fpul, fr8
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fsts fpul, fr9
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fsts fpul, fr10
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fsts fpul, fr11
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fsts fpul, fr12
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fsts fpul, fr13
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fsts fpul, fr14
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fsts fpul, fr15
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pop r0
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rts
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nop
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.endif
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.align 2
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a5a5: .long 0xa5a5a5a5
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main:
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.endm
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.macro exit val
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mov #\val, r5
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bra mexit
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nop
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.endm
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.macro pass
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bsr mpass
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nop
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.endm
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.macro fail
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bra mfail
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nop
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.endm
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# Branch if false -- 8k range
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.macro bf8k label
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bt .Lbf8k\@
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bra \label
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.Lbf8k\@:
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.endm
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# Branch if true -- 8k range
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.macro bt8k label
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bf .Lbt8k\@
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bra \label
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.Lbt8k\@:
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.endm
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# Assert value of register (any general register but r0)
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# Preserves r0 on stack, restores it on success.
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.macro assertreg val reg
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push r0
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mov.l .Larval\@, r0
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cmp/eq r0, \reg
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bt .Lar\@
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fail
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.align 2
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.Larval\@:
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.long \val
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.Lar\@: pop r0
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.endm
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# Assert value of register zero
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# Preserves r1 on stack, restores it on success.
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.macro assertreg0 val
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push r1
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mov.l .Lazval\@, r1
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cmp/eq r1, r0
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bt .Laz\@
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fail
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.align 2
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.Lazval\@:
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.long \val
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.Laz\@: pop r1
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.endm
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# Assert value of system register
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# [mach, macl, pr, dsr, a0, x0, x1, y0, y1, ...]
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.macro assert_sreg val reg
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push r0
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sts \reg, r0
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assertreg0 \val
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pop r0
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.endm
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# Assert value of system register that isn't directly stc-able
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# [a1, m0, m1, ...]
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.macro assert_sreg2 val reg
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push r0
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sts a0, r0
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push r0
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pcopy \reg, a0
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sts a0, r0
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assertreg0 \val
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pop r0
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lds r0, a0
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pop r0
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.endm
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# Assert value of control register
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# [gbr, vbr, ssr, spc, sgr, dbr, r[0-7]_bank, sr, mod, re, rs, ...]
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.macro assert_creg val reg
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push r0
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stc \reg, r0
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assertreg0 \val
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pop r0
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.endm
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# Assert integer value of fp register
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# Preserves r0 on stack, restores it on success
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# Assumes single-precision fp mode
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.macro assert_fpreg_i val freg
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push r0
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ftrc \freg, fpul
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sts fpul, r0
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assertreg0 \val
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pop r0
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.endm
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# Assert integer value of dp register
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# Preserves r0 on stack, restores it on success
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# Assumes double-precision fp mode
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.macro assert_dpreg_i val dreg
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push r0
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ftrc \dreg, fpul
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sts fpul, r0
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assertreg0 \val
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pop r0
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.endm
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# Assert hex value of fp register
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# Preserves r0 on stack, restores it on success
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# Assumes single-precision fp mode
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.macro assert_fpreg_x val freg
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push r0
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flds \freg, fpul
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sts fpul, r0
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assertreg0 \val
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pop r0
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.endm
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# Set FP bank 0
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# Saves and restores r0 and r1
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.macro bank0
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push r0
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push r1
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mov #32, r1
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shll16 r1
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not r1, r1
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sts fpscr, r0
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and r1, r0
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lds r0, fpscr
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pop r1
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pop r0
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.endm
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# Set FP bank 1
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.macro bank1
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push r0
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push r1
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mov #32, r1
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shll16 r1
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sts fpscr, r0
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or r1, r0
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lds r0, fpscr
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pop r1
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pop r0
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.endm
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# Set FP 32-bit xfer
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.macro sz_32
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push r0
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push r1
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mov #16, r1
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shll16 r1
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not r1, r1
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sts fpscr, r0
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and r1, r0
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lds r0, fpscr
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pop r1
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pop r0
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.endm
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# Set FP 64-bit xfer
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.macro sz_64
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push r0
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push r1
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mov #16, r1
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shll16 r1
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sts fpscr, r0
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or r1, r0
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lds r0, fpscr
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pop r1
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pop r0
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.endm
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# Set FP single precision
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.macro single_prec
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push r0
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push r1
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mov #8, r1
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shll16 r1
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not r1, r1
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sts fpscr, r0
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and r1, r0
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lds r0, fpscr
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pop r1
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pop r0
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.endm
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# Set FP double precision
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.macro double_prec
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push r0
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push r1
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mov #8, r1
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shll16 r1
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sts fpscr, r0
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or r1, r0
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lds r0, fpscr
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pop r1
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pop r0
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.endm
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.macro set_carry
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sett
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.endm
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.macro set_ovf
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sett
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.endm
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.macro clear_carry
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clrt
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.endm
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.macro clear_ovf
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clrt
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.endm
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# sets, clrs
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.macro set_grs_a5a5
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bsr mseta5
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nop
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.endm
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.macro set_greg val greg
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mov.l gregval\@, \greg
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bra set_greg\@
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nop
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.align 2
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gregval\@: .long \val
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set_greg\@:
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.endm
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.macro set_fprs_a5a5
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bsr mseta5_fp
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nop
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.endm
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.macro test_grs_a5a5
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bsr mtesta5
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nop
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.endm
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.macro test_fprs_a5a5
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bsr mtesta5_fp
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nop
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.endm
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.macro test_gr_a5a5 reg
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assertreg 0xa5a5a5a5 \reg
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.endm
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.macro test_fpr_a5a5 reg
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assert_fpreg_x 0xa5a5a5a5 \reg
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.endm
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.macro test_gr0_a5a5
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assertreg0 0xa5a5a5a5
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.endm
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# Perform a single to double precision floating point conversion.
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# Assumes correct settings of fpscr.
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.macro _s2d fpr dpr
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flds \fpr, fpul
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fcnvsd fpul, \dpr
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.endm
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# Manipulate the status register
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.macro set_sr val
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push r0
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mov.l .Lsrval\@, r0
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ldc r0, sr
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pop r0
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bra .Lsetsr\@
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nop
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.align 2
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.Lsrval\@:
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.long \val
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.Lsetsr\@:
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.endm
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.macro get_sr reg
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stc sr, \reg
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.endm
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.macro test_sr val
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push r0
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get_sr r0
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assertreg0 \val
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pop r0
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.endm
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.macro set_sr_bit val
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push r0
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push r1
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get_sr r0
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mov.l .Lsrbitval\@, r1
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or r1, r0
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ldc r0, sr
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pop r1
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pop r0
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bra .Lsrbit\@
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nop
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.align 2
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.Lsrbitval\@:
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.long \val
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.Lsrbit\@:
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.endm
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.macro test_sr_bit_set val
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push r0
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push r1
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get_sr r0
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mov.l .Ltsbsval\@, r1
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tst r1, r0
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bf .Ltsbs\@
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fail
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.align 2
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.Ltsbsval\@:
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.long \val
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.Ltsbs\@:
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pop r1
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pop r0
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.endm
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.macro test_sr_bit_clear val
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push r0
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push r1
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get_sr r0
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mov.l .Ltsbcval\@, r1
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not r0, r0
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tst r1, r0
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bf .Ltsbc\@
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fail
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.align 2
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.Ltsbcval\@:
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.long \val
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.Ltsbc\@:
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pop r1
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pop r0
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.endm
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# Set system registers
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.macro set_sreg val reg
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# [mach, macl, pr, dsr, a0, x0, x1, y0, y1, ...]
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push r0
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mov.l .Lssrval\@, r0
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lds r0, \reg
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pop r0
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bra .Lssr\@
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nop
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.align 2
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.Lssrval\@:
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.long \val
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.Lssr\@:
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.endm
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.macro set_sreg2 val reg
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# [a1, m0, m1, ...]
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push r0
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sts a0, r0
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push r0
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mov.l .Lssr2val\@, r0
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lds r0, a0
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pcopy a0, \reg
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pop r0
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lds r0, a0
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pop r0
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bra .Lssr2_\@
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nop
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.align 2
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.Lssr2val\@:
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.long \val
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.Lssr2_\@:
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.endm
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.macro set_creg val reg
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# [gbr, vbr, ssr, spc, sgr, dbr... ]
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push r0
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mov.l .Lscrval\@, r0
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ldc r0, \reg
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pop r0
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bra .Lscr\@
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nop
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.align 2
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.Lscrval\@:
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.long \val
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.Lscr\@:
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.endm
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.macro set_dctrue
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push r0
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sts dsr, r0
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or #1, r0
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lds r0, dsr
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pop r0
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.endm
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.macro set_dcfalse
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push r0
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sts dsr, r0
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not r0, r0
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or #1, r0
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not r0, r0
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lds r0, dsr
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pop r0
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.endm
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.macro assertmem addr val
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push r0
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mov.l .Laddr\@, r0
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mov.l @r0, r0
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assertreg0 \val
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bra .Lam\@
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nop
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.align 2
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.Laddr\@:
|
|
.long \addr
|
|
.Lam\@: pop r0
|
|
.endm
|