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1d506c26d9
This commit is the result of the following actions: - Running gdb/copyright.py to update all of the copyright headers to include 2024, - Manually updating a few files the copyright.py script told me to update, these files had copyright headers embedded within the file, - Regenerating gdbsupport/Makefile.in to refresh it's copyright date, - Using grep to find other files that still mentioned 2023. If these files were updated last year from 2022 to 2023 then I've updated them this year to 2024. I'm sure I've probably missed some dates. Feel free to fix them up as you spot them.
220 lines
5.6 KiB
C
220 lines
5.6 KiB
C
/* Blackfin External Bus Interface Unit (EBIU) SDRAM Controller (SDC) Model.
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Copyright (C) 2010-2024 Free Software Foundation, Inc.
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Contributed by Analog Devices, Inc.
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This file is part of simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This must come before any other includes. */
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#include "defs.h"
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#include "sim-main.h"
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#include "devices.h"
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#include "dv-bfin_ebiu_sdc.h"
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struct bfin_ebiu_sdc
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{
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bu32 base;
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int type;
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bu32 reg_size, bank_size;
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/* Order after here is important -- matches hardware MMR layout. */
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bu32 sdgctl;
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bu32 sdbctl; /* 16bit on most parts ... */
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bu16 BFIN_MMR_16(sdrrc);
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bu16 BFIN_MMR_16(sdstat);
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};
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#define mmr_base() offsetof(struct bfin_ebiu_sdc, sdgctl)
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#define mmr_offset(mmr) (offsetof(struct bfin_ebiu_sdc, mmr) - mmr_base())
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static const char * const mmr_names[] =
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{
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"EBIU_SDGCTL", "EBIU_SDBCTL", "EBIU_SDRRC", "EBIU_SDSTAT",
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};
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#define mmr_name(off) mmr_names[(off) / 4]
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static unsigned
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bfin_ebiu_sdc_io_write_buffer (struct hw *me, const void *source,
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int space, address_word addr, unsigned nr_bytes)
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{
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struct bfin_ebiu_sdc *sdc = hw_data (me);
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bu32 mmr_off;
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bu32 value;
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bu16 *value16p;
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bu32 *value32p;
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void *valuep;
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/* Invalid access mode is higher priority than missing register. */
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if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, true))
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return 0;
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if (nr_bytes == 4)
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value = dv_load_4 (source);
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else
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value = dv_load_2 (source);
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mmr_off = addr - sdc->base;
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valuep = (void *)((uintptr_t)sdc + mmr_base() + mmr_off);
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value16p = valuep;
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value32p = valuep;
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HW_TRACE_WRITE ();
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switch (mmr_off)
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{
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case mmr_offset(sdgctl):
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/* XXX: SRFS should make external mem unreadable. */
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*value32p = value;
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break;
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case mmr_offset(sdbctl):
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if (sdc->type == 561)
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{
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if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
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return 0;
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*value32p = value;
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}
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else
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{
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if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
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return 0;
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*value16p = value;
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}
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break;
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case mmr_offset(sdrrc):
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if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
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return 0;
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*value16p = value;
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break;
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case mmr_offset(sdstat):
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if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
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return 0;
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/* XXX: Some bits are W1C ... */
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break;
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}
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return nr_bytes;
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}
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static unsigned
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bfin_ebiu_sdc_io_read_buffer (struct hw *me, void *dest,
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int space, address_word addr, unsigned nr_bytes)
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{
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struct bfin_ebiu_sdc *sdc = hw_data (me);
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bu32 mmr_off;
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bu32 *value32p;
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bu16 *value16p;
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void *valuep;
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/* Invalid access mode is higher priority than missing register. */
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if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, false))
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return 0;
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mmr_off = addr - sdc->base;
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valuep = (void *)((uintptr_t)sdc + mmr_base() + mmr_off);
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value16p = valuep;
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value32p = valuep;
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HW_TRACE_READ ();
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switch (mmr_off)
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{
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case mmr_offset(sdgctl):
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dv_store_4 (dest, *value32p);
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break;
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case mmr_offset(sdbctl):
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if (sdc->type == 561)
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{
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if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false))
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return 0;
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dv_store_4 (dest, *value32p);
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}
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else
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{
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if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
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return 0;
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dv_store_2 (dest, *value16p);
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}
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break;
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case mmr_offset(sdrrc):
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case mmr_offset(sdstat):
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if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
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return 0;
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dv_store_2 (dest, *value16p);
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break;
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}
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return nr_bytes;
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}
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static void
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attach_bfin_ebiu_sdc_regs (struct hw *me, struct bfin_ebiu_sdc *sdc)
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{
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address_word attach_address;
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int attach_space;
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unsigned attach_size;
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reg_property_spec reg;
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if (hw_find_property (me, "reg") == NULL)
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hw_abort (me, "Missing \"reg\" property");
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if (!hw_find_reg_array_property (me, "reg", 0, ®))
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hw_abort (me, "\"reg\" property must contain three addr/size entries");
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hw_unit_address_to_attach_address (hw_parent (me),
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®.address,
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&attach_space, &attach_address, me);
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hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me);
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if (attach_size != BFIN_MMR_EBIU_SDC_SIZE)
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hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_EBIU_SDC_SIZE);
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hw_attach_address (hw_parent (me),
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0, attach_space, attach_address, attach_size, me);
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sdc->base = attach_address;
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}
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static void
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bfin_ebiu_sdc_finish (struct hw *me)
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{
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struct bfin_ebiu_sdc *sdc;
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sdc = HW_ZALLOC (me, struct bfin_ebiu_sdc);
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set_hw_data (me, sdc);
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set_hw_io_read_buffer (me, bfin_ebiu_sdc_io_read_buffer);
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set_hw_io_write_buffer (me, bfin_ebiu_sdc_io_write_buffer);
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attach_bfin_ebiu_sdc_regs (me, sdc);
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sdc->type = hw_find_integer_property (me, "type");
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/* Initialize the SDC. */
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sdc->sdgctl = 0xE0088849;
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sdc->sdbctl = 0x00000000;
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sdc->sdrrc = 0x081A;
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sdc->sdstat = 0x0008;
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/* XXX: We boot with 64M external memory by default ... */
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sdc->sdbctl |= EBE | EBSZ_64 | EBCAW_10;
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}
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const struct hw_descriptor dv_bfin_ebiu_sdc_descriptor[] =
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{
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{"bfin_ebiu_sdc", bfin_ebiu_sdc_finish,},
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{NULL, NULL},
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};
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