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fd67aa1129
Adds two new external authors to etc/update-copyright.py to cover bfd/ax_tls.m4, and adds gprofng to dirs handled automatically, then updates copyright messages as follows: 1) Update cgen/utils.scm emitted copyrights. 2) Run "etc/update-copyright.py --this-year" with an extra external author I haven't committed, 'Kalray SA.', to cover gas testsuite files (which should have their copyright message removed). 3) Build with --enable-maintainer-mode --enable-cgen-maint=yes. 4) Check out */po/*.pot which we don't update frequently.
457 lines
11 KiB
Plaintext
457 lines
11 KiB
Plaintext
/* itbl-parse.y
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Copyright (C) 1997-2024 Free Software Foundation, Inc.
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This file is part of GAS, the GNU Assembler.
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GAS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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GAS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GAS; see the file COPYING. If not, write to the Free
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Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
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02110-1301, USA. */
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%{
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/*
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Yacc grammar for instruction table entries.
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=======================================================================
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Original Instruction table specification document:
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MIPS Coprocessor Table Specification
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====================================
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This document describes the format of the MIPS coprocessor table. The
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table specifies a list of valid functions, data registers and control
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registers that can be used in coprocessor instructions. This list,
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together with the coprocessor instruction classes listed below,
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specifies the complete list of coprocessor instructions that will
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be recognized and assembled by the GNU assembler. In effect,
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this makes the GNU assembler table-driven, where the table is
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specified by the programmer.
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The table is an ordinary text file that the GNU assembler reads when
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it starts. Using the information in the table, the assembler
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generates an internal list of valid coprocessor registers and
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functions. The assembler uses this internal list in addition to the
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standard MIPS registers and instructions which are built-in to the
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assembler during code generation.
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To specify the coprocessor table when invoking the GNU assembler, use
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the command line option "--itbl file", where file is the
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complete name of the table, including path and extension.
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Examples:
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gas -t cop.tbl test.s -o test.o
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gas -t /usr/local/lib/cop.tbl test.s -o test.o
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gas --itbl d:\gnu\data\cop.tbl test.s -o test.o
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Only one table may be supplied during a single invocation of
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the assembler.
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Instruction classes
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===================
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Below is a list of the valid coprocessor instruction classes for
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any given coprocessor "z". These instructions are already recognized
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by the assembler, and are listed here only for reference.
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Class format instructions
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-------------------------------------------------
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Class1:
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op base rt offset
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LWCz rt,offset (base)
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SWCz rt,offset (base)
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Class2:
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COPz sub rt rd 0
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MTCz rt,rd
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MFCz rt,rd
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CTCz rt,rd
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CFCz rt,rd
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Class3:
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COPz CO cofun
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COPz cofun
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Class4:
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COPz BC br offset
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BCzT offset
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BCzF offset
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Class5:
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COPz sub rt rd 0
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DMFCz rt,rd
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DMTCz rt,rd
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Class6:
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op base rt offset
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LDCz rt,offset (base)
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SDCz rt,offset (base)
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Class7:
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COPz BC br offset
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BCzTL offset
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BCzFL offset
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The coprocessor table defines coprocessor-specific registers that can
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be used with all of the above classes of instructions, where
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appropriate. It also defines additional coprocessor-specific
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functions for Class3 (COPz cofun) instructions, Thus, the table allows
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the programmer to use convenient mnemonics and operands for these
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functions, instead of the COPz mmenmonic and cofun operand.
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The names of the MIPS general registers and their aliases are defined
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by the assembler and will be recognized as valid register names by the
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assembler when used (where allowed) in coprocessor instructions.
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However, the names and values of all coprocessor data and control
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register mnemonics must be specified in the coprocessor table.
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Table Grammar
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=============
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Here is the grammar for the coprocessor table:
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table -> entry*
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entry -> [z entrydef] [comment] '\n'
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entrydef -> type name val
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entrydef -> 'insn' name val funcdef ; type of entry (instruction)
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z -> 'p'['0'..'3'] ; processor number
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type -> ['dreg' | 'creg' | 'greg' ] ; type of entry (register)
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; 'dreg', 'creg' or 'greg' specifies a data, control, or general
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; register mnemonic, respectively
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name -> [ltr|dec]* ; mnemonic of register/function
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val -> [dec|hex] ; register/function number (integer constant)
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funcdef -> frange flags fields
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; bitfield range for opcode
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; list of fields' formats
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fields -> field*
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field -> [','] ftype frange flags
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flags -> ['*' flagexpr]
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flagexpr -> '[' flagexpr ']'
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flagexpr -> val '|' flagexpr
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ftype -> [ type | 'immed' | 'addr' ]
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; 'immed' specifies an immediate value; see grammar for "val" above
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; 'addr' specifies a C identifier; name of symbol to be resolved at
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; link time
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frange -> ':' val '-' val ; starting to ending bit positions, where
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; where 0 is least significant bit
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frange -> (null) ; default range of 31-0 will be assumed
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comment -> [';'|'#'] [char]*
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char -> any printable character
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ltr -> ['a'..'z'|'A'..'Z']
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dec -> ['0'..'9']* ; value in decimal
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hex -> '0x'['0'..'9' | 'a'..'f' | 'A'..'F']* ; value in hexadecimal
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Examples
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========
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Example 1:
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The table:
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p1 dreg d1 1 ; data register "d1" for COP1 has value 1
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p1 creg c3 3 ; ctrl register "c3" for COP1 has value 3
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p3 func fill 0x1f:24-20 ; function "fill" for COP3 has value 31 and
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; no fields
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will allow the assembler to accept the following coprocessor instructions:
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LWC1 d1,0x100 ($2)
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fill
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Here, the general purpose register "$2", and instruction "LWC1", are standard
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mnemonics built-in to the MIPS assembler.
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Example 2:
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The table:
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p3 dreg d3 3 ; data register "d3" for COP3 has value 3
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p3 creg c2 22 ; control register "c2" for COP3 has value 22
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p3 func fee 0x1f:24-20 dreg:17-13 creg:12-8 immed:7-0
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; function "fee" for COP3 has value 31, and 3 fields
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; consisting of a data register, a control register,
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; and an immediate value.
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will allow the assembler to accept the following coprocessor instruction:
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fee d3,c2,0x1
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and will emit the object code:
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31-26 25 24-20 19-18 17-13 12-8 7-0
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COPz CO fun dreg creg immed
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010011 1 11111 00 00011 10110 00000001
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0x4ff07601
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Example 3:
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The table:
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p3 dreg d3 3 ; data register "d3" for COP3 has value 3
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p3 creg c2 22 ; control register "c2" for COP3 has value 22
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p3 func fuu 0x01f00001 dreg:17-13 creg:12-8
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will allow the assembler to accept the following coprocessor
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instruction:
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fuu d3,c2
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and will emit the object code:
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31-26 25 24-20 19-18 17-13 12-8 7-0
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COPz CO fun dreg creg
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010011 1 11111 00 00011 10110 00000001
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0x4ff07601
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In this way, the programmer can force arbitrary bits of an instruction
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to have predefined values.
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=======================================================================
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Additional notes:
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Encoding of ranges:
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To handle more than one bit position range within an instruction,
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use 0s to mask out the ranges which don't apply.
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May decide to modify the syntax to allow commas separate multiple
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ranges within an instruction (range','range).
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Changes in grammar:
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The number of parms argument to the function entry
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was deleted from the original format such that we now count the fields.
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----
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FIXME! should really change lexical analyzer
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to recognize 'dreg' etc. in context sensitive way.
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Currently function names or mnemonics may be incorrectly parsed as keywords
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FIXME! hex is ambiguous with any digit
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*/
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#include "as.h"
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#include "itbl-lex.h"
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#include "itbl-ops.h"
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/* #define DEBUG */
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#ifdef DEBUG
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#ifndef DBG_LVL
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#define DBG_LVL 1
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#endif
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#else
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#define DBG_LVL 0
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#endif
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#if DBG_LVL >= 1
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#define DBG(x) printf x
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#else
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#define DBG(x)
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#endif
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#if DBG_LVL >= 2
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#define DBGL2(x) printf x
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#else
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#define DBGL2(x)
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#endif
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static int sbit, ebit;
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static struct itbl_entry *insn=0;
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static void yyerror (const char *);
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%}
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%union
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{
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char *str;
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int num;
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int processor;
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unsigned long val;
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}
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%token DREG CREG GREG IMMED ADDR INSN NUM ID NL PNUM
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%type <val> value flags flagexpr
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%type <num> number NUM ftype regtype pnum PNUM
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%type <str> ID name
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%start insntbl
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%%
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insntbl:
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entrys
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;
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entrys:
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entry entrys
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;
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entry:
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pnum regtype name value NL
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{
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DBG (("line %d: entry pnum=%d type=%d name=%s value=x%x\n",
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insntbl_line, $1, $2, $3, $4));
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itbl_add_reg ($1, $2, $3, $4);
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}
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| pnum INSN name value range flags
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{
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DBG (("line %d: entry pnum=%d type=INSN name=%s value=x%x",
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insntbl_line, $1, $3, $4));
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DBG ((" sbit=%d ebit=%d flags=0x%x\n", sbit, ebit, $6));
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insn=itbl_add_insn ($1, $3, $4, sbit, ebit, $6);
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}
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fieldspecs NL
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{}
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| NL
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| error NL
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;
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fieldspecs:
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',' fieldspec fieldspecs
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| fieldspec fieldspecs
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;
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ftype:
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regtype
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{
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DBGL2 (("ftype\n"));
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$$ = $1;
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}
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| ADDR
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{
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DBGL2 (("addr\n"));
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$$ = ADDR;
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}
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| IMMED
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{
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DBGL2 (("immed\n"));
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$$ = IMMED;
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}
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;
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fieldspec:
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ftype range flags
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{
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DBG (("line %d: field type=%d sbit=%d ebit=%d, flags=0x%x\n",
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insntbl_line, $1, sbit, ebit, $3));
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itbl_add_operand (insn, $1, sbit, ebit, $3);
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}
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;
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flagexpr:
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NUM '|' flagexpr
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{
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$$ = $1 | $3;
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}
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| '[' flagexpr ']'
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{
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$$ = $2;
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}
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| NUM
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{
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$$ = $1;
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}
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;
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flags:
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'*' flagexpr
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{
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DBGL2 (("flags=%d\n", $2));
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$$ = $2;
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}
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{
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$$ = 0;
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}
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;
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range:
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':' NUM '-' NUM
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{
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DBGL2 (("range %d %d\n", $2, $4));
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sbit = $2;
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ebit = $4;
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}
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{
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sbit = 31;
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ebit = 0;
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}
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;
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pnum:
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PNUM
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{
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DBGL2 (("pnum=%d\n",$1));
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$$ = $1;
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}
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;
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regtype:
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DREG
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{
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DBGL2 (("dreg\n"));
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$$ = DREG;
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}
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| CREG
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{
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DBGL2 (("creg\n"));
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$$ = CREG;
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}
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| GREG
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{
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DBGL2 (("greg\n"));
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$$ = GREG;
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}
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;
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name:
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ID
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{
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DBGL2 (("name=%s\n",$1));
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$$ = $1;
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}
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;
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number:
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NUM
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{
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DBGL2 (("num=%d\n",$1));
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$$ = $1;
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}
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;
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value:
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NUM
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{
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DBGL2 (("val=x%x\n",$1));
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$$ = $1;
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}
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;
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%%
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static void
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yyerror (const char *msg)
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{
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printf ("line %d: %s\n", insntbl_line, msg);
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}
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