Commit Graph

2733 Commits

Author SHA1 Message Date
Maciej W. Rozycki
fdfb475260 MIPS/opcodes: Remove an incorrect MT ASE reference in MFC0/MTC0 decoding
The `sel' operand of CP0 move instructions is a part of the base ISA and
has nothing to do with the MT ASE.

	opcodes/
	* mips-dis.c (print_insn_args) <default>: Remove an MT ASE
	reference in CP0 move operand decoding.
2017-05-15 13:57:07 +01:00
Maciej W. Rozycki
a4f8991513 MIPS16/opcodes: Make the handling of BREAK and SDBBP consistent
Disassemble the MIPS16 BREAK and SDBBP instruction's immediate operand
in the hexadecimal rather than decimal numeral system and add respective
operandless variants with an implicit 0 operand, making our handling of
these instructions consistent with how we have processed their regular
MIPS and microMIPS counterparts since forever.

	opcodes/
	* mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
	type to hexadecimal.
	(mips16_opcodes): Add operandless "break" and "sdbbp" entries.

	binutils/
	* testsuite/binutils-all/mips/mips16-extend-insn.d: Adjust BREAK
	and SDBBP disassembly.

	gas/
	* testsuite/gas/mips/mips16.d: Adjust BREAK disassembly.
	* testsuite/gas/mips/mips16-64@mips16.d: Likewise.
	* testsuite/gas/mips/mips16-64.d: Likewise.
	* testsuite/gas/mips/mips16-64@mips16-64.d: Likewise.
	* testsuite/gas/mips/mips16-macro.d: Likewise.
	* testsuite/gas/mips/mips16-64@mips16-macro.d: Likewise.
	* testsuite/gas/mips/mips16-sub.d: Likewise.
	* testsuite/gas/mips/mips16-32@mips16-sub.d: Likewise.
2017-05-12 01:12:10 +01:00
Maciej W. Rozycki
99e2d67a0e MIPS/opcodes: Mark descriptive SYNC mnemonics as aliases
Following the way how descriptive SYNC mnemonics have been defined in
the architecture[1][2] mark them as aliases, so that the generic SYNC
instruction can be alternatively disassembled along with its immediate
operand, as noted in the documents referred.

References:

[1] "MIPS Architecture For Programmers, Volume II-A: The MIPS32
    Instruction Set", MIPS Technologies, Inc., Document Number: MD00086,
    Revision 5.04, December 11, 2013, Table 4.7 "Encodings of the
    Bits[10:6] of the SYNC instruction; the SType Field", p. 305

[2] "MIPS Architecture for Programmers, Volume II-B: The microMIPS32
    Instruction Set", MIPS Technologies, Inc., Document Number: MD00582,
    Revision 5.04, January 15, 2014, Table 5.28 "Encodings of the
    Bits[10:6] of the SYNC instruction; the SType Field", p. 481

	opcodes/
	* mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
	"syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
	"sync_rmb" and "sync_wmb" as aliases.
	* micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
	"sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.

	gas/
	* testsuite/gas/mips/mips32r2-sync-1.d: New test.
	* testsuite/gas/mips/micromips@mips32r2-sync-1.d: New test.
	* testsuite/gas/mips/mips.exp: Run the new tests.
2017-05-12 00:48:19 +01:00
Claudiu Zissulescu
53a346d823 [ARC] Object attributes.
gas/
2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>

	* testsuite/gas/arc/attr-arc600.d: New file.
	* testsuite/gas/arc/attr-arc600_mul32x16.d: Likewise.
	* testsuite/gas/arc/attr-arc600_norm.d: Likewise.
	* testsuite/gas/arc/attr-arc601.d: Likewise.
	* testsuite/gas/arc/attr-arc601_mul32x16.d: Likewise.
	* testsuite/gas/arc/attr-arc601_mul64.d: Likewise.
	* testsuite/gas/arc/attr-arc601_norm.d: Likewise.
	* testsuite/gas/arc/attr-arc700.d: Likewise.
	* testsuite/gas/arc/attr-arcem.d: Likewise.
	* testsuite/gas/arc/attr-archs.d: Likewise.
	* testsuite/gas/arc/attr-autodetect-1.d: Likewise.
	* testsuite/gas/arc/attr-autodetect-1.s: Likewise.
	* testsuite/gas/arc/attr-cpu-a601.d: Likewise.
	* testsuite/gas/arc/attr-cpu-a601.s: Likewise.
	* testsuite/gas/arc/attr-cpu-a700.d: Likewise.
	* testsuite/gas/arc/attr-cpu-a700.s: Likewise.
	* testsuite/gas/arc/attr-cpu-em.d: Likewise.
	* testsuite/gas/arc/attr-cpu-em.s: Likewise.
	* testsuite/gas/arc/attr-cpu-hs.d: Likewise.
	* testsuite/gas/arc/attr-cpu-hs.s: Likewise.
	* testsuite/gas/arc/attr-em.d: Likewise.
	* testsuite/gas/arc/attr-em4.d: Likewise.
	* testsuite/gas/arc/attr-em4_dmips.d: Likewise.
	* testsuite/gas/arc/attr-em4_fpuda.d: Likewise.
	* testsuite/gas/arc/attr-em4_fpus.d: Likewise.
	* testsuite/gas/arc/attr-hs.d: Likewise.
	* testsuite/gas/arc/attr-hs34.d: Likewise.
	* testsuite/gas/arc/attr-hs38.d: Likewise.
	* testsuite/gas/arc/attr-hs38_linux.d: Likewise.
	* testsuite/gas/arc/attr-mul64.d: Likewise.
	* testsuite/gas/arc/attr-name.d: Likewise.
	* testsuite/gas/arc/attr-name.s: Likewise.
	* testsuite/gas/arc/attr-nps400.d: Likewise.
	* testsuite/gas/arc/attr-override-mcpu.d: Likewise.
	* testsuite/gas/arc/attr-override-mcpu.s
	* testsuite/gas/arc/attr-quarkse_em.d: Likewise.
	* testsuite/gas/arc/blank.s: Likewise.
	* testsuite/gas/elf/section2.e-arc: Likewise.
	* testsuite/gas/arc/cpu-pseudop-1.d: Update test.
	* testsuite/gas/arc/cpu-pseudop-2.d: Likewise.
	* testsuite/gas/arc/nps400-0.d: Likewise.
	* testsuite/gas/elf/elf.exp: Set target_machine for ARC.
	* config/tc-arc.c (opcode/arc-attrs.h): Include.
	(ARC_GET_FLAG, ARC_SET_FLAG, streq): Define.
	(arc_attribute): Declare new function.
	(md_pseudo_table): Add arc_attribute.
	(cpu_types): Rename default cpu features.
	(selected_cpu): Set the default OSABI flag.
	(mpy_option): New variable.
	(pic_option): Likewise.
	(sda_option): Likewise.
	(tls_option): Likewise.
	(feature_type, feature_list): Remove.
	(arc_initial_eflag): Likewise.
	(attributes_set_explicitly): New variable.
	(arc_check_feature): Check also for the conflicting features.
	(arc_select_cpu): Refactor assignment of selected_cpu.eflags.
	(arc_option): Remove setting of private flags and architecture.
	(check_cpu_feature): Refactor feature names.
	(autodetect_attributes): New function.
	(assemble_tokens): Use above function.
	(md_parse_option): Refactor feature names.
	(arc_attribute): New function.
	(arc_set_attribute_int): Likewise.
	(arc_set_attribute_string): Likewise.
	(arc_stralloc): Likewise.
	(arc_set_public_attributes): Likewise.
	(arc_md_end): Likewise.
	(arc_copy_symbol_attributes): Likewise.
	(rc_convert_symbolic_attribute): Likewise.
	* config/tc-arc.h (md_end): Define.
	(CONVERT_SYMBOLIC_ATTRIBUTE): Likewise.
	(TC_COPY_SYMBOL_ATTRIBUTES): Likewise.
	* doc/c-arc.texi: Document ARC object attributes.

binutils/
2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>

	* readelf.c (decode_ARC_machine_flags): Recognize OSABI v4.
	(get_arc_section_type_name): New function.
	(get_section_type_name): Use the above function.
	(display_arc_attribute): New function.
	(process_arc_specific): Likewise.
	(process_arch_specific): Handle ARC specific information.
	* testsuite/binutils-all/strip-3.d: Consider ARC.attributes
	section.

include/
2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>

	* elf/arc.h (SHT_ARC_ATTRIBUTES): Define.
	(Tag_ARC_*): Define.
	(E_ARC_OSABI_V4): Define.
	(E_ARC_OSABI_CURRENT): Reassign it.
	(TAG_CPU_*): Define.
	* opcode/arc-attrs.h: New file.
	* opcode/arc.h (insn_subclass_t): Assign enum values.
	(insn_subclass_t): Update enum with QUARKSE1, QUARKSE2, and LL64.
	(ARC_EA, ARC_CD, ARC_LLOCK, ARC_ATOMIC, ARC_MPY, ARC_MULT)
	(ARC_NPS400, ARC_DPFP, ARC_SPFP, ARC_FPU, ARC_FPUDA, ARC_SWAP)
	(ARC_NORM, ARC_BSCAN, ARC_UIX, ARC_TSTAMP, ARC_VBFDW)
	(ARC_BARREL, ARC_DSPA, ARC_SHIFT, ARC_INTR, ARC_DIV, ARC_XMAC)
	(ARC_CRC): Delete.

bfd/
2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>

	* elf32-arc.c (FEATURE_LIST_NAME): Define.
	(CONFLICT_LIST): Likewise.
	(opcode/arc-attrs.h): Include.
	(arc_elf_print_private_bfd_data): Print OSABI v4 flag.
	(arc_extract_features): New file.
	(arc_stralloc): Likewise.
	(arc_elf_merge_attributes): Likewise.
	(arc_elf_merge_private_bfd_data): Use object attributes.
	(bfd_arc_get_mach_from_attributes): New function.
	(arc_elf_object_p): Use object attributes.
	(arc_elf_final_write_processing): Likewise.
	(elf32_arc_obj_attrs_arg_type): New function.
	(elf32_arc_obj_attrs_handle_unknown): Likewise.
	(elf32_arc_section_from_shdr): Likewise.
	(elf_backend_obj_attrs_vendor): Define.
	(elf_backend_obj_attrs_section): Likewise.
	(elf_backend_obj_attrs_arg_type): Likewise.
	(elf_backend_obj_attrs_section_type): Likewise.
	(elf_backend_obj_attrs_handle_unknown): Likewise.
	(elf_backend_section_from_shdr): Likewise.

ld/
2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>

	* testsuite/ld-arc/attr-merge-0.d: New file.
	* testsuite/ld-arc/attr-merge-0.s: Likewise.
	* testsuite/ld-arc/attr-merge-0e.s: Likewise.
	* testsuite/ld-arc/attr-merge-1.d: Likewise.
	* testsuite/ld-arc/attr-merge-1.s: Likewise.
	* testsuite/ld-arc/attr-merge-1e.s: Likewise.
	* testsuite/ld-arc/attr-merge-2.d: Likewise.
	* testsuite/ld-arc/attr-merge-2.s: Likewise.
	* testsuite/ld-arc/attr-merge-3.d: Likewise.
	* testsuite/ld-arc/attr-merge-3.s: Likewise.
	* testsuite/ld-arc/attr-merge-3e.s: Likewise.
	* testsuite/ld-arc/attr-merge-4.s: Likewise.
	* testsuite/ld-arc/attr-merge-5.d: Likewise.
	* testsuite/ld-arc/attr-merge-5a.s: Likewise.
	* testsuite/ld-arc/attr-merge-5b.s: Likewise.
	* testsuite/ld-arc/attr-merge-conflict-isa.d: Likewise.
	* testsuite/ld-arc/attr-merge-err-isa.d: Likewise.
	* testsuite/ld-arc/attr-merge-incompatible-cpu.d: Likewise.
	* testsuite/ld-arc/got-01.d: Update test.
	* testsuite/ld-arc/attr-merge-err-quarkse.d: New file.
	* testsuite/ld-arc/attr-quarkse.s: Likewise.
	* testsuite/ld-arc/attr-quarkse2.s: Likewise.

opcodes/
2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-dis.c (parse_option): Update quarkse_em option..
	* arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
	QUARKSE1.
	(dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
2017-05-10 14:42:22 +02:00
Kito Cheng
f91d48deb2 RISC-V: Fix disassemble for c.li, c.andi and c.addiw
ChangeLog

2017-05-03  Kito Cheng  <kito.cheng@gmail.com>

        * riscv-dis.c (print_insn_args): Handle 'Co' operands.
2017-05-04 03:20:30 -07:00
Michael Clark
43e379d74c RISC-V: Change CALL macro to use ra as the temporary address register
e.g.

    1:  auipc ra, %pcrel_hi(symbol)
        jalr  ra, %pcrel_lo(1b)(ra)

The use of ra instead of t1 for address construction provides an
opportunity for a microarchitecture to elide the write of the
destination address, and instead read the target address as an
immediate spread across the fused auipc+jalr pair. The link
register ra in the jalr overwrites the target address temporary.

2017-05-01  Michael Clark  <michaeljclark@mac.com>

	* riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
	register.
2017-05-02 15:19:07 -07:00
Maciej W. Rozycki
a4ddc54ec1 MIPS16/opcodes: Keep the LSB of PC-relative offsets in disassembly
Correct the disassembly of the PC-relative immediate argument of the
MIPS16 synthetic LA, LW, DLA and LD instructions and do not mask the
LSB, which in this case is a part of the data address rather than the
ISA bit and has to be fully presented.

	opcodes/
	* mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
	and branches and not synthetic data instructions.

	binutils/
	* testsuite/binutils-all/mips/mips16-undecoded.d: Adjust the
	disassembly of PC-relative LA and LW synthetic instructions.
2017-05-02 11:58:44 +01:00
Bernd Edlinger
fe50e98c9a Fix value in comment of disassembled ARM type A opcodes.
* arm-dis.c (print_insn_thumb32): Fix value_in_comment.
2017-05-02 10:28:09 +01:00
Claudiu Zissulescu
126124cc0f [ARC] Enhance enter/leave mnemonics.
enter/leave mnemonics are enhanced to not only accept register ranges
but also single register (i.e., r13) or even no GPR register at all.

gas/
2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>

	* testsuite/gas/arc/leave_enter.d: Update test.
	* testsuite/gas/arc/leave_enter.s: Likewise.

opcodes/
2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
	* arc-opc.c (insert_r13el): New function.
	(R13_EL): Define.
	* arc-tbl.h: Add new enter/leave variants.
2017-04-25 17:07:00 +02:00
Claudiu Zissulescu
be6a24d8ea [ARC] Prefer NOP instead of MOV 0,0
NOP and MOV 0,0 are having the same encoding. As MOV mnemonic is
located before NOP in the instruction table, the disassembler prints
MOV 0,0 for NOP. Reorder the instructions such that NOP is first.

gas/
2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>

	* testsuite/gas/arc/b.d: Update test.
	* testsuite/gas/arc/noargs_hs.d: Likewise.

opcode/
2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-tbl.h: Reorder NOP entry to be before MOV instructions.
2017-04-25 17:07:00 +02:00
Maciej W. Rozycki
0348fd79d4 MIPS16/opcodes: Add `-M no-aliases' disassembler option help text
Complement commit 986e18a5a9 ("Add a second 'pinfo' member to
mips_opcode to extend number of available bits"),
<https://sourceware.org/ml/binutils/2005-01/msg00261.html>, and add a
help text for the `-M no-aliases' disassembler option.

	opcodes/
	* mips-dis.c (print_mips_disassembler_options): Add
	`no-aliases'.
2017-04-25 11:57:57 +01:00
Maciej W. Rozycki
6e3d1f0728 MIPS16/opcodes: Annotate instruction aliases
Complement commit 986e18a5a9 ("Add a second 'pinfo' member to
mips_opcode to extend number of available bits"),
<https://sourceware.org/ml/binutils/2005-01/msg00261.html>, and annotate
MIPS16 NOP, LA, DLA and the synthetic forms of LD and LW instructions as
aliases.  These correspond to MOVE, and the PC-relative ADDIU, DADDIU,
LD and LW hardware instructions respectively.

	binutils/
	* testsuite/binutils-all/mips/mips16-alias.d: New test.
	* testsuite/binutils-all/mips/mips16-noalias.d: New test.
	* testsuite/binutils-all/mips/mips16-alias.s: New test source.
	* testsuite/binutils-all/mips/mips.exp: Run the new tests.

	opcodes/
	* mips16-opc.c (AL): New macro.
	(mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
	of "ld" and "lw" as aliases.
2017-04-25 11:55:34 +01:00
Tamar Christina
957f6b39ca Fix snafu in aarch64 opcodes debugging statement.
* aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
	arguments.
2017-04-24 11:55:44 +01:00
Alan Modra
a8cc8a548e PowerPC VLE insn set additions
opcodes/
	* ppc-opc.c (ELEV): Define.
	(vle_opcodes): Add se_rfgi and e_sc.
	(powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
	for E200Z4.
gas/
	* testsuite/gas/ppc/vle.s: Format.  Add se_rfgi and e_sc.
	* testsuite/gas/ppc/vle.d: Update.
2017-04-22 17:45:50 +09:30
Jose E. Marchesi
3ab87b6883 opcodes: mark SPARC RETT instructions as v6notv9.
This prevents the disassembler to show `return' instructions as
`rett' in V9 and later architectures.

opcodes/ChangeLog:

2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
2017-04-21 05:19:06 -07:00
Nick Clifton
792f174f8a Fix detection of illegal AArch64 opcodes that resemble LD1R, LD2R, LD3R and LD4R.
PR binutils/21380
opcodes	* aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
	LD3R and LD4R.

gas	* testsuite/gas/aarch64/illegal-3.s: New file.
	* testsuite/gas/aarch64/illegal-3.d: New file.
2017-04-21 12:18:06 +01:00
Alan Modra
4274208406 Regen cgen files
* epiphany-desc.c: Regenerate.
	* fr30-desc.c: Regenerate.
	* frv-desc.c: Regenerate.
	* ip2k-desc.c: Regenerate.
	* iq2000-desc.c: Regenerate.
	* lm32-desc.c: Regenerate.
	* m32c-desc.c: Regenerate.
	* m32r-desc.c: Regenerate.
	* mep-desc.c: Regenerate.
	* mt-desc.c: Regenerate.
	* or1k-desc.c: Regenerate.
	* xc16x-desc.c: Regenerate.
	* xstormy16-desc.c: Regenerate.
2017-04-13 21:38:04 +09:30
Alan Modra
c03dc33b60 Reorder PPC_OPCODE_* and set PPC_OPCODE_TMR for e6500
PPC_OPCODE_* renumbered to fill the gaps left by previous patches,
and reordered chronologically just because.  I kept PPC_OPCODE_TMR
because presumably it might be used in future APUinfo for e6500.

include/
	* opcode/ppc.h (PPC_OPCODE_*): Renumber and order chronologically.
	(PPC_OPCODE_SPE): Comment on this and other bits used for APUinfo.
opcodes/
	* ppc-dis.c (ppc_opts): Formatting.  Set PPC_OPCODE_TMR for e6500.
	* ppc-opc.c (powerpc_opcodes <mftmr, mttmr>): Remove now
	unnecessary E6500.
2017-04-11 07:43:21 +09:30
Alan Modra
ef85eab0ec Bye bye PPC_OPCODE_HTM and -mhtm
The -mhtm option is fairly useless too.

include/
	* opcode/ppc.h (PPC_OPCODE_HTM): Delete.
gas/
	* config/tc-ppc.c (md_show_usage): Delete mention of -mhtm.
	* testsuite/gas/ppc/htm.d: Pass -mpower8 and -Mpower8.
opcodes/
	* ppc-dis.c (ppc_opts): Remove PPC_OPCODE_HTM and "htm".
	* ppc-opc.c (PPCHTM): Define as PPC_OPCODE_POWER8.
2017-04-11 07:40:24 +09:30
Alan Modra
9570835e55 Bye Bye PPC_OPCODE_VSX3
This bit is also useless as it can be replaced with PPC_OPCODE_POWER9.
Defining the VSX2 and VSX3 selection based on cpu bits also lets the
assembler/disassembler distinguish between the power7 VSX opcodes and
the power8 ones.  Note that this change means -mvsx now reverts back
to just adding the power7 VSX insns.

include/
	* opcode/ppc.h (PPC_OPCODE_VSX3): Delete.
opcodes/
	* ppc-dis.c (ppc_opts): Remove PPC_OPCODE_VSX3.
	* ppc-opc.c (PPCVSX2): Define as PPC_OPCODE_POWER8.
	(PPCVSX3): Define as PPC_OPCODE_POWER9.
2017-04-11 07:36:43 +09:30
Alan Modra
9a85b496ac Bye bye PPC_OPCODE_ALTIVEC2
This bit is worse than useless.  Using it prevents the assembler and
disassembler distinguishing between opcodes added for power8 and those
added for power9.

include/
	* opcode/ppc.h (PPC_OPCODE_ALTIVEC2): Delete.
opcodes/
	* ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2.
	* ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
	(PPCVEC3): Define as PPC_OPCODE_POWER9.
2017-04-11 07:33:50 +09:30
Alan Modra
62adc51030 Tidy ppc476 opcodes
PPC_OPCODE_440 being set for ppc476 meant that many opcodes needed to
be deprecated for ppc476.  There are far fewer to add specially for
ppc476 if PPC_OPCODE_440 is not set for ppc476.

	* ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
	* ppc-opc.c (MULHW): Add PPC_OPCODE_476.
	(powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
	removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
2017-04-10 15:35:11 +09:30
Pip Cet
aa80870703 WebAssembly disassembler support
* wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
	appropriate floating-point precision directly.
2017-04-10 13:51:45 +09:30
Alan Modra
ac8f0f721b Remove E6500 insns from PPC_OPCODE_ALTIVEC2
This isn't losing anything from the testsuite.  All of these insns
appear in testsuite/gas/ppc/e6500.s

opcodes/
	* ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
	lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
	lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
	lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
	vector instructions with E6500 not PPCVEC2.
gas/
	* testsuite/gas/ppc/altivec2.s: Delete E6500 vector insns.
	* testsuite/gas/ppc/altivec2.d: Adjust to suit.
2017-04-07 18:24:38 +09:30
Pip Cet
62ecb94c4a Add support for disassembling WebAssembly opcodes.
include	* dis-asm.h: Add prototypes for wasm32 disassembler.

opcodes	* Makefile.am: Add wasm32-dis.c.
	* configure.ac: Add wasm32-dis.c to wasm32 target.
	* disassemble.c: Add wasm32 disassembler code.
	* wasm32-dis.c: New file.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* po/POTFILES.in: Regenerate.
	* po/opcodes.pot: Regenerate.

gas	* testsuite/gas/wasm32/allinsn.d: Adjust test for disassembler
	changes.
	* testsuite/gas/wasm32/disass.d: New test.
	* testsuite/gas/wasm32/disass.s: New test.
	* testsuite/gas/wasm32/disass-2.d: New test.
	* testsuite/gas/wasm32/disass-2.s: New test.
	* testsuite/gas/wasm32/reloc.d: Adjust test for changed reloc
	names.
	* testsuite/gas/wasm32/reloc.s: Update test for changed assembler
	syntax.
	* testsuite/gas/wasm32/wasm32.exp: Run new tests.  Expect allinsn
	test to succeed.
2017-04-06 17:20:02 +01:00
Pedro Alves
f995bbe8e6 -Wwrite-strings: Constify struct disassemble_info's disassembler_options field
The memory disassemble_info::disassembler_options points to is always
owned by the client.  I.e., that field is an non-owning, observing
pointer.  Thus const makes sense.

Are the include/ and opcodes/ bits OK?

Tested on x86_64 Fedora 23, built with --enable-targets=all.

include/ChangeLog:
2017-04-05  Pedro Alves  <palves@redhat.com>

	* dis-asm.h (disassemble_info) <disassembler_options>: Now a
	"const char *".
	(next_disassembler_option): Constify.

opcodes/ChangeLog:
2017-04-05  Pedro Alves  <palves@redhat.com>

	* arc-dis.c (parse_option, parse_disassembler_options): Constify.
	* arm-dis.c (parse_arm_disassembler_options): Constify.
	* ppc-dis.c (powerpc_init_dialect): Constify local.
	* vax-dis.c (parse_disassembler_options): Constify.

gdb/ChangeLog:
2017-04-05  Pedro Alves  <palves@redhat.com>

	* arm-tdep.c (show_disassembly_style_sfunc): Constify local.
	* disasm.c (set_disassembler_options): Constify local.
	* i386-tdep.c (i386_print_insn): Remove cast and FIXME comment.
2017-04-05 19:21:33 +01:00
Palmer Dabbelt
b52920324f RISC-V: Resurrect GP-relative disassembly hints
We missed a "_gp" when changing the GP symbol.  To make sure that
doesn't happen again, we now use the same definition everywhere (thanks,
Nick).

include/ChangeLog:

2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>

        * elf/riscv.h (RISCV_GP_SYMBOL): New define.

bfd/ChangeLog:

2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>

        * elfnn-riscv.c (GP_NAME): Delete.
        (riscv_global_pointer_value): Change GP_NAME to RISCV_GP_SYMBOL.
        (_bfd_riscv_relax_lui): Likewise.

opcodes/ChangeLog:

2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>

        * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
        RISCV_GP_SYMBOL.
2017-04-04 08:29:16 -07:00
Pip Cet
f96bd6c2d7 Add support for the WebAssembly file format and the wasm32 ELF conversion to gas and the binutils.
binutils * readelf.c: Add support for wasm32 ELF format WebAssembly files.
	(guess_is_rela): Likewise.
	(dump_relocations): Likewise.
	(is_32bit_abs_reloc): Likewise.
	(is_none_reloc_): Likewise.
	* NEWS: Mention the new support.
	* testsuite/lib/binutils-common.exp (is_elf_format): Mark wasm32
	as ELF target.
	(supports_gnu_unique): Mark wasm32 as supporting STB_GNU_UNIQUE.
	* testsuite/binutils-all/nm.exp: Mark wasm32 as requiring .size annotations.
	* testsuite/binutils-all/wasm32: New directory.
	* testsuite/binutils-all/wasm32/create-wasm.d: New file.
	* testsuite/binutils-all/wasm32/create-wasm.s: Likewise.
	* testsuite/binutils-all/wasm32/custom-section.d: Likewise.
	* testsuite/binutils-all/wasm32/custom-section.s: Likewise.
	* testsuite/binutils-all/wasm32/invalid-wasm-1.d: Likewise.
	* testsuite/binutils-all/wasm32/invalid-wasm-1.s: Likewise.
	* testsuite/binutils-all/wasm32/long-sections.d: Likewise.
	* testsuite/binutils-all/wasm32/long-sections.s: Likewise.
	* testsuite/binutils-all/wasm32/parse-wasm.d: Likewise.
	* testsuite/binutils-all/wasm32/parse-wasm.s: Likewise.
	* testsuite/binutils-all/wasm32/parse-wasm-2.d: Likewise.
	* testsuite/binutils-all/wasm32/parse-wasm-2.s: Likewise.
	* testsuite/binutils-all/wasm32/prepared-section.d: Likewise.
	* testsuite/binutils-all/wasm32/prepared-section.s: Likewise.
	* testsuite/binutils-all/wasm32/wasm32.exp: New file, run tests.

gas	* config/tc-wasm32.h: New file: Add WebAssembly assembler target.
	* config/tc-wasm32.c: New file: Add WebAssembly assembler target.
	* Makefile.am: Add WebAssembly assembler target.
	* configure.tgt: Add WebAssembly assembler target.
	* doc/c-wasm32.texi: New file: Start documenting WebAssembly
	assembler.
	* doc/all.texi: Define WASM32.
	* doc/as.texinfo: Add WebAssembly entries.
	* NEWS: Mention the new support.
	* Makefile.in: Regenerate.
	* po/gas.pot: Regenerate.
	* po/POTFILES.in: Regenerate.
	* testsuite/gas/wasm32: New directory.
	* testsuite/gas/wasm32/allinsn.d: New file.
	* testsuite/gas/wasm32/allinsn.s: New file.
	* testsuite/gas/wasm32/illegal.l: New file.
	* testsuite/gas/wasm32/illegal.s: New file.
	* testsuite/gas/wasm32/illegal-2.l: New file.
	* testsuite/gas/wasm32/illegal-2.s: New file.
	* testsuite/gas/wasm32/illegal-3.l: New file.
	* testsuite/gas/wasm32/illegal-3.s: New file.
	* testsuite/gas/wasm32/illegal-4.l: New file.
	* testsuite/gas/wasm32/illegal-4.s: New file.
	* testsuite/gas/wasm32/illegal-5.l: New file.
	* testsuite/gas/wasm32/illegal-5.s: New file.
	* testsuite/gas/wasm32/illegal-6.l: New file.
	* testsuite/gas/wasm32/illegal-6.s: New file.
	* testsuite/gas/wasm32/illegal-7.l: New file.
	* testsuite/gas/wasm32/illegal-7.s: New file.
	* testsuite/gas/wasm32/illegal-8.l: New file.
	* testsuite/gas/wasm32/illegal-8.s: New file.
	* testsuite/gas/wasm32/illegal-9.l: New file.
	* testsuite/gas/wasm32/illegal-9.s: New file.
	* testsuite/gas/wasm32/illegal-10.l: New file.
	* testsuite/gas/wasm32/illegal-10.s: New file.
	* testsuite/gas/wasm32/illegal-11.l: New file.
	* testsuite/gas/wasm32/illegal-11.s: New file.
	* testsuite/gas/wasm32/illegal-12.l: New file.
	* testsuite/gas/wasm32/illegal-12.s: New file.
	* testsuite/gas/wasm32/illegal-13.l: New file.
	* testsuite/gas/wasm32/illegal-13.s: New file.
	* testsuite/gas/wasm32/illegal-14.l: New file.
	* testsuite/gas/wasm32/illegal-14.s: New file.
	* testsuite/gas/wasm32/illegal-15.l: New file.
	* testsuite/gas/wasm32/illegal-15.s: New file.
	* testsuite/gas/wasm32/illegal-16.l: New file.
	* testsuite/gas/wasm32/illegal-16.s: New file.
	* testsuite/gas/wasm32/illegal-17.l: New file.
	* testsuite/gas/wasm32/illegal-17.s: New file.
	* testsuite/gas/wasm32/illegal-18.l: New file.
	* testsuite/gas/wasm32/illegal-18.s: New file.
	* testsuite/gas/wasm32/illegal-19.l: New file.
	* testsuite/gas/wasm32/illegal-19.s: New file.
	* testsuite/gas/wasm32/illegal-20.l: New file.
	* testsuite/gas/wasm32/illegal-20.s: New file.
	* testsuite/gas/wasm32/illegal-21.l: New file.
	* testsuite/gas/wasm32/illegal-21.s: New file.
	* testsuite/gas/wasm32/illegal-22.l: New file.
	* testsuite/gas/wasm32/illegal-22.s: New file.
	* testsuite/gas/wasm32/illegal-24.l: New file.
	* testsuite/gas/wasm32/illegal-24.s: New file.
	* testsuite/gas/wasm32/illegal-25.l: New file.
	* testsuite/gas/wasm32/illegal-25.s: New file.
	* testsuite/gas/wasm32/reloc.d: New file.
	* testsuite/gas/wasm32/reloc.s: New file.
	* testsuite/gas/wasm32/wasm32.exp: New tests for WebAssembly
	architecture.

opcodes * configure.ac: Add (empty) bfd_wasm32_arch target.
	* configure: Regenerate
	* po/opcodes.pot: Regenerate.

include	* opcode/wasm.h: New file to support wasm32 architecture.
	* elf/wasm32.h: Add R_WASM32_32 relocation.

bfd	* elf32-wasm32.c: Add relocation code, two relocs.
	* reloc.c: Add wasm32 relocations.
	* libbfd.h: Regenerate.
	* bfd-in2.h: Regenerate.
	* bfd/po/bfd.pot: Regenerate.
2017-03-30 10:57:21 +01:00
Jose E. Marchesi
f7c514a378 opcodes: sparc: support missing SPARC ASIs from UA2005, UA2007, OSA2011, & OSA2015 2017-03-29 21:20:23 +02:00
Alan Modra
52be03fd13 PowerPC -Mraw disassembly
This adds -Mraw for PowerPC objdump, a disassembler option to display
the underlying machine instruction rather than aliases.  For example,
"rlwinm" always rather than "rotlwi" when the instruction is
performing a simple rotate.

binutils/
	* doc/binutils.texi (objdump): Document PowerPC -M options.
gas/
	* config/tc-ppc.c (md_parse_option): Reject -mraw.
include/
	* opcode/ppc.h (PPC_OPCODE_RAW): Define.
	(PPC_OPCODE_*): Make them all unsigned long long constants.
opcodes/
	* ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
	"raw" option.
	(lookup_powerpc): Don't special case -1 dialect.  Handle
	PPC_OPCODE_RAW.
	(print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
	lookup_powerpc call, pass it on second.
2017-03-29 22:55:18 +10:30
Alan Modra
9b75393746 PR21303, objdump doesn't show e200z4 insns
PR 21303
opcodes/
	* ppc-dis.c (struct ppc_mopt): Comment.
	(ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
gas/
	* testsuite/gas/ppc/pr21303.d,
	* testsuite/gas/ppc/pr21303.s: New test
	* testsuite/gas/ppc/ppc.exp: Run it.
2017-03-27 21:49:32 +10:30
Rinat Zelig
c0c31e91ad Implement ARC NPS-400 Ultra Ip and Miscellaneous instructions.
opcodes	* arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
	* arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR, F_NPS_M, F_NPS_CORE, F_NPS_ALL.
	(insert_nps_misc_imm_offset): New function.
	(extract_nps_misc imm_offset): New function.
	(arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
	(arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.

include * opcode/arc.h (insn_class_t): Add ULTRAIP and MISC class.

gas     * testsuite/gas/arc/nps400-12.s: New file.
        * testsuite/gas/arc/nps400-12.d: New file.
2017-03-27 11:14:30 +01:00
Andreas Krebbel
2253c8f089 S/390: Remove vx2 facility flag
This patch removes the vx2 facility flag.  It will not be used by GCC
and was a misnomer anyway.

Committed to mainline and 2.28 branch.

include/ChangeLog:

2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* opcode/s390.h (S390_INSTR_FLAG_VX2): Remove.
	(S390_INSTR_FLAG_FACILITY_MASK): Adjust value.

gas/ChangeLog:

2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* config/tc-s390.c (s390_parse_cpu): Remove S390_INSTR_FLAG_VX2
	from cpu_table.  Remove vx2, and novx2 from cpu_flags.

opcodes/ChangeLog:

2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-mkopc.c (main): Remove vx2 check.
	* s390-opc.txt: Remove vx2 instruction flags.
2017-03-21 14:21:02 +01:00
Rinat Zelig
645d3342ba arc/nps400: Add cp16/cp32 instructions to opcodes library
Instructions for loading or storing 16/32B data from one address type to
another.

gas/ChangeLog

	* testsuite/gas/arc/nps400-11.s: New file.
	* testsuite/gas/arc/nps400-11.d: New file.

include/ChangeLog

	* opcode/arc.h (insn_class_t): Add DMA class.

opcodes/ChangeLog

	* arc-nps400-tbl.h: Add cp32/cp16 instructions format.
	* arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
	(insert_nps_imm_offset): New function.
	(extract_nps_imm_offset): New function.
	(insert_nps_imm_entry): New function.
	(extract_nps_imm_entry): New function.
2017-03-21 11:51:49 +00:00
Alan Modra
4b94dd2de1 E6500 spr mnemonics
PR 21248
	* ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
	mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
	those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
2017-03-17 19:09:15 +10:30
Kito Cheng
b416fe873e RISC-V: Fix assembler for c.li, c.andi and c.addiw
- They can accept 0 in imm field

 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>

       * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
       <c.andi>: Likewise.
       <c.addiw> Likewise.
2017-03-15 07:47:52 -07:00
Kito Cheng
03b039a518 RISC-V: Fix assembler for c.addi, rd can be x0
opcodes/ChangeLog:

2017-03-14  Kito Cheng  <kito.cheng@gmail.com>

	* riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
2017-03-15 07:47:52 -07:00
Andrew Waterman
2c232b8361 RISC-V: Fix [dis]assembly of srai/srli
These were simple copy/paste errors from the compressed left shift
pattern, which can't have a 0-register.
2017-03-14 09:23:18 -07:00
H.J. Lu
86fa6981e7 X86: Add pseudo prefixes to control encoding
Many x86 instructions have more than one encodings.  Assembler picks
the default one, usually the shortest one.  Although the ".s", ".d8"
and ".d32" suffixes can be used to swap register operands or specify
displacement size, they aren't very flexible.  This patch adds pseudo
prefixes, {xxx}, to control instruction encoding.  The available
pseudo prefixes are {disp8}, {disp32}, {load}, {store}, {vex2}, {vex3}
and {evex}.  Pseudo prefixes are preferred over the ".s", ".d8" and
".d32" suffixes, which are deprecated.

gas/

	* config/tc-i386.c (_i386_insn): Add dir_encoding and
	vec_encoding.  Remove swap_operand and need_vrex.
	(extra_symbol_chars): Add '}'.
	(md_begin): Mark '}' with LEX_BEGIN_NAME.  Allow '}' in
	mnemonic.
	(build_vex_prefix): Don't use 2-byte VEX encoding with
	{vex3}.  Check dir_encoding and load.
	(parse_insn): Check pseudo prefixes.  Set dir_encoding.
	(VEX_check_operands): Likewise.
	(match_template): Check dir_encoding and load.
	(parse_real_register): Set vec_encoding instead of need_vrex.
	(parse_register): Likewise.
	* doc/c-i386.texi: Document {disp8}, {disp32}, {load}, {store},
	{vex2}, {vex3} and {evex}.  Remove ".s", ".d8" and ".d32"
	* testsuite/gas/i386/i386.exp: Run pseudos and x86-64-pseudos.
	* testsuite/gas/i386/pseudos.d: New file.
	* testsuite/gas/i386/pseudos.s: Likewise.
	* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
	* testsuite/gas/i386/x86-64-pseudos.s: Likewise.

opcodes/

	* i386-gen.c (opcode_modifiers): Replace S with Load.
	* i386-opc.h (S): Removed.
	(Load): New.
	(i386_opcode_modifier): Replace s with load.
	* i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
	and {evex}.  Replace S with Load.
	* i386-tbl.h: Regenerated.
2017-03-09 09:59:00 -08:00
H.J. Lu
c1fe188b15 Use CpuCET on rdsspq
* i386-opc.tbl: Use CpuCET on rdsspq.
	* i386-tbl.h: Regenerated.
2017-03-09 07:43:48 -08:00
Peter Bergner
4b8b687e88 Update -maltivec and -mvsx options to only enable their oldest instructions.
Currently, the -maltivec and -mvsx GAS options enable *all* of the altivec
and vsx instructions respecitively that have ever been added.  This is in
constract to GCC's -maltivec and -mvsx options, which only enable the oldest
(ie, first) set of altivec and vsx instructions.  This patch changes GAS to
mimic GCC's behaviour with respect to -maltivec and -mvsx and it solves a
problem with trying to assemble the lxvx instruction which is different
between POWER8 and POWER9.

opcodes/
	* ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
	<vsx>: Do not use PPC_OPCODE_VSX3;

gas/
	* testsuite/gas/ppc/altivec2.d (as): Use the -mpower8 option.
	(objdump): Use the -Mpower8 option.
2017-03-08 20:49:03 -06:00
Peter Bergner
1437d0631b Add support for the new 'lnia' extended mnemonic.
opcodes/
	* ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.

gas/
	* testsuite/gas/ppc/power9.d <lnia> New test.
	* testsuite/gas/ppc/power9.s: Likewise.
2017-03-08 14:02:18 -06:00
H.J. Lu
603555e563 Add support for Intel CET instructions
Support Intel Control-flow Enforcement Technology (CET) instructions:

https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf

gas/

	* config/tc-i386.c (cpu_arch): Add .cet.
	* doc/c-i386.texi: Document cet.
	* testsuite/gas/i386/cet-intel.d: New file.
	* testsuite/gas/i386/cet.d: Likewise.
	* testsuite/gas/i386/cet.s: Likewise.
	* testsuite/gas/i386/x86-64-cet-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-cet.d: Likewise.
	* testsuite/gas/i386/x86-64-cet.s: Likewise.
	* testsuite/gas/i386/i386.exp: Run Intel CET tests.

opcodes/

	* i386-dis.c (REG_0F1E_MOD_3): New enum.
	(MOD_0F1E_PREFIX_1): Likewise.
	(MOD_0F38F5_PREFIX_2): Likewise.
	(MOD_0F38F6_PREFIX_0): Likewise.
	(RM_0F1E_MOD_3_REG_7): Likewise.
	(PREFIX_MOD_0_0F01_REG_5): Likewise.
	(PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
	(PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
	(PREFIX_0F1E): Likewise.
	(PREFIX_MOD_0_0FAE_REG_5): Likewise.
	(PREFIX_0F38F5): Likewise.
	(dis386_twobyte): Use PREFIX_0F1E.
	(reg_table): Add REG_0F1E_MOD_3.
	(prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
	PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
	PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
	PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
	(three_byte_table): Use PREFIX_0F38F5.
	(mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
	Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
	(rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
	RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
	PREFIX_MOD_3_0F01_REG_5_RM_2.
	* i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
	(cpu_flags): Add CpuCET.
	* i386-opc.h (CpuCET): New enum.
	(CpuUnused): Commented out.
	(i386_cpu_flags): Add cpucet.
	* i386-opc.tbl: Add Intel CET instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
2017-03-06 15:26:37 -08:00
Alan Modra
73f07bffaf Don't decode powerpc insns with invalid fields
Certain insns have restrictions on fields.  For example, the insn
mentioned in the PR, lqarx, must specify an even general purpose
register as its destination and that register cannot appear in
either of the base or index reg fields.  This holds even when the RA0
field is 0 (meaning a zero rather than r0).

	PR 21124
	* ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
	(extract_raq, extract_ras, extract_rbx): New functions.
	(powerpc_operands): Use opposite corresponding insert function.
	(Q_MASK): Define.
	(powerpc_opcodes): Apply Q_MASK to all quad insns with even
	register restriction.
2017-03-06 21:54:23 +10:30
Peter Bergner
65b48a8140 GDB: Add support for the new set/show disassembler-options commands.
This commit adds support to GDB so that it can modify the disassembler-options
value that is passed to the disassembler, similar to objdump's -M option.
Currently, the only supported targets are ARM, PowerPC and S/390, but
adding support for a new target(s) is not difficult.

include/
	* dis-asm.h (disasm_options_t): New typedef.
	(parse_arm_disassembler_option): Remove prototype.
	(set_arm_regname_option): Likewise.
	(get_arm_regnames): Likewise.
	(get_arm_regname_num_options): Likewise.
	(disassemble_init_s390): New prototype.
	(disassembler_options_powerpc): Likewise.
	(disassembler_options_arm): Likewise.
	(disassembler_options_s390): Likewise.
	(remove_whitespace_and_extra_commas): Likewise.
	(disassembler_options_cmp): Likewise.
	(next_disassembler_option): New inline function.
	(FOR_EACH_DISASSEMBLER_OPTION): New macro.

opcodes/
	* disassemble.c Include "safe-ctype.h".
	(disassemble_init_for_target): Handle s390 init.
	(remove_whitespace_and_extra_commas): New function.
	(disassembler_options_cmp): Likewise.
	* arm-dis.c: Include "libiberty.h".
	(NUM_ELEM): Delete.
	(regnames): Use long disassembler style names.
	Add force-thumb and no-force-thumb options.
	(NUM_ARM_REGNAMES): Rename from this...
	(NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
	(get_arm_regname_num_options): Delete.
	(set_arm_regname_option): Likewise.
	(get_arm_regnames): Likewise.
	(parse_disassembler_options): Likewise.
	(parse_arm_disassembler_option): Rename from this...
	(parse_arm_disassembler_options): ...to this.  Make static.
	Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
	(print_insn): Use parse_arm_disassembler_options.
	(disassembler_options_arm): New function.
	(print_arm_disassembler_options): Handle updated regnames.
	* ppc-dis.c: Include "libiberty.h".
	(ppc_opts): Add "32" and "64" entries.
	(ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
	(powerpc_init_dialect): Add break to switch statement.
	Use new FOR_EACH_DISASSEMBLER_OPTION macro.
	(disassembler_options_powerpc): New function.
	(print_ppc_disassembler_options): Use ARRAY_SIZE.
	Remove printing of "32" and "64".
	* s390-dis.c: Include "libiberty.h".
	(init_flag): Remove unneeded variable.
	(struct s390_options_t): New structure type.
	(options): New structure.
	(init_disasm): Rename from this...
	(disassemble_init_s390): ...to this.  Add initializations for
	current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
	(print_insn_s390): Delete call to init_disasm.
	(disassembler_options_s390): New function.
	(print_s390_disassembler_options): Print using information from
	struct 'options'.
	* po/opcodes.pot: Regenerate.

binutils/
	* objdump.c (main): Use remove_whitespace_and_extra_commas.

gdb/
	* NEWS: Mention new set/show disassembler-options commands.
	* doc/gdb.texinfo: Document new set/show disassembler-options commands.
	* disasm.c: Include "arch-utils.h", "gdbcmd.h" and "safe-ctype.h".
	(prospective_options): New static variable.
	(gdb_disassembler::gdb_disassembler): Initialize
	m_di.disassembler_options.
	(gdb_buffered_insn_length_init_dis): Initilize di->disassembler_options.
	(get_disassembler_options): New function.
	(set_disassembler_options): Likewise.
	(set_disassembler_options_sfunc): Likewise.
	(show_disassembler_options_sfunc): Likewise.
	(disassembler_options_completer): Likewise.
	(_initialize_disasm): Likewise.
	* disasm.h (get_disassembler_options): New prototype.
	(set_disassembler_options): Likewise.
	* gdbarch.sh (gdbarch_disassembler_options): New variable.
	(gdbarch_verify_disassembler_options): Likewise.
	* gdbarch.c: Regenerate.
	* gdbarch.h: Likewise.
	* arm-tdep.c (num_disassembly_options): Delete.
	(set_disassembly_style): Likewise.
	(arm_disassembler_options): New static variable.
	(set_disassembly_style_sfunc): Convert short style name into long
	option name.  Call set_disassembler_options.
	(show_disassembly_style_sfunc): New function.
	(arm_gdbarch_init): Call set_gdbarch_disassembler_options and
	set_gdbarch_verify_disassembler_options.
	(_initialize_arm_tdep): Delete regnames variable and update callers.
	(arm_disassembler_options): Initialize.
	(disasm_options): New variable.
	(num_disassembly_options): Rename from this...
	(num_disassembly_styles): ...to this.  Compute by scanning through
	disasm_options.
	(valid_disassembly_styles): Initialize using disasm_options.
	Remove calls to parse_arm_disassembler_option, get_arm_regnames and
	set_arm_regname_option.
	Pass show_disassembly_style_sfunc to the "disassembler" setshow command.
	* rs6000-tdep.c (powerpc_disassembler_options): New static variable.
	(rs6000_gdbarch_init): Call set_gdbarch_disassembler_options and
	set_gdbarch_verify_disassembler_options.
	* s390-tdep.c (s390_disassembler_options): New static variable.
	(s390_gdbarch_init):all set_gdbarch_disassembler_options and
	set_gdbarch_verify_disassembler_options.

gdb/testsuite/
	* gdb.arch/powerpc-power.exp: Delete test.
	* gdb.arch/powerpc-power.s: Likewise.
	* gdb.disasm/disassembler-options.exp: New test.
	* gdb.arch/powerpc-altivec.exp: Likewise.
	* gdb.arch/powerpc-altivec.s: Likewise.
	* gdb.arch/powerpc-altivec2.exp: Likewise.
	* gdb.arch/powerpc-altivec2.s: Likewise.
	* gdb.arch/powerpc-altivec3.exp: Likewise.
	* gdb.arch/powerpc-altivec3.s: Likewise.
	* gdb.arch/powerpc-power7.exp: Likewise.
	* gdb.arch/powerpc-power7.s: Likewise.
	* gdb.arch/powerpc-power8.exp: Likewise.
	* gdb.arch/powerpc-power8.s: Likewise.
	* gdb.arch/powerpc-power9.exp: Likewise.
	* gdb.arch/powerpc-power9.s: Likewise.
	* gdb.arch/powerpc-vsx.exp: Likewise.
	* gdb.arch/powerpc-vsx.s: Likewise.
	* gdb.arch/powerpc-vsx2.exp: Likewise.
	* gdb.arch/powerpc-vsx2.s: Likewise.
	* gdb.arch/powerpc-vsx3.exp: Likewise.
	* gdb.arch/powerpc-vsx3.s: Likewise.
	* gdb.arch/arm-disassembler-options.exp: Likewise.
	* gdb.arch/powerpc-disassembler-options.exp: Likewise.
	* gdb.arch/s390-disassembler-options.exp: Likewise.
2017-02-28 12:32:07 -06:00
Jan Beulich
15c7c1d8a5 x86: fix handling of 64-bit operand size VPCMPESTR{I,M}
Just like REX.W affects operand size of the implicit rAX/rDX inputs to
PCMPESTR{I,M}, VEX.W does for VPCMPESTR{I,M}. Allow Q or L suffixes on
the instructions.

Similarly the disassembler needs to be adjusted to no longer require
VEX.W to be zero for the instructions to be valid, and to emit proper
suffixes.

Note, however, that this doesn't address the problem of there being no
way to control (at least) {,E}VEX.W for 32- or 16-bit code. Nor does it
address the problem of the many WIG instructions not getting properly
disassembled when VEX.W=1.
2017-02-28 10:53:35 +01:00
Richard Sandiford
582e12bf76 [AArch64] Additional SVE instructions
This patch supports some additions to the SVE architecture prior to
its public release.

include/
	* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16)
	(AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2)
	(AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX)
	(AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds.

opcodes/
	* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
	(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
	(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
	(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
	(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
	(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
	(OP_SVE_V_HSD): New macros.
	(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
	(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
	(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
	(aarch64_opcode_table): Add new SVE instructions.
	(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
	for rotation operands.  Add new SVE operands.
	* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
	(ins_sve_quad_index): Likewise.
	(ins_imm_rotate): Split into...
	(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
	* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
	(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
	functions.
	(aarch64_ins_sve_addr_ri_s4): New function.
	(aarch64_ins_sve_quad_index): Likewise.
	(do_misc_encoding): Handle "MOV Zn.Q, Qm".
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
	(ext_sve_quad_index): Likewise.
	(ext_imm_rotate): Split into...
	(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
	* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
	(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
	functions.
	(aarch64_ext_sve_addr_ri_s4): New function.
	(aarch64_ext_sve_quad_index): Likewise.
	(aarch64_ext_sve_index): Allow quad indices.
	(do_misc_decoding): Likewise.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
	aarch64_field_kinds.
	(OPD_F_OD_MASK): Widen by one bit.
	(OPD_F_NO_ZR): Bump accordingly.
	(get_operand_field_width): New function.
	* aarch64-opc.c (fields): Add new SVE fields.
	(operand_general_constraint_met_p): Handle new SVE operands.
	(aarch64_print_operand): Likewise.
	* aarch64-opc-2.c: Regenerate.

gas/
	* doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum.
	* config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q
	to be used with SVE registers.
	(parse_operands): Handle new SVE operands.
	(aarch64_features): Make "sve" require F16 rather than FP.  Also
	require COMPNUM.
	* testsuite/gas/aarch64/sve.s: Add tests for new instructions.
	Include compnum tests.
	* testsuite/gas/aarch64/sve.d: Update accordingly.
	* testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions.
	* testsuite/gas/aarch64/sve-invalid.l: Update accordingly.  Also
	update expected output for new FMOV and MOV alternatives.
2017-02-24 18:29:00 +00:00
Richard Sandiford
f482d30447 [AArch64] Add a "compnum" feature
This patch adds a named "compnum" feature for the ARMv8.3-A FCADD
and FCMLA extensions.

include/
	* opcode/aarch64.h (AARCH64_FEATURE_COMPNUM): New macro.
	(AARCH64_ARCH_V8_3): Include AARCH64_FEATURE_COMPNUM.

opcodes/
	* aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
	(aarch64_feature_compnum): ...this.
	(SIMD_V8_3): Replace with...
	(COMPNUM): ...this.
	(CNUM_INSN): New macro.
	(aarch64_opcode_table): Use it for the complex number instructions.

gas/
	* doc/c-aarch64.texi: Add a "compnum" entry.
	* config/tc-aarch64.c (aarch64_features): Likewise,
	* testsuite/gas/aarch64/advsimd-compnum.s: New test.
	* testsuite/gas/aarch64/advsimd-compnum.d: Likewise.
2017-02-24 18:27:26 +00:00
Jan Beulich
7db2c58848 x86: also correctly support TEST opcode aliases
Opcodes F6/1 and F7/1 are aliases of F6/0 and F7/0 in all modes. This
complements commit 8b89fe14b5 ("X86: Decode opcode 0x82 as opcode 0x80
in 32-bit mode"), just that here 64-bit mode is also covered.
2017-02-24 10:04:26 +01:00
Andreas Krebbel
64025b4ec9 S/390: Add support for new cpu architecture - arch12.
This adds support of new instructions to the S/390 specific parts.

The important feature of the new instruction set is the support of
single and extended precision floating point vector operations.

Note: arch12 is NOT the official name of the new CPU.  It just
continues the series of archXX options supported as alternate names.
The archXX terminology refers to the edition number of the Principle
of Operations manual.  The official CPU name will be added later while
keeping support of the arch12 for backwards compatibility.

No testsuite regressions.

Committed to mainline.

Bye,

-Andreas-

opcodes/ChangeLog:

2017-02-23  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-mkopc.c (main): Accept arch12 as cpu string and vx2 as
	facility.
	* s390-opc.c: Add new operand description macros, new instruction
	types, instruction masks, and new .insn instruction types.
	* s390-opc.txt: Add new arch12 instructions.

include/ChangeLog:

2017-02-23  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* opcode/s390.h (enum s390_opcode_cpu_val): New value
	S390_OPCODE_ARCH12.
	(S390_INSTR_FLAG_VX2): New macro definition.

gas/ChangeLog:

2017-02-23  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* config/tc-s390.c (s390_parse_cpu): New entry for arch12.
	* doc/as.texinfo: Document arch12 as cpu type.
	* doc/c-s390.texi: Likewise.
	* testsuite/gas/s390/s390.exp: Run arch12 specific tests.
	* testsuite/gas/s390/zarch-arch12.d: New test.
	* testsuite/gas/s390/zarch-arch12.s: New test.
	* testsuite/gas/s390/zarch-z13.d: Rename some mnemonics in the
	output patterns.
2017-02-23 18:27:38 +01:00