Commit Graph

781 Commits

Author SHA1 Message Date
Andreas Krebbel
2253c8f089 S/390: Remove vx2 facility flag
This patch removes the vx2 facility flag.  It will not be used by GCC
and was a misnomer anyway.

Committed to mainline and 2.28 branch.

include/ChangeLog:

2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* opcode/s390.h (S390_INSTR_FLAG_VX2): Remove.
	(S390_INSTR_FLAG_FACILITY_MASK): Adjust value.

gas/ChangeLog:

2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* config/tc-s390.c (s390_parse_cpu): Remove S390_INSTR_FLAG_VX2
	from cpu_table.  Remove vx2, and novx2 from cpu_flags.

opcodes/ChangeLog:

2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-mkopc.c (main): Remove vx2 check.
	* s390-opc.txt: Remove vx2 instruction flags.
2017-03-21 14:21:02 +01:00
Rinat Zelig
645d3342ba arc/nps400: Add cp16/cp32 instructions to opcodes library
Instructions for loading or storing 16/32B data from one address type to
another.

gas/ChangeLog

	* testsuite/gas/arc/nps400-11.s: New file.
	* testsuite/gas/arc/nps400-11.d: New file.

include/ChangeLog

	* opcode/arc.h (insn_class_t): Add DMA class.

opcodes/ChangeLog

	* arc-nps400-tbl.h: Add cp32/cp16 instructions format.
	* arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
	(insert_nps_imm_offset): New function.
	(extract_nps_imm_offset): New function.
	(insert_nps_imm_entry): New function.
	(extract_nps_imm_entry): New function.
2017-03-21 11:51:49 +00:00
Richard Sandiford
582e12bf76 [AArch64] Additional SVE instructions
This patch supports some additions to the SVE architecture prior to
its public release.

include/
	* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16)
	(AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2)
	(AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX)
	(AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds.

opcodes/
	* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
	(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
	(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
	(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
	(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
	(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
	(OP_SVE_V_HSD): New macros.
	(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
	(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
	(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
	(aarch64_opcode_table): Add new SVE instructions.
	(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
	for rotation operands.  Add new SVE operands.
	* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
	(ins_sve_quad_index): Likewise.
	(ins_imm_rotate): Split into...
	(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
	* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
	(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
	functions.
	(aarch64_ins_sve_addr_ri_s4): New function.
	(aarch64_ins_sve_quad_index): Likewise.
	(do_misc_encoding): Handle "MOV Zn.Q, Qm".
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
	(ext_sve_quad_index): Likewise.
	(ext_imm_rotate): Split into...
	(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
	* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
	(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
	functions.
	(aarch64_ext_sve_addr_ri_s4): New function.
	(aarch64_ext_sve_quad_index): Likewise.
	(aarch64_ext_sve_index): Allow quad indices.
	(do_misc_decoding): Likewise.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
	aarch64_field_kinds.
	(OPD_F_OD_MASK): Widen by one bit.
	(OPD_F_NO_ZR): Bump accordingly.
	(get_operand_field_width): New function.
	* aarch64-opc.c (fields): Add new SVE fields.
	(operand_general_constraint_met_p): Handle new SVE operands.
	(aarch64_print_operand): Likewise.
	* aarch64-opc-2.c: Regenerate.

gas/
	* doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum.
	* config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q
	to be used with SVE registers.
	(parse_operands): Handle new SVE operands.
	(aarch64_features): Make "sve" require F16 rather than FP.  Also
	require COMPNUM.
	* testsuite/gas/aarch64/sve.s: Add tests for new instructions.
	Include compnum tests.
	* testsuite/gas/aarch64/sve.d: Update accordingly.
	* testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions.
	* testsuite/gas/aarch64/sve-invalid.l: Update accordingly.  Also
	update expected output for new FMOV and MOV alternatives.
2017-02-24 18:29:00 +00:00
Richard Sandiford
f482d30447 [AArch64] Add a "compnum" feature
This patch adds a named "compnum" feature for the ARMv8.3-A FCADD
and FCMLA extensions.

include/
	* opcode/aarch64.h (AARCH64_FEATURE_COMPNUM): New macro.
	(AARCH64_ARCH_V8_3): Include AARCH64_FEATURE_COMPNUM.

opcodes/
	* aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
	(aarch64_feature_compnum): ...this.
	(SIMD_V8_3): Replace with...
	(COMPNUM): ...this.
	(CNUM_INSN): New macro.
	(aarch64_opcode_table): Use it for the complex number instructions.

gas/
	* doc/c-aarch64.texi: Add a "compnum" entry.
	* config/tc-aarch64.c (aarch64_features): Likewise,
	* testsuite/gas/aarch64/advsimd-compnum.s: New test.
	* testsuite/gas/aarch64/advsimd-compnum.d: Likewise.
2017-02-24 18:27:26 +00:00
Andrew Waterman
742d14b39b Add new counter-enable CSRs
include/ChangeLog:

2017-02-22  Andrew Waterman  <andrew@sifive.com>

       * opcode/riscv-opc.h (CSR_SCOUNTEREN): New define.
       (CSR_MCOUNTEREN): Likewise.
       (scounteren): Declare register.
       (mcounteren): Likewise.
2017-02-24 09:24:58 -08:00
Andreas Krebbel
64025b4ec9 S/390: Add support for new cpu architecture - arch12.
This adds support of new instructions to the S/390 specific parts.

The important feature of the new instruction set is the support of
single and extended precision floating point vector operations.

Note: arch12 is NOT the official name of the new CPU.  It just
continues the series of archXX options supported as alternate names.
The archXX terminology refers to the edition number of the Principle
of Operations manual.  The official CPU name will be added later while
keeping support of the arch12 for backwards compatibility.

No testsuite regressions.

Committed to mainline.

Bye,

-Andreas-

opcodes/ChangeLog:

2017-02-23  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-mkopc.c (main): Accept arch12 as cpu string and vx2 as
	facility.
	* s390-opc.c: Add new operand description macros, new instruction
	types, instruction masks, and new .insn instruction types.
	* s390-opc.txt: Add new arch12 instructions.

include/ChangeLog:

2017-02-23  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* opcode/s390.h (enum s390_opcode_cpu_val): New value
	S390_OPCODE_ARCH12.
	(S390_INSTR_FLAG_VX2): New macro definition.

gas/ChangeLog:

2017-02-23  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* config/tc-s390.c (s390_parse_cpu): New entry for arch12.
	* doc/as.texinfo: Document arch12 as cpu type.
	* doc/c-s390.texi: Likewise.
	* testsuite/gas/s390/s390.exp: Run arch12 specific tests.
	* testsuite/gas/s390/zarch-arch12.d: New test.
	* testsuite/gas/s390/zarch-arch12.s: New test.
	* testsuite/gas/s390/zarch-z13.d: Rename some mnemonics in the
	output patterns.
2017-02-23 18:27:38 +01:00
Sheldon Lobo
1e9d41d49f opcodes,gas: associate SPARC ASIs with an architecture level.
With this change an architecture level bump due to assembly ASIs will show
up as a warning/error depending on options passed to gas.

Tested with sparc64-linux-gnu, and it does not introduce any regressions.

gas/ChangeLog:

	Add support for associating SPARC ASIs with an architecture level.
	* config/tc-sparc.c (parse_sparc_asi): New encode SPARC ASIs.

opcodes/ChangeLog:

	Add support for associating SPARC ASIs with an architecture level.
	* include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
	* opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
	decoding of SPARC ASIs.
2017-02-23 07:53:16 -08:00
Andrew Waterman
f98d33be3a Add SFENCE.VMA instruction
include/ChangeLog:

2017-02-14  Andrew Waterman  <andrew@sifive.com>

        * opcode/riscv-opc.h (MATCH_SFENCE_VMA): New define.
        (MASK_SFENCE_VMA): Likewise.
        (sfence_vma): Declare instruction.

opcodes/ChangeLog:

2017-02-14  Andrew Waterman  <andrew@sifive.com>

        * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
        pseudoinstructions.
2017-02-15 10:35:00 -08:00
Alan Modra
7e0de605cb PowerPC register expression checks
This stops powerpc gas blithely accepting such nonsense as
"addi %f4,%cr3,%r31".

	PR 21118
gas/
	* NEWS: Mention powerpc register checks.
	* config/tc-ppc.c (struct pd_reg): Make value a short.  Add flags.
	(pre_defined_registers): Delete fpscr and pmr entries.  Set
	register type in flags.
	(cr_names): Set type in flags.
	(reg_name_search): Return pointer to struct pd_reg rather than value.
	(register_name): Adjust to suit.  Set X_md from flags.
	(ppc_parse_name): Likewise.
	(ppc_optimize_expr): New function.
	(md_assemble): Verify expresion reg flags match operand.
	* config/tc-ppc.h (md_optimize_expr): Define.
	(ppc_optimize_expr): Declare.
include/
	* opcode/ppc.h (PPC_OPERAND_*): Reassign values, regs first.
	(PPC_OPERAND_SPR, PPC_OPERAND_GQR): Define.
opcodes/
	* ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
	with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
2017-02-14 21:12:07 +10:30
Claudiu Zissulescu
6ec7c1ae19 [ARC] Provide an interface to decode ARC instructions.
gas/
2017-02-06  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/tc-arc.c (parse_opcode_flags): Ignore implicit flags.

include/
2017-02-06  Claudiu Zissulescu  <claziss@synopsys.com>
	    Anton Kolesov  <anton.kolesov@synopsys.com>

	* opcode/arc.h (insn_class_t): Add ENTER, LEAVE, POP, PUSH, BBIT0,
	BBIT1, BI, BIH, BRCC, EI, JLI, and SUB instruction classes.
	(flag_class_t): Add F_CLASS_WB, F_CLASS_ZZ, and F_CLASS_IMPLICIT
	flag classes.

opcode/
2017-02-06  Claudiu Zissulescu  <claziss@synopsys.com>
	    Anton Kolesov  <anton.kolesov@synopsys.com>

	* arc-dis.c (arc_disassemble_info): New structure.
	(init_arc_disasm_info): New function.
	(find_format_from_table): Ignore implicit flags.
	(find_format): Update dissassembler private data.
	(print_flags): Likewise.
	(print_insn_arc): Likewise.
	(arc_opcode_to_insn_type): Consider the new added instruction
	classes.
	(arcAnalyzeInstr): Remove.
	(arc_insn_decode): New function.
	* arc-dis.h (arc_ldst_writeback_mode): New enum.
	(arc_ldst_data_size): Likewise.
	(arc_condition_code): Likewise.
	(arc_operand_kind): Likewise.
	(arc_insn_kind): New struct.
	(arc_instruction): Likewise.
	(arc_insn_decode): Declare function.
	(ARC_Debugger_OperandType): Deleted.
	(Flow): Likewise.
	(NullifyMode): Likewise.
	(allOperandsSize): Likewise.
	(arcDisState): Likewise.
	(arcAnalyzeInstr): Likewise.
	* arc-dis.c (arc_opcode_to_insn_type): Handle newly introduced
	insn_class_t enums.
	* arc-opc.c (F_SIZED): New define.
	(C_CC_EQ, C_CC_GE, C_CC_GT, C_CC_HI, C_CC_HS): Likewise.
	(C_CC_LE, C_CC_LO, C_CC_LS, C_CC_LT, C_CC_NE): Likewise.
	(C_CC_NE, C_AA_AB, C_AA_AW, C_ZZ_D, C_ZZ_H, C_ZZ_B): Likewise.
	(arc_flag_classes): Add F_CLASS_COND/F_CLASS_IMPLICIT flags.
	* opcodes/arc-tbl.h: Update instructions to include new
	F_CLASS_IMPLICIT flags.
	(bbit0, lp): Change class.
	(bbit1, bi, bih, br*, ei_s, jli_s): Likewsie
2017-02-06 11:26:13 +01:00
Dimitar Dimitrov
a1aa5e81de Clarify that include/opcode/ files are part of GNU opcodes
include/ChangeLog:
2017-01-25  Dimitar Dimitrov  <dimitar@dinux.eu>

        * opcode/hppa.h: Clarify that file is part of GNU opcodes.
        * opcode/i860.h: Ditto.
        * opcode/nios2.h: Ditto.
        * opcode/nios2r1.h: Ditto.
        * opcode/nios2r2.h: Ditto.
        * opcode/pru.h: Ditto.

opcodes/ChangeLog:
2017-01-25  Dimitar Dimitrov  <dimitar@dinux.eu>

        * pru-opc.c: Remove vague reference to a future GDB port.
2017-01-25 12:30:52 +00:00
Szabolcs Nagy
d74d4880e2 [AArch64] Add separate feature flag for weaker release consistent load insns
The weaker release consistency support of ARMv8.3-A is allowed as an optional
extension for ARMv8.2-A, so separate command line option and feature flag is
added: -march=armv8.2-a+rcpc turns LDAPR, LDAPRB, LDAPRH instructions on.

opcodes/
	* aarch64-tbl.h (RCPC, RCPC_INSN): Define.
	(aarch64_opcode_table): Use RCPC_INSN.

include/
	* opcode/aarch64.h (AARCH64_FEATURE_RCPC): Define.
	(AARCH64_ARCH_V8_3): Update.

gas/
	* config/tc-aarch64.c (aarch64_features): Add rcpc.
	* doc/c-aarch64.texi (AArch64 Extensions): Document rcpc.
	* testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Rename to ...
	* testsuite/gas/aarch64/ldst-rcpc.d: This.
	* testsuite/gas/aarch64/ldst-exclusive-armv8_3.s: Rename to ...
	* testsuite/gas/aarch64/ldst-rcpc.s: This.
	* testsuite/gas/aarch64/ldst-rcpc-armv8_2.d: New test.
2017-01-04 12:31:08 +00:00
Kito Cheng
cc917fd93d Add support for the Q extension to the RISCV ISA.
gas    * config/tc-riscv.c (riscv_set_arch): Whitelist the "q" ISA
        extension.
        (riscv_after_parse_args): Set FLOAT_ABI_QUAD when the Q ISA is
        enabled and no other ABI is specified.

include * opcode/riscv-opc.h: Add support for the "q" ISA extension.

opcodes * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
        extension.
        * riscv-opcodes/all-opcodes: Likewise.
2017-01-03 17:42:01 +00:00
Alan Modra
2571583aed Update year range in copyright notice of all files. 2017-01-02 14:08:56 +10:30
Dimitar Dimitrov
889294f6ff PRU BFD support
include/
	* elf/common.h: Add PRU ELF.
	* elf/pru.h: New file.
	* opcode/pru.h: New file.
	* dis-asm.h (print_insn_pru): Declare.
bfd/
	* archures.c: Add bfd_arch_pru.
	* Makefile.am: Add PRU target.
	* config.bfd: Ditto.
	* configure.ac: Ditto.
	* elf-bfd.h (enum elf_target_id): Add PRU_ELF_DATA.
	* targets.c: Add pru_elf32_vec.
	* reloc.c: Add PRU relocations.
	* cpu-pru.c: New file.
	* elf32-pru.c: New file.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* po/SRC-POTFILES.in: Regenerate.
	* bfd-in2.h: Regenerate
	* libbfd.h: Regenerate.

Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
2016-12-31 12:02:09 +10:30
Maciej W. Rozycki
5284e471d5 MIPS16: Add ASMACRO instruction support
Add ASMACRO instruction support as per the MIPS16e ASE architecture
specifications [1][2], completing MIPS16e instruction set support.

[1] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e
    Application-Specific Extension to the MIPS32 Architecture", MIPS
    Technologies, Inc., Document Number: MD00076, Revision 2.63, July
    16, 2013, Section 4.1 "MIPS16e Instruction Descriptions", p. 65

[2] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e
    Application-Specific Extension to the MIPS64 Architecture", MIPS
    Technologies, Inc., Document Number: MD00077, Revision 2.60, June
    25, 2008, Section 1.1 "MIPS16e Instruction Descriptions", p. 66

	include/
	* opcode/mips.h: Document `0', `1', `2', `3', `4' and `s'
	operand codes.

	opcodes/
	* mips16-opc.c (decode_mips16_operand): Add `0', `1', `2', `3',
	`4' and `s' operand codes.
	(mips16_opcodes): Add "asmacro" entry.

	binutils/
	* testsuite/binutils-all/mips/mips16-extend-insn.d: Update for
	ASMACRO support.

	gas/
	* testsuite/gas/mips/mips16-asmacro.d: New test.
	* testsuite/gas/mips/mips16-32@mips16-asmacro.d: New test.
	* testsuite/gas/mips/mips16-64@mips16-asmacro.d: New test.
	* testsuite/gas/mips/mips16-asmacro.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.
2016-12-23 19:55:21 +00:00
Maciej W. Rozycki
d8722d7641 MIPS16: Reassign 0' and 4' operand codes
Replace `0' and `4' operand codes with `.' and `F' respectively to free
up the `0'-`4' consecutive range.  No functional change.

	gas/
	* config/tc-mips.c (mips16_macro_build): Replace `0' and `4'
	operand codes with `.' and `F' respectively.
	(mips16_macro): Likewise.

	include/
	* opcode/mips.h: Replace `0' and `4' operand codes with `.' and
	`F' respectively.

	opcodes/
	* mips16-opc.c (decode_mips16_operand): Replace `0' and `4'
	operand codes with `.' and `F' respectively.
	(mips16_opcodes): Likewise.
2016-12-23 19:37:13 +00:00
Maciej W. Rozycki
0674ee5dad MIPS16: Handle non-extensible instructions correctly
Identify non-extensible instructions in the MIPS16 opcode table and
disallow their use with the `.e' instruction size suffix in assembly and
do not interpret any EXTEND prefix present as a part of the instruction
in disassembly.

According to all versions of the MIPS16 ASE specifications the following
instructions encodings are not extensible [1][2][3][4][5][6]: I8/MOV32R,
I8/MOVR32, all RRR minor opcodes, all RR minor opcodes except from DSRA
and DSRL, and EXTEND itself, and as from revision 2.50 of the MIPS16e
ASE specifications it has been further clarified what was previously
implied, that non-extesiable instructions when preceded with an EXTEND
prefix must cause a Reserved Instruction exception [3][5].

Therefore in the presence of an EXTEND prefix none of these instructions
are supposed to be handled as extended instructions and supporting these
forms in disassembly causes confusion, and in the case of the RRR major
opcode it also clashes with the ASMACRO encoding.

References:

[1] "Product Description, MIPS16 Application-Specific Extension",
    Version 1.3, MIPS Technologies, Inc., 970130, Table 3. "MIPS16
    Instruction Set Summary", p. 5

[2] same, Table 5 "RR Minor Opcodes (RR-type instructions)", p.10

[3] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e
    Application-Specific Extension to the MIPS32 Architecture", MIPS
    Technologies, Inc., Document Number: MD00076, Revision 2.63, July
    16, 2013, Section 3.9 "MIPS16e Instruction Summaries", pp. 37-39

[4] same, Section 3.15 "Instruction Bit Encoding", pp. 46-49

[5] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e
    Application-Specific Extension to the MIPS64 Architecture", MIPS
    Technologies, Inc., Document Number: MD00077, Revision 2.60, June
    25, 2008, Section 1.9 "MIPS16e Instruction Summaries", pp. 38-41

[6] same, Section 1.15 "Instruction Bit Encoding", pp. 48-51

	include/
	* opcode/mips.h (INSN2_SHORT_ONLY): New macro.

	gas/
	* config/tc-mips.c (is_size_valid_16): Disallow a `.e' suffix
	instruction size override for INSN2_SHORT_ONLY opcode table
	entries.
	* testsuite/gas/mips/mips16-extend-swap.d: Adjust output.
	* testsuite/gas/mips/mips16-macro-e.l: Adjust error messages.
	* testsuite/gas/mips/mips16-32@mips16-macro-e.l: Adjust error
	messages.
	* testsuite/gas/mips/mips16e-32@mips16-macro-e.l: Adjust error
	messages.
	* testsuite/gas/mips/mips16-insn-e.d: New test.
	* testsuite/gas/mips/mips16-insn-t.d: New test.
	* testsuite/gas/mips/mips16-32@mips16-insn-e.d: New test.
	* testsuite/gas/mips/mips16-64@mips16-insn-e.d: New test.
	* testsuite/gas/mips/mips16e-32@mips16-insn-e.d: New test.
	* testsuite/gas/mips/mips16-32@mips16-insn-t.d: New test.
	* testsuite/gas/mips/mips16-64@mips16-insn-t.d: New test.
	* testsuite/gas/mips/mips16e-32@mips16-insn-t.d: New test.
	* testsuite/gas/mips/mips16-insn-e.l: New stderr output.
	* testsuite/gas/mips/mips16-insn-t.l: New stderr output.
	* testsuite/gas/mips/mips16-32@mips16-insn-e.l: New stderr
	output.
	* testsuite/gas/mips/mips16-64@mips16-insn-e.l: New stderr
	output.
	* testsuite/gas/mips/mips16e-32@mips16-insn-e.l: New stderr
	output.
	* testsuite/gas/mips/mips16-32@mips16-insn-t.l: New stderr
	output.
	* testsuite/gas/mips/mips16-64@mips16-insn-t.l: New stderr
	output.
	* testsuite/gas/mips/mips16e-32@mips16-insn-t.l: New stderr
	output.
	* testsuite/gas/mips/mips16-insn-e.s: New test source.
	* testsuite/gas/mips/mips16-insn-t.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.

	opcodes/
	* mips-dis.c (print_insn_mips16): Disallow EXTEND prefix
	matching for INSN2_SHORT_ONLY opcode table entries.
	* mips16-opc.c (SH): New macro.
	(mips16_opcodes): Set SH in `pinfo2' for non-extensible
	instruction entries: "nop", "addu", "and", "break", "cmp",
	"daddu", "ddiv", "ddivu", "div", "divu", "dmult", "dmultu",
	"drem", "dremu", "dsllv", "dsll", "dsrav", "dsra", "dsrlv",
	"dsrl", "dsubu", "exit", "entry", "jalr", "jal", "jr", "j",
	"jalrc", "jrc", "mfhi", "mflo", "move", "mult", "multu", "neg",
	"not", "or", "rem", "remu", "sllv", "sll", "slt", "sltu",
	"srav", "sra", "srlv", "srl", "subu", "xor", "sdbbp", "seb",
	"seh", "sew", "zeb", "zeh", "zew" and "extend".

	binutils/
	* testsuite/binutils-all/mips/mips16-extend-insn.d: New test.
	* testsuite/binutils-all/mips/mips16-extend-insn.s: New test
	source.
	* testsuite/binutils-all/mips/mips.exp: Run the new tests.
2016-12-23 19:33:45 +00:00
Alan Modra
4e25adb395 Remove high bit set characters
gas/
	* doc/c-lm32.texi: Fix chars with high bit set.
	* testsuite/gas/bfin/vector2.s: Likewise.
gold/
	* arm.cc: Fix comment chars with high bit set.
include/
	* coff/pe.h: Fix comment chars with high bit set.
	* opcode/xgate.h: Likewise.
ld/
	* testsuite/ld-scripts/sysroot-prefix.exp: Fix chars with high bit set.
2016-12-21 19:18:46 +10:30
Maciej W. Rozycki
7fd5392005 MIPS16: Switch to 32-bit opcode table interpretation
Switch to 32-bit MIPS16 opcode table entry interpretation, similar to
how the microMIPS opcode table is handled, for both the `match' and
`mask' fields, removing special casing for JAL and JALX instructions and
their `a' and `i' operand codes throughout, while retaining automatic
processing of extendable opcodes in assembly and disassembly.

In assembly disallow size enforcement suffixes as appropriate: `.t' for
both 32-bit instructions and macros and `.e' for macros only, making
macro handling consistent with the microMIPS instruction set.

In disassembly fully decode EXTEND prefixes prepended to unsupported
instruction encodings (according to the ISA selection) rather than
dumping them as hexadecimal data along with the following instruction,
removing all special casing for the EXTEND prefix and making its
handling rely on its opcode table entry, except where it is considered a
part of an extendable instruction.

	include/
	* opcode/mips.h (mips_opcode_32bit_p): New inline function.

	gas/
	* config/tc-mips.c (micromips_insn_length): Use
	`mips_opcode_32bit_p'.
	(is_size_valid): Adjust description.
	(is_size_valid_16): New function.
	(validate_mips_insn): Use `mips_opcode_32bit_p' in MIPS16
	operand decoding.
	(validate_mips16_insn): Remove `a' and `i' operand code special
	casing, use `mips_opcode_32bit_p' to determine instruction
	width.
	(append_insn): Adjust forced MIPS16 instruction size
	determination.
	(match_mips16_insn): Likewise.  Don't shift the instruction's
	opcode with the `a' and `i' operand codes.  Use
	`mips_opcode_32bit_p' in operand decoding.
	(match_mips16_insns): Check for forced instruction size's
	validity.
	(mips16_ip): Don't force instruction size in the `noautoextend'
	mode.
	* testsuite/gas/mips/mips16-jal-e.d: New test.
	* testsuite/gas/mips/mips16-jal-t.d: New test.
	* testsuite/gas/mips/mips16-macro-e.d: New test.
	* testsuite/gas/mips/mips16-macro-t.d: New test.
	* testsuite/gas/mips/mips16-jal-t.l: New stderr output.
	* testsuite/gas/mips/mips16-macro-e.l: New stderr output.
	* testsuite/gas/mips/mips16-macro-t.l: New stderr output.
	* testsuite/gas/mips/mips16-jal-e.s: New test source.
	* testsuite/gas/mips/mips16-jal-t.s: New test source.
	* testsuite/gas/mips/mips16-macro-e.s: New test source.
	* testsuite/gas/mips/mips16-macro-t.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.

	opcodes/
	* mips-dis.c (print_mips16_insn_arg): Always handle `extend' and
	`insn' together, with `extend' as the high-order 16 bits.
	(match_kind): New enum.
	(print_insn_mips16): Rework for 32-bit instruction matching.
	Do not dump EXTEND prefixes here.
	* mips16-opc.c (mips16_opcodes): Move "extend" entry to the end.
	Recode `match' and `mask' fields as 32-bit in absolute "jal" and
	"jalx" entries.

	binutils/
	* testsuite/binutils-all/mips/mips16-extend-noinsn.d: Adjust
	test for separate EXTEND prefix disassembly.
2016-12-20 11:56:32 +00:00
Renlin Li
a6a5175474 [Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm field
The internal CN register representation for coprocessor fields used in aarch64
sys, sysl instructions are removed in this patch.

After the change, those fields are represented as immediate. Related checks are
added as well.

opcodes/

	* aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
	qualifier.
	(operand_general_constraint_met_p): Remove case for CP_REG.
	(aarch64_print_operand): Print CRn, CRm operand using imm field.
	* aarch64-tbl.h (QL_SYS): Use CR qualifier.
	(QL_SYSL): Likewise.
	(aarch64_opcode_table): Change CRn, CRm operand class and type.
	* aarch64-opc-2.c : Regenerate.
	* aarch64-asm-2.c : Likewise.
	* aarch64-dis-2.c : Likewise.

include/

	* opcode/aarch64.h (aarch64_operand_class): Remove
	AARCH64_OPND_CLASS_CP_REG.
	(enum aarch64_opnd): Change AARCH64_OPND_Cn to AARCH64_OPND_CRn,
	AARCH64_OPND_Cm to AARCH64_OPND_CRm.
	(aarch64_opnd_qualifier): Define AARCH64_OPND_QLF_CR qualifier.

gas/

	* config/tc-aarch64.c (AARCH64_REG_TYPES): Remove CN register.
	(get_reg_expected_msg): Remove CN register case.
	(parse_operands): rewrite parser for CRn, CRm operand.
	(reg_names): Remove CN register.
	* testsuite/gas/aarch64/diagnostic.s: Add a new test case.
	* testsuite/gas/aarch64/diagnostic.l: Adjust error message.
2016-12-13 17:20:08 +00:00
Maciej W. Rozycki
64c1118340 MIPS16: Remove unused `>' operand code
This code has never been used throughout the repository history, and
likely not before either, as due to the assymetry of MIPS16 instruction
set encoding there are no 32-bit shift operations having their immediate
shift count placed in the position of the usual `rx' instruction field.

	gas/
	* config/tc-mips.c (mips16_macro_build) <'>'>: Remove case.

	include/
	* opcode/mips.h: Remove references to `>' operand code.

	opcodes/
	* mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
2016-12-09 23:21:40 +00:00
Maciej W. Rozycki
4b0781150f MIPS/include: opcode/mips.h: Correct INSN_CHIP_MASK
Complement commit e407c74b5b ("Support for MIPS R5900 (Sony Playstation
2)"), <https://sourceware.org/ml/binutils/2012-12/msg00240.html>, and
commit 2c62985659 ("MIPS: Add Octeon 3 support") and update the chip
mask accordingly.

	include/
	* opcode/mips.h (INSN_CHIP_MASK): Update according to bit use.
2016-12-07 12:31:38 +00:00
Maciej W. Rozycki
b8760d2cb5 MIPS/include: opcode/mips.h: Add a comment for ASE_DSPR3
Complement commit 8f4f9071ad ("Add MIPS32 DSPr3 support.").

	include/
	* opcode/mips.h (ASE_DSPR3): Add a comment.
2016-12-07 12:26:11 +00:00
Szabolcs Nagy
a12fd8e1b1 [ARM] Add ARMv8.3 command line option and feature flag
ARMv8.3 is an architectural extension of ARMv8.  Add the
feature macro and -march=armv8.3-a gas command line option
for the ARM target.

https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions

gas/
	* config/tc-arm.c (arm_archs): Add "armv8.3-a".
	* doc/c-arm.texi (-march): Add "armv8.3-a".

include/
	* opcode/arm.h (ARM_EXT2_V8_3A, ARM_AEXT2_V8_3A): New.
	(ARM_ARCH_V8_3A): New.
2016-12-05 14:07:25 +00:00
Claudiu Zissulescu
abe7c33b45 [ARC] Add checking for LP_COUNT reg usage, improve error reporting.
gas/
2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/tc-arc.c (find_opcode_match): New function argument
	errmsg.
	(assemble_tokens): Collect and report the eventual error message
	found during opcode matching process.
	* testsuite/gas/arc/lpcount-err.s: New file.
	* testsuite/gas/arc/add_s-err.s: Update error message.

opcode/
2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-opc.c (insert_ra_chk): New function.
	(insert_rb_chk): Likewise.
	(insert_rad): Update text error message.
	(insert_rcd): Likewise.
	(insert_rhv2): Likewise.
	(insert_r0): Likewise.
	(insert_r1): Likewise.
	(insert_r2): Likewise.
	(insert_r3): Likewise.
	(insert_sp): Likewise.
	(insert_gp): Likewise.
	(insert_pcl): Likewise.
	(insert_blink): Likewise.
	(insert_ilink1): Likewise.
	(insert_ilink2): Likewise.
	(insert_ras): Likewise.
	(insert_rbs): Likewise.
	(insert_rcs): Likewise.
	(insert_simm3s): Likewise.
	(insert_rrange): Likewise.
	(insert_fpel): Likewise.
	(insert_blinkel): Likewise.
	(insert_pcel): Likewise.
	(insert_nps_3bit_dst): Likewise.
	(insert_nps_3bit_dst_short): Likewise.
	(insert_nps_3bit_src2_short): Likewise.
	(insert_nps_bitop_size_2b): Likewise.
	(MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
	(RA_CHK): Define.
	(RB): Adjust.
	(RB_CHK): Define.
	(RC): Adjust.
	* arc-dis.c (print_insn_arc): Add LOAD and STORE class.
	* arc-tbl.h (div, divu): All instructions are DIVREM class.
	Change first insn argument to check for LP_COUNT usage.
	(rem): Likewise.
	(ld, ldd): All instructions are LOAD class.  Change first insn
	argument to check for LP_COUNT usage.
	(st, std): All instructions are STORE class.
	(mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
	Change first insn argument to check for LP_COUNT usage.
	(mov): All instructions are MOVE class.  Change first insn
	argument to check for LP_COUNT usage.

include/
2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>

	* opcode/arc.h (insn_class_t): Add DIVREM, LOAD, MOVE, MPY, STORE
	instruction classes.
2016-11-29 11:29:18 +01:00
Jose E. Marchesi
6884417a0f gas,opcodes: fix hardware capabilities bumping in the sparc assembler.
When the assembler finds an instruction which is part of a higher
opcode architecture it bumps the current opcode architecture.  For
example:

   $ echo "mwait" | as -bump
   {standard input}: Assembler messages:
   {standard input}:1: Warning: architecture bumped from "v6" to "v9m" on "mwait"

However, when two instructions pertaining to the same opcode
architecture but associated to different SPARC hardware capabilities
are found in the input stream, and no GAS architecture is specified in
the command line, the assembler bangs:

   $ echo "mwait; wr %g0,%g1,%mcdper" | as -bump
   {standard input}: Assembler messages:
   {standard input}:1: Warning: architecture bumped from "v6" to "v9m" on "mwait"
   {standard input}:1: Error: Hardware capability "sparc5" not enabled for "wr".

... and it should'nt, as WRMCDPER pertains to the same architecture
level than MWAIT.

This patch fixes this by extending the definition of sparc opcode
architectures to contain a set of hardware capabilities and making the
assembler to take these capabilities into account when updating the
set of allowed hwcaps when an architecture bump is triggered by some
instruction.

This way, hwcaps associated to architecture levels are maintained in
opcodes, while the assembler keeps the flexibiity of defining GAS
architectures including additional hwcaps (like -Asparcfmaf or the
v8plus* variants).

A test covering this failure case is included.

gas/ChangeLog:

2016-11-22  Jose E. Marchesi  <jose.marchesi@oracle.com>

       	* config/tc-sparc.c: Move HWS_* and HWS2_* definitions to
       	opcodes/sparc-opc.c.
       	(sparc_arch): Clarify the new role of the hwcap_allowed and
       	hwcap2_allowed fields.
       	(sparc_arch_table): Remove HWS_* and HWS2_* instances from
       	hwcap_allowed and hwcap2_allowed respectively.
       	(md_parse_option): Include the opcode arch hwcaps when processing
       	-A.
       	(sparc_ip): Use the current opcode arch hwcaps to update
       	hwcap_allowed, as well of the hwcaps of the instruction triggering
       	the bump.
       	* testsuite/gas/sparc/hwcaps-bump.s: New file.
       	* testsuite/gas/sparc/hwcaps-bump.l: Likewise.
       	* testsuite/gas/sparc/sparc.exp (gas_64_check): Run tests in
       	hwcaps-bump.

include/ChangeLog:

2016-11-22  Jose E. Marchesi  <jose.marchesi@oracle.com>

       	* opcode/sparc.h (sparc_opcode_arch): New fields hwcaps and
       	hwcaps2.

opcodes/ChangeLog:

2016-11-22  Jose E. Marchesi  <jose.marchesi@oracle.com>

       	* sparc-opc.c (HWS_V8): Definition moved from
       	gas/config/tc-sparc.c.
       	(HWS_V9): Likewise.
       	(HWS_VA): Likewise.
       	(HWS_VB): Likewise.
       	(HWS_VC): Likewise.
       	(HWS_VD): Likewise.
       	(HWS_VE): Likewise.
       	(HWS_VV): Likewise.
       	(HWS_VM): Likewise.
       	(HWS2_VM): Likewise.
       	(sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
       	existing entries.
2016-11-22 04:40:37 -08:00
Alan Modra
08dc996fed PR20744, Incorrect PowerPC VLE relocs
VLE 16A and 16D relocs were functionally swapped.

	PR 20744
include/
	* opcode/ppc.h: Define VLE insns using 16A and 16D relocs.
bfd/
	* elf32-ppc.h (struct ppc_elf_params): Add vle_reloc_fixup field.
	* elf32-ppc.c: Include opcode/ppc.h.
	(ppc_elf_howto_raw): Correct dst_mask for R_PPC_VLE_LO16A,
	R_PPC_VLE_LO16D, R_PPC_VLE_HI16A, R_PPC_VLE_HI16D, R_PPC_VLE_HA16A,
	R_PPC_VLE_HA16D, R_PPC_VLE_SDAREL_LO16A, R_PPC_VLE_SDAREL_LO16D,
	R_PPC_VLE_SDAREL_HI16A, R_PPC_VLE_SDAREL_HI16D,
	R_PPC_VLE_SDAREL_HA16A, and R_PPC_VLE_SDAREL_HA16D relocs.
	(ppc_elf_link_hash_table_create): Update default_params init.
	(ppc_elf_vle_split16): Correct shift and mask.  Add params.
	Report or fix insn/reloc mismatches.
	(ppc_elf_relocate_section): Pass input_section, offset and fixup
	to ppc_elf_vle_split16.
binutils/
	* NEWS: Mention PowerPC VLE relocation error.
gas/
	* config/tc-ppc.c: Delete VLE insn defines.
	(md_assemble): Swap use_a_reloc and use_d_reloc.
	* testsuite/gas/ppc/vle-reloc.d: Update.
ld/
	* emultempl/ppc32elf.em (params): Update initializer.  Handle
	--vle-reloc-fixup command line arg.
2016-11-22 20:19:29 +10:30
Szabolcs Nagy
c2c4ff8d52 [AArch64] Add ARMv8.3 FCMLA and FCADD instructions
Add support for FCMLA and FCADD complex arithmetic SIMD instructions.
FCMLA has an indexed element variant where the index range has to be
treated specially because a complex number takes two elements and the
indexed vector size depends on the other operands.

These complex number SIMD instructions are part of ARMv8.3
https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions

include/
2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_IMM_ROT1,
	AARCH64_OPND_IMM_ROT2, AARCH64_OPND_IMM_ROT3.
	(enum aarch64_op): Add OP_FCMLA_ELEM.

opcodes/
2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
	(aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
	(aarch64_opcode_table): Add fcmla and fcadd.
	(AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
	* aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
	* aarch64-asm.c (aarch64_ins_imm_rotate): Define.
	* aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
	* aarch64-dis.c (aarch64_ext_imm_rotate): Define.
	* aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
	* aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
	(operand_general_constraint_met_p): Rotate and index range check.
	(aarch64_print_operand): Handle rotate operand.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Likewise.
	* aarch64-opc-2.c: Likewise.

gas/
2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_IMM_ROT*.
	* testsuite/gas/aarch64/advsimd-armv8_3.d: New.
	* testsuite/gas/aarch64/advsimd-armv8_3.s: New.
	* testsuite/gas/aarch64/illegal-fcmla.s: New.
	* testsuite/gas/aarch64/illegal-fcmla.l: New.
	* testsuite/gas/aarch64/illegal-fcmla.d: New.
2016-11-18 10:02:16 +00:00
Szabolcs Nagy
3f06e55061 [AArch64] Add ARMv8.3 combined pointer authentication load instructions
Add support for ARMv8.3 LDRAA and LDRAB combined pointer authentication and
load instructions.

These instructions authenticate the base register and load 8 byte from it plus
a scaled 10-bit offset with optional writeback to update the base register.

A new instruction class (ldst_imm10) and operand type (AARCH64_OPND_ADDR_SIMM10)
were introduced to handle the special addressing form.

include/
2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM10.
	(enum aarch64_insn_class): Add ldst_imm10.

opcodes/
2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* aarch64-tbl.h (QL_X1NIL): New.
	(arch64_opcode_table): Add ldraa, ldrab.
	(AARCH64_OPERANDS): Add "ADDR_SIMM10".
	* aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
	* aarch64-asm.c (aarch64_ins_addr_simm10): Define.
	* aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
	* aarch64-dis.c (aarch64_ext_addr_simm10): Define.
	* aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
	* aarch64-opc.c (fields): Add data for FLD_S_simm10.
	(operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
	(aarch64_print_operand): Likewise.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.

gas/
2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_ADDR_SIMM10.
	(fix_insn): Likewise.
	(warn_unpredictable_ldst): Handle ldst_imm10.
	* testsuite/gas/aarch64/pac.s: Add ldraa and ldrab tests.
	* testsuite/gas/aarch64/pac.d: Likewise.
	* testsuite/gas/aarch64/illegal-ldraa.s: New.
	* testsuite/gas/aarch64/illegal-ldraa.l: New.
	* testsuite/gas/aarch64/illegal-ldraa.d: New.
2016-11-18 09:49:06 +00:00
Szabolcs Nagy
c84364ece4 [AArch64] Add ARMv8.3 PACGA instruction
Add support for the ARMv8.3 PACGA instruction.

include/
2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rm_SP.

opcodes/
2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* aarch64-tbl.h (arch64_opcode_table): Add pacga.
	(AARCH64_OPERANDS): Add Rm_SP.
	* aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.

gas/
2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* config/tc-aarch64.c (process_omitted_operand): Handle AARCH64_OPND_Rm_SP.
	(parse_operands): Likewise.
	* testsuite/gas/aarch64/pac.s: Add pacga.
	* testsuite/gas/aarch64/pac.d: Add pacga.
2016-11-11 10:39:46 +00:00
Szabolcs Nagy
1924ff7567 [AArch64] Add ARMv8.3 command line option and feature flag
ARMv8.3 can be selected with -march=armv8.3-a command line option.
An overview of the ARMv8.3 architecture extension is at
https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions

gas/
2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* config/tc-aarch64.c (aarch64_archs): Add "armv8.3-a".
	* doc/c-aarch64.texi (-march): Likewise.

include/
2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_V8_3): Define.
	(AARCH64_ARCH_V8_3): Define.
	(AARCH64_ARCH_V8_1, AARCH64_ARCH_V8_2): Simplify.
2016-11-11 10:20:30 +00:00
Thomas Preud'homme
b19ea8d28b Add support for ARM Cortex-M33 processor
2016-11-04  Thomas Preud'homme  <thomas.preudhomme@arm.com>

gas/
	* config/tc-arm.c (cortex-m33): Declare new processor.
	* doc/c-arm.texi (-mcpu ARM command line option): Document new
	Cortex-M33 processor.
	* NEWS: Mention ARM Cortex-M33 support.
2016-11-04 16:24:59 +00:00
Graham Markall
5a736821ef arc: Implement NPS-400 dcmac instruction
gas/ChangeLog:

       * testsuite/gas/arc/nps-400-9.d: Added.
       * testsuite/gas/arc/nps-400-9.s: Added.

include/ChangeLog:

       * opcode/arc.h: Add PROTOCOL_DECODE to insn_class_t.

opcodes/ChangeLog:

       * arc-dis.c (arc_insn_length): Return length 8 for instructions with
       major opcode 0xa.
       * arc-nps-400-tbl.h: Add dcmac instruction.
       * arc-opc.c (arc_operands): Added operands for dcmac instruction.
       (insert_nps_rbdouble_64): Added.
       (extract_nps_rbdouble_64): Added.
       (insert_nps_proto_size): Added.
       (extract_nps_proto_size): Added.
2016-11-03 17:14:38 +00:00
Andrew Burgess
bdfe53e3cf arc: Change max instruction length to 64-bits
The current handling for arc instructions longer than 32-bits is all
handled as a special case in both the assembler and disassembler.

The problem with this approach is that it leads to code duplication,
selecting a long instruction is exactly the same process as selecting a
short instruction, except over more bits, in both cases we select based
on bit comparison, and initial operand insertion and extraction.

This commit unifies both the long and short instruction worlds,
converting the core opcodes library from being largely 32-bit focused,
to being largely 64-bit focused.

The changes are, on the whole, not too much.  There's obviously a lot of
type changes but otherwise the bulk of the code just works.  Most of the
actual functional changes are to code that previously handled the longer
48 or 64 bit instructions.  The insert/extract handlers for these have
now been brought into line with the short instruction insert/extract
handlers.

All of the special case handling code that was previously added has now
been removed again.  Overall, this commit reduces the amount of code in
the arc assembler and disassembler.

gas/ChangeLog:

	* config/tc-arc.c (struct arc_insn): Change type of insn field.
	(md_number_to_chars_midend): Support 6- and 8-byte values.
	(emit_insn0): Update debug output.
	(find_opcode_match): Likewise.
	(build_fake_opcode_hash_entry): Delete.
	(find_special_case_long_opcode): Delete.
	(find_special_case): Remove long format special case handling.
	(insert_operand): Change instruction type and update debug print
	format.
	(assemble_insn): Change instruction type, update debug print
	formats, and remove unneeded assert.

include/ChangeLog:

	* opcode/arc.h (struct arc_opcode): Change type of opcode and mask
	fields.
	(struct arc_long_opcode): Delete.
	(struct arc_operand): Change types for insert and extract
	handlers.

opcodes/ChangeLog:

	* arc-dis.c (struct arc_operand_iterator): Remove all fields
	relating to long instruction processing, add new limm field.
	(OPCODE): Rename to...
	(OPCODE_32BIT_INSN): ...this.
	(OPCODE_AC): Delete.
	(skip_this_opcode): Handle different instruction lengths, update
	macro name.
	(special_flag_p): Update parameter type.
	(find_format_from_table): Update for more instruction lengths.
	(find_format_long_instructions): Delete.
	(find_format): Update for more instruction lengths.
	(arc_insn_length): Likewise.
	(extract_operand_value): Update for more instruction lengths.
	(operand_iterator_next): Remove code relating to long
	instructions.
	(arc_opcode_to_insn_type): New function.
	(print_insn_arc):Update for more instructions lengths.
	* arc-ext.c (extInstruction_t): Change argument type.
	* arc-ext.h (extInstruction_t): Change argument type.
	* arc-fxi.h: Change type unsigned to unsigned long long
	extensively throughout.
	* arc-nps400-tbl.h: Add long instructions taken from
	arc_long_opcodes table in arc-opc.c.
	* arc-opc.c: Update parameter types on insert/extract handlers.
	(arc_long_opcodes): Delete.
	(arc_num_long_opcodes): Delete.
	(arc_opcode_len): Update for more instruction lengths.
2016-11-03 17:14:38 +00:00
Graham Markall
2e27220211 opcodes/arc: Make some macros 64-bit safe
In preparation to moving to a world where arc instructions can be 2, 4,
6, or 8 bytes long, make some macros 64-bit safe.

There should be no functional change after this commit.

include/ChangeLog:

	* opcode/arc.h: Make macros 64-bit safe.
2016-11-03 17:14:37 +00:00
Graham Markall
06fe285fd2 arc: Replace ARC_SHORT macro with arc_opcode_len function
In preparation for moving to a world where arc instructions can be 2, 4,
6, or 8 bytes in length, replace the ARC_SHORT macro (which is either
true of false) with an arc_opcode_len function that returns a length in
bytes.

There should be no functional change after this commit.

gas/ChangeLog:

	* config/tc-arc.c (assemble_insn): Replace use of ARC_SHORT with
	arc_opcode_len.

include/ChangeLog:

	* opcode/arc.h (arc_opcode_len): Declare.
	(ARC_SHORT): Delete.

opcodes/ChangeLog:

	* arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
	with arc_opcode_len.
	(find_format_long_instructions): Likewise.
	* arc-opc.c (arc_opcode_len): New function.
2016-11-03 17:14:37 +00:00
Nick Clifton
e23eba971d Add support for RISC-V architecture.
bfd	* Makefile.am: Add entries for riscv32-elf and riscv64-elf.
	* config.bdf: Likewise.
	* configure.ac: Likewise.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* archures.c: Add bfd_riscv_arch.
	* reloc.c: Add riscv relocs.
	* targets.c: Add riscv_elf32_vec and riscv_elf64_vec.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.
	* elf-bfd.h: Add RISCV_ELF_DATA to enum elf_target_id.
	* elfnn-riscv.c: New file.
	* elfxx-riscv.c: New file.
	* elfxx-riscv.h: New file.

binutils* readelf.c (guess_is_rela): Add EM_RISCV.
	(get_machine_name): Likewise.
	(dump_relocations): Add support for riscv relocations.
	(get_machine_flags): Add support for riscv flags.
	(is_32bit_abs_reloc): Add R_RISCV_32.
	(is_64bit_abs_reloc): Add R_RISCV_64.
	(is_none_reloc): Add R_RISCV_NONE.
	* testsuite/binutils-all/objdump.exp (cpus_expected): Add riscv.
	Expect the debug_ranges test to fail.

gas	* Makefile.am: Add riscv files.
	* Makefile.in: Regenerate.
	* NEWS: Mention the support for this architecture.
	* configure.in: Define a default architecture.
	* configure: Regenerate.
	* configure.tgt: Add entries for riscv.
	* doc/as.texinfo: Likewise.
	* testsuite/gas/all/gas.exp: Expect the redef tests to fail.
	* testsuite/gas/elf/elf.exp: Expect the groupauto tests to fail.
	* config/tc-riscv.c: New file.
	* config/tc-riscv.h: New file.
	* doc/c-riscv.texi: New file.
	* testsuite/gas/riscv: New directory.
	* testsuite/gas/riscv/riscv.exp: New file.
	* testsuite/gas/riscv/t_insns.d: New file.
	* testsuite/gas/riscv/t_insns.s: New file.

ld	* Makefile.am: Add riscv files.
	* Makefile.in: Regenerate.
	* NEWS: Mention the support for this target.
	* configure.tgt: Add riscv entries.
	* emulparams/elf32lriscv-defs.sh: New file.
	* emulparams/elf32lriscv.sh: New file.
	* emulparams/elf64lriscv-defs.sh: New file.
	* emulparams/elf64lriscv.sh: New file.
	* emultempl/riscvelf.em: New file.

opcodes	* configure.ac: Add entry for bfd_riscv_arch.
	* configure: Regenerate.
	* disassemble.c (disassembler): Add support for riscv.
	(disassembler_usage): Likewise.
	* riscv-dis.c: New file.
	* riscv-opc.c: New file.

include	* dis-asm.h: Add prototypes for print_insn_riscv and
	print_riscv_disassembler_options.
	* elf/riscv.h: New file.
	* opcode/riscv-opc.h: New file.
	* opcode/riscv.h: New file.
2016-11-01 16:45:57 +00:00
Claudiu Zissulescu
e5b06ef06b [ARC] Disassembler: fix LIMM detection for short instructions.
The ARC (short) instructions are using a special register number to
indicate is the instruction uses a long immediate (LIMM).  In the case
of short instruction, this LIMM indicator depends on the ISA version
used. Thus, for ARCv1 processors, the LIMM indicator is 0x3E, the same
value used in "long" instructions.  However, for the ARCv2 processors,
this LIMM indicator is 0x1E.

This patch fixes the LIMM detection for ARCv1 ISA and adds two tests.

gas/
2016-10-13  Claudiu Zissulescu  <claziss@synopsys.com>

	* testsuite/gas/arc/shortlimm_a7.d: New file.
	* testsuite/gas/arc/shortlimm_a7.s: Likewise.
	* testsuite/gas/arc/shortlimm_hs.d: Likewise.
	* testsuite/gas/arc/shortlimm_hs.s: Likewise.

include/
2016-10-13  Claudiu Zissulescu  <claziss@synopsys.com>

	* opcode/arc.h (ARC_OPCODE_ARCV2): New define.

opcodes/
2016-10-13  Claudiu Zissulescu  <claziss@synopsys.com>

        * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
	usage on ISA basis.
2016-10-14 13:52:15 +02:00
Alan Modra
a5721ba270 Disallow 3-operand cmp[l][i] for ppc64
cmp[l][o] get an optional L field only when generating 32-bit code.
dcbf, tlbie and tlbiel keep their optional L field, ditto for R field
of tbegin.  cmprb, tsr., wlcr[all] and mtsle all change to a
compulsory L field.

L field of dcbf and wclr is 2 bits.

	PR 20641
include/
	* opcode/ppc.h (PPC_OPERAND_OPTIONAL32): Define.
opcodes/
	* ppc-opc.c (L): Make compulsory.
	(LOPT): New, optional form of L.
	(HTM_R): Define as LOPT.
	(L0, L1): Delete.
	(L32OPT): New, optional for 32-bit L.
	(L2OPT): New, 2-bit L for dcbf.
	(SVC_LEC): Update.
	(L2): Define.
	(insert_l0, extract_l0, insert_l1, extract_l2): Delete.
	(powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
	<dcbf>: Use L2OPT.
	<tlbiel, tlbie>: Use LOPT.
	<wclr, wclrall>: Use L2.
gas/
	* config/tc-ppc.c (md_assemble): Handle PPC_OPERAND_OPTIONAL32.
	* testsuite/gas/ppc/power8.s: Provide tbegin. operand.
	* testsuite/gas/ppc/power9.d: Update cmprb disassembly.
2016-09-29 15:12:47 +09:30
Claudiu Zissulescu
2b848ebdbb [ARC] ISA alignment.
include/
2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>

	* opcode/arc.h (insn_class_t): Add two new classes.

opcodes/
2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-ext-tbl.h (EXTINSN2OPF): Define.
	(EXTINSN2OP): Use EXTINSN2OPF.
	(bspeekm, bspop, modapp): New extension instructions.
	* arc-opc.c (F_DNZ_ND): Define.
	(F_DNZ_D): Likewise.
	(F_SIZEB1): Changed.
	(C_DNZ_D): Define.
	(C_HARD): Changed.
	* arc-tbl.h (dbnz): New instruction.
	(prealloc): Allow it for ARC EM.
	(xbfu): Likewise.
2016-09-26 16:47:17 +02:00
Richard Sandiford
bb7eff5206 [AArch64] Add SVE condition codes
SVE defines new names for existing NZCV conditions, to reflect the
result of instructions like PTEST.  This patch adds support for these
names.

The patch also adds comments to the disassembly output to show the
alternative names of a condition code.  For example:

	cinv	x0, x1, cc

becomes:

     	cinv	x0, x1, cc  // cc = lo, ul, last

and:

	b.cc	f0 <...>

becomes:

     	b.cc	f0 <...>  // b.lo, b.ul, b.last

Doing this for the SVE names follows the practice recommended by the
SVE specification and is definitely useful when reading SVE code.
If the feeling is that it's too distracting elsewhere, we could add
an option to turn it off.

include/
	* opcode/aarch64.h (aarch64_cond): Bump array size to 4.

opcodes/
	* aarch64-dis.c (remove_dot_suffix): New function, split out from...
	(print_mnemonic_name): ...here.
	(print_comment): New function.
	(print_aarch64_insn): Call it.
	* aarch64-opc.c (aarch64_conds): Add SVE names.
	(aarch64_print_operand): Print alternative condition names in
	a comment.

gas/
	* config/tc-aarch64.c (opcode_lookup): Search for the end of
	a condition name, rather than assuming that it will have exactly
	2 characters.
	(parse_operands): Likewise.
	* testsuite/gas/aarch64/alias.d: Add new condition-code comments
	to the expected output.
	* testsuite/gas/aarch64/beq_1.d: Likewise.
	* testsuite/gas/aarch64/float-fp16.d: Likewise.
	* testsuite/gas/aarch64/int-insns.d: Likewise.
	* testsuite/gas/aarch64/no-aliases.d: Likewise.
	* testsuite/gas/aarch64/programmer-friendly.d: Likewise.
	* testsuite/gas/aarch64/reloc-insn.d: Likewise.
	* testsuite/gas/aarch64/b_c_1.d, testsuite/gas/aarch64/b_c_1.s:
	New test.

ld/
	* testsuite/ld-aarch64/emit-relocs-280.d: Match branch comments.
	* testsuite/ld-aarch64/weak-undefined.d: Likewise.
2016-09-21 17:09:59 +01:00
Richard Sandiford
c0890d2628 [AArch64][SVE 31/32] Add SVE instructions
This patch adds the SVE instruction definitions and associated OP_*
enum values.

include/
	* opcode/aarch64.h (AARCH64_FEATURE_SVE): New macro.
	(OP_MOV_P_P, OP_MOV_Z_P_Z, OP_MOV_Z_V, OP_MOV_Z_Z, OP_MOV_Z_Zi)
	(OP_MOVM_P_P_P, OP_MOVS_P_P, OP_MOVZS_P_P_P, OP_MOVZ_P_P_P)
	(OP_NOTS_P_P_P_Z, OP_NOT_P_P_P_Z): New aarch64_ops.

opcodes/
	* aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
	(OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
	(OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
	(OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
	(OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
	(OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
	(OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
	(OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
	(OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
	(OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
	(OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
	(OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
	(OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
	(OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
	(OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
	(OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
	(OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
	(OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
	(OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
	(OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
	(OP_SVE_XWU, OP_SVE_XXU): New macros.
	(aarch64_feature_sve): New variable.
	(SVE): New macro.
	(_SVE_INSN): Likewise.
	(aarch64_opcode_table): Add SVE instructions.
	* aarch64-opc.h (extract_fields): Declare.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis.c (extract_fields): Make global.
	(do_misc_decoding): Handle the new SVE aarch64_ops.
	* aarch64-dis-2.c: Regenerate.

gas/
	* doc/c-aarch64.texi: Document the "sve" feature.
	* config/tc-aarch64.c (REG_TYPE_R_Z_BHSDQ_VZP): New register type.
	(get_reg_expected_msg): Handle it.
	(parse_operands): When parsing operands of an SVE instruction,
	disallow immediates that match REG_TYPE_R_Z_BHSDQ_VZP.
	(aarch64_features): Add an entry for SVE.
2016-09-21 16:58:48 +01:00
Richard Sandiford
116b601937 [AArch64][SVE 30/32] Add SVE instruction classes
The main purpose of the SVE aarch64_insn_classes is to describe how
an index into an aarch64_opnd_qualifier_seq_t is represented in the
instruction encoding.  Other instructions usually use flags for this
information, but (a) we're running out of those and (b) the iclass
would otherwise be unused for SVE.

include/
	* opcode/aarch64.h (sve_cpy, sve_index, sve_limm, sve_misc)
	(sve_movprfx, sve_pred_zm, sve_shift_pred, sve_shift_unpred)
	(sve_size_bhs, sve_size_bhsd, sve_size_hsd, sve_size_sd): New
	aarch64_insn_classes.

opcodes/
	* aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
	(FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
	aarch64_field_kinds.
	* aarch64-opc.c (fields): Add corresponding entries.
	* aarch64-asm.c (aarch64_get_variant): New function.
	(aarch64_encode_variant_using_iclass): Likewise.
	(aarch64_opcode_encode): Call it.
	* aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
	(aarch64_opcode_decode): Call it.
2016-09-21 16:58:22 +01:00
Richard Sandiford
047cd301d4 [AArch64][SVE 29/32] Add new SVE core & FP register operands
SVE uses some new fields to store W, X and scalar FP registers.
This patch adds corresponding operands.

include/
	* opcode/aarch64.h (AARCH64_OPND_SVE_Rm): New aarch64_opnd.
	(AARCH64_OPND_SVE_Rn_SP, AARCH64_OPND_SVE_VZn, AARCH64_OPND_SVE_Vd)
	(AARCH64_OPND_SVE_Vm, AARCH64_OPND_SVE_Vn): Likewise.

opcodes/
	* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
	and FP register operands.
	* aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
	(FLD_SVE_Vn): New aarch64_field_kinds.
	* aarch64-opc.c (fields): Add corresponding entries.
	(aarch64_print_operand): Handle the new SVE core and FP register
	operands.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-asm-2.c: Likewise.
	* aarch64-dis-2.c: Likewise.

gas/
	* config/tc-aarch64.c (parse_operands): Handle the new SVE core
	and FP register operands.
2016-09-21 16:57:43 +01:00
Richard Sandiford
165d495085 [AArch64][SVE 28/32] Add SVE FP immediate operands
This patch adds support for the new SVE floating-point immediate
operands.  One operand uses the same 8-bit encoding as base AArch64,
but in a different position.  The others use a single bit to select
between two values.

One of the single-bit operands is a choice between 0 and 1, where 0
is not a valid 8-bit encoding.  I think the cleanest way of handling
these single-bit immediates is therefore to use the IEEE float encoding
itself as the immediate value and select between the two possible values
when encoding and decoding.

As described in the covering note for the patch that added F_STRICT,
we get better error messages by accepting unsuffixed vector registers
and leaving the qualifier matching code to report an error.  This means
that we carry on parsing the other operands, and so can try to parse FP
immediates for invalid instructions like:

	fcpy	z0, #2.5

In this case there is no suffix to tell us whether the immediate should
be treated as single or double precision.  Again, we get better error
messages by picking one (arbitrary) immediate size and reporting an error
for the missing suffix later.

include/
	* opcode/aarch64.h (AARCH64_OPND_SVE_FPIMM8): New aarch64_opnd.
	(AARCH64_OPND_SVE_I1_HALF_ONE, AARCH64_OPND_SVE_I1_HALF_TWO)
	(AARCH64_OPND_SVE_I1_ZERO_ONE): Likewise.

opcodes/
	* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
	immediate operands.
	* aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
	* aarch64-opc.c (fields): Add corresponding entry.
	(operand_general_constraint_met_p): Handle the new SVE FP immediate
	operands.
	(aarch64_print_operand): Likewise.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
	(ins_sve_float_zero_one): New inserters.
	* aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
	(aarch64_ins_sve_float_half_two): Likewise.
	(aarch64_ins_sve_float_zero_one): Likewise.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
	(ext_sve_float_zero_one): New extractors.
	* aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
	(aarch64_ext_sve_float_half_two): Likewise.
	(aarch64_ext_sve_float_zero_one): Likewise.
	* aarch64-dis-2.c: Regenerate.

gas/
	* config/tc-aarch64.c (double_precision_operand_p): New function.
	(parse_operands): Use it to calculate the dp_p input to
	parse_aarch64_imm_float.  Handle the new SVE FP immediate operands.
2016-09-21 16:57:22 +01:00
Richard Sandiford
e950b34539 [AArch64][SVE 27/32] Add SVE integer immediate operands
This patch adds the new SVE integer immediate operands.  There are
three kinds:

- simple signed and unsigned ranges, but with new widths and positions.

- 13-bit logical immediates.  These have the same form as in base AArch64,
  but at a different bit position.

  In the case of the "MOV Zn.<T>, #<limm>" alias of DUPM, the logical
  immediate <limm> is not allowed to be a valid DUP immediate, since DUP
  is preferred over DUPM for constants that both instructions can handle.

- a new 9-bit arithmetic immediate, of the form "<imm8>{, LSL #8}".
  In some contexts the operand is signed and in others it's unsigned.
  As an extension, we allow shifted immediates to be written as a single
  integer, e.g. "#256" is equivalent to "#1, LSL #8".  We also use the
  shiftless form as the preferred disassembly, except for the special
  case of "#0, LSL #8" (a redundant encoding of 0).

include/
	* opcode/aarch64.h (AARCH64_OPND_SIMM5): New aarch64_opnd.
	(AARCH64_OPND_SVE_AIMM, AARCH64_OPND_SVE_ASIMM)
	(AARCH64_OPND_SVE_INV_LIMM, AARCH64_OPND_SVE_LIMM)
	(AARCH64_OPND_SVE_LIMM_MOV, AARCH64_OPND_SVE_SHLIMM_PRED)
	(AARCH64_OPND_SVE_SHLIMM_UNPRED, AARCH64_OPND_SVE_SHRIMM_PRED)
	(AARCH64_OPND_SVE_SHRIMM_UNPRED, AARCH64_OPND_SVE_SIMM5)
	(AARCH64_OPND_SVE_SIMM5B, AARCH64_OPND_SVE_SIMM6)
	(AARCH64_OPND_SVE_SIMM8, AARCH64_OPND_SVE_UIMM3)
	(AARCH64_OPND_SVE_UIMM7, AARCH64_OPND_SVE_UIMM8)
	(AARCH64_OPND_SVE_UIMM8_53): Likewise.
	(aarch64_sve_dupm_mov_immediate_p): Declare.

opcodes/
	* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
	integer immediate operands.
	* aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
	(FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
	(FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
	* aarch64-opc.c (fields): Add corresponding entries.
	(operand_general_constraint_met_p): Handle the new SVE integer
	immediate operands.
	(aarch64_print_operand): Likewise.
	(aarch64_sve_dupm_mov_immediate_p): New function.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
	(ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
	* aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
	(aarch64_ins_limm): ...here.
	(aarch64_ins_inv_limm): New function.
	(aarch64_ins_sve_aimm): Likewise.
	(aarch64_ins_sve_asimm): Likewise.
	(aarch64_ins_sve_limm_mov): Likewise.
	(aarch64_ins_sve_shlimm): Likewise.
	(aarch64_ins_sve_shrimm): Likewise.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
	(ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
	* aarch64-dis.c (decode_limm): New function, split out from...
	(aarch64_ext_limm): ...here.
	(aarch64_ext_inv_limm): New function.
	(decode_sve_aimm): Likewise.
	(aarch64_ext_sve_aimm): Likewise.
	(aarch64_ext_sve_asimm): Likewise.
	(aarch64_ext_sve_limm_mov): Likewise.
	(aarch64_top_bit): Likewise.
	(aarch64_ext_sve_shlimm): Likewise.
	(aarch64_ext_sve_shrimm): Likewise.
	* aarch64-dis-2.c: Regenerate.

gas/
	* config/tc-aarch64.c (parse_operands): Handle the new SVE integer
	immediate operands.
2016-09-21 16:56:57 +01:00
Richard Sandiford
98907a7049 [AArch64][SVE 26/32] Add SVE MUL VL addressing modes
This patch adds support for addresses of the form:

       [<base>, #<offset>, MUL VL]

This involves adding a new AARCH64_MOD_MUL_VL modifier, which is
why I split it out from the other addressing modes.

For LD2, LD3 and LD4, the offset must be a multiple of the structure
size, so for LD3 the possible values are 0, 3, 6, ....  The patch
therefore extends value_aligned_p to handle non-power-of-2 alignments.

include/
	* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4xVL): New aarch64_opnd.
	(AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, AARCH64_OPND_SVE_ADDR_RI_S4x3xVL)
	(AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, AARCH64_OPND_SVE_ADDR_RI_S6xVL)
	(AARCH64_OPND_SVE_ADDR_RI_S9xVL): Likewise.
	(AARCH64_MOD_MUL_VL): New aarch64_modifier_kind.

opcodes/
	* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
	operands.
	* aarch64-opc.c (aarch64_operand_modifiers): Initialize
	the AARCH64_MOD_MUL_VL entry.
	(value_aligned_p): Cope with non-power-of-two alignments.
	(operand_general_constraint_met_p): Handle the new MUL VL addresses.
	(print_immediate_offset_address): Likewise.
	(aarch64_print_operand): Likewise.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
	(ins_sve_addr_ri_s9xvl): New inserters.
	* aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
	(aarch64_ins_sve_addr_ri_s6xvl): Likewise.
	(aarch64_ins_sve_addr_ri_s9xvl): Likewise.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
	(ext_sve_addr_ri_s9xvl): New extractors.
	* aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
	(aarch64_ext_sve_addr_ri_s4xvl): Likewise.
	(aarch64_ext_sve_addr_ri_s6xvl): Likewise.
	(aarch64_ext_sve_addr_ri_s9xvl): Likewise.
	* aarch64-dis-2.c: Regenerate.

gas/
	* config/tc-aarch64.c (SHIFTED_NONE, SHIFTED_MUL_VL): New
	parse_shift_modes.
	(parse_shift): Handle SHIFTED_MUL_VL.
	(parse_address_main): Add an imm_shift_mode parameter.
	(parse_address, parse_sve_address): Update accordingly.
	(parse_operands): Handle MUL VL addressing modes.
2016-09-21 16:56:15 +01:00
Richard Sandiford
4df068de52 [AArch64][SVE 25/32] Add support for SVE addressing modes
This patch adds most of the new SVE addressing modes and associated
operands.  A follow-on patch adds MUL VL, since handling it separately
makes the changes easier to read.

The patch also introduces a new "operand-dependent data" field to the
operand flags, based closely on the existing one for opcode flags.
For SVE this new field needs only 2 bits, but it could be widened
in future if necessary.

include/
	* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_U6): New aarch64_opnd.
	(AARCH64_OPND_SVE_ADDR_RI_U6x2, AARCH64_OPND_SVE_ADDR_RI_U6x4)
	(AARCH64_OPND_SVE_ADDR_RI_U6x8, AARCH64_OPND_SVE_ADDR_RR)
	(AARCH64_OPND_SVE_ADDR_RR_LSL1, AARCH64_OPND_SVE_ADDR_RR_LSL2)
	(AARCH64_OPND_SVE_ADDR_RR_LSL3, AARCH64_OPND_SVE_ADDR_RX)
	(AARCH64_OPND_SVE_ADDR_RX_LSL1, AARCH64_OPND_SVE_ADDR_RX_LSL2)
	(AARCH64_OPND_SVE_ADDR_RX_LSL3, AARCH64_OPND_SVE_ADDR_RZ)
	(AARCH64_OPND_SVE_ADDR_RZ_LSL1, AARCH64_OPND_SVE_ADDR_RZ_LSL2)
	(AARCH64_OPND_SVE_ADDR_RZ_LSL3, AARCH64_OPND_SVE_ADDR_RZ_XTW_14)
	(AARCH64_OPND_SVE_ADDR_RZ_XTW_22, AARCH64_OPND_SVE_ADDR_RZ_XTW1_14)
	(AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, AARCH64_OPND_SVE_ADDR_RZ_XTW2_14)
	(AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, AARCH64_OPND_SVE_ADDR_RZ_XTW3_14)
	(AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, AARCH64_OPND_SVE_ADDR_ZI_U5)
	(AARCH64_OPND_SVE_ADDR_ZI_U5x2, AARCH64_OPND_SVE_ADDR_ZI_U5x4)
	(AARCH64_OPND_SVE_ADDR_ZI_U5x8, AARCH64_OPND_SVE_ADDR_ZZ_LSL)
	(AARCH64_OPND_SVE_ADDR_ZZ_SXTW, AARCH64_OPND_SVE_ADDR_ZZ_UXTW):
	Likewise.

opcodes/
	* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
	address operands.
	* aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
	(FLD_SVE_xs_22): New aarch64_field_kinds.
	(OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
	(get_operand_specific_data): New function.
	* aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
	FLD_SVE_xs_14 and FLD_SVE_xs_22.
	(operand_general_constraint_met_p): Handle the new SVE address
	operands.
	(sve_reg): New array.
	(get_addr_sve_reg_name): New function.
	(aarch64_print_operand): Handle the new SVE address operands.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
	(ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
	(ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
	* aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
	(aarch64_ins_sve_addr_rr_lsl): Likewise.
	(aarch64_ins_sve_addr_rz_xtw): Likewise.
	(aarch64_ins_sve_addr_zi_u5): Likewise.
	(aarch64_ins_sve_addr_zz): Likewise.
	(aarch64_ins_sve_addr_zz_lsl): Likewise.
	(aarch64_ins_sve_addr_zz_sxtw): Likewise.
	(aarch64_ins_sve_addr_zz_uxtw): Likewise.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
	(ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
	(ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
	* aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
	(aarch64_ext_sve_addr_ri_u6): Likewise.
	(aarch64_ext_sve_addr_rr_lsl): Likewise.
	(aarch64_ext_sve_addr_rz_xtw): Likewise.
	(aarch64_ext_sve_addr_zi_u5): Likewise.
	(aarch64_ext_sve_addr_zz): Likewise.
	(aarch64_ext_sve_addr_zz_lsl): Likewise.
	(aarch64_ext_sve_addr_zz_sxtw): Likewise.
	(aarch64_ext_sve_addr_zz_uxtw): Likewise.
	* aarch64-dis-2.c: Regenerate.

gas/
	* config/tc-aarch64.c (REG_TYPE_SVE_BASE, REG_TYPE_SVE_OFFSET): New
	register types.
	(get_reg_expected_msg): Handle them.
	(aarch64_addr_reg_parse): New function, split out from
	aarch64_reg_parse_32_64.  Handle Z registers too.
	(aarch64_reg_parse_32_64): Call it.
	(parse_address_main): Add base_qualifier, offset_qualifier,
	base_type and offset_type parameters.  Handle SVE base and offset
	registers.
	(parse_address): Update call to parse_address_main.
	(parse_sve_address): New function.
	(parse_operands): Parse the new SVE address operands.
2016-09-21 16:55:49 +01:00
Richard Sandiford
2442d8466e [AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALED
Some SVE instructions count the number of elements in a given vector
pattern and allow a scale factor of [1, 16] to be applied to the result.
This scale factor is written ", MUL #n", where "MUL" is a new operator.
E.g.:

	UQINCD	X0, POW2, MUL #2

This patch adds support for this kind of operand.

All existing operators were shifts of some kind, so there was a natural
range of [0, 63] regardless of context.  This was then narrowered further
by later checks (e.g. to [0, 31] when used for 32-bit values).

In contrast, MUL doesn't really have a natural context-independent range.
Rather than pick one arbitrarily, it seemed better to make the "shift"
amount a full 64-bit value and leave the range test to the usual
operand-checking code.  I've rearranged the fields of aarch64_opnd_info
so that this doesn't increase the size of the structure (although I don't
think its size is critical anyway).

include/
	* opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN_SCALED): New
	aarch64_opnd.
	(AARCH64_MOD_MUL): New aarch64_modifier_kind.
	(aarch64_opnd_info): Make shifter.amount an int64_t and
	rearrange the fields.

opcodes/
	* aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
	AARCH64_OPND_SVE_PATTERN_SCALED.
	* aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
	* aarch64-opc.c (fields): Add a corresponding entry.
	(set_multiplier_out_of_range_error): New function.
	(aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
	(operand_general_constraint_met_p): Handle
	AARCH64_OPND_SVE_PATTERN_SCALED.
	(print_register_offset_address): Use PRIi64 to print the
	shift amount.
	(aarch64_print_operand): Likewise.  Handle
	AARCH64_OPND_SVE_PATTERN_SCALED.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-asm.h (ins_sve_scale): New inserter.
	* aarch64-asm.c (aarch64_ins_sve_scale): New function.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis.h (ext_sve_scale): New inserter.
	* aarch64-dis.c (aarch64_ext_sve_scale): New function.
	* aarch64-dis-2.c: Regenerate.

gas/
	* config/tc-aarch64.c (SHIFTED_MUL): New parse_shift_mode.
	(parse_shift): Handle it.  Reject AARCH64_MOD_MUL for all other
	shift modes.  Skip range tests for AARCH64_MOD_MUL.
	(process_omitted_operand): Handle AARCH64_OPND_SVE_PATTERN_SCALED.
	(parse_operands): Likewise.
2016-09-21 16:55:22 +01:00