Prevent sparc backend making symbols dynamic unless they are undefined
weak. Use R_SPARC_RELATIVE for the symbols which are not dynamic in PIC.
This patch is tested on sparc64-unknown-linux-gnu, no regressions are
found.
bfd/ChangeLog:
2017-06-29 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
* elfxx-sparc.c (allocate_dynrelocs): Don't make a symbol dynamic
unless it is undefined weak.
* elfxx-sparc.c (_bfd_sparc_elf_relocate_section): Set the flag
relative_reloc to direct non-dynamic symbols to R_SPARC_RELATIVE
relocation.
* elfxx-sparc.c (_bfd_sparc_elf_finish_dynamic_symbol): If symbol
is not dynamic in PIC, abort.
This fix is an adaption of the x86-64 PR ld/21402 fix to AArch64.
After the generic code deciding one symbol is not dynamic, AArch64 backend
only overrides the decision on undefined weak symbols.
bfd/
PR ld/21402
* elfnn-aarch64.c (elfNN_aarch64_allocate_dynrelocs): Only make
undefined weak symbols into dynamic.
(elfNN_aarch64_final_link_relocate): Generate runtime RELATIVE
relocation for non-dynamic symbols.
(elfNN_aarch64_finish_dynamic_symbol): Add sanity check.
There are quite a few duplicated code supporting several GP based
relocation types. They are:
BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
These relocation types are supposed to be used for large memory model PIC/pic
mode under which we will have an initialized GP register points to the base of
GOT table, then these relocations are supposed to put the distance between GOT
entry and GOT table base address into the related instructions.
So, the parameters required to calculate the relocation should be the same as
BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15 etc, all of them are require the GOT entry
address and GOT table base address to perform the relocation.
This patch has removed those duplicated code when handling above listed
relocation types, grouped them with others as relocation types that are
require GOT table base address during performing relocation, reused the
existed GOT handling code.
The relocation calculation for these types before and after this patch should be
identical.
bfd/
* elfnn-aarch64.c (aarch64_relocation_aginst_gp_p): New function.
(elfNN_aarch64_final_link_relocate): Delete duplicated code for
BFD_RELOC_AARCH64_LD64_GOTOFF_LO15, BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC,
BFD_RELOC_AARCH64_MOVW_GOTOFF_G1.
* elfxx-aarch64.c (_bfd_aarch64_elf_resolve_relocation): Optimize the
support for them.
Newer Linux kernel versions offer two new register sets in support of the
z/Architecture's guarded storage facility: NT_S390_GS_CB, the
"guarded-storage registers", and NT_S390_GS_BC, the "guarded-storage
broadcast control block". This patch adds support for the respective core
notes sections to binutils.
bfd/ChangeLog:
* elf-bfd.h (elfcore_write_s390_gs_cb): Add prototype.
(elfcore_write_s390_gs_bc): Likewise.
* elf.c (elfcore_grok_s390_gs_cb): New function.
(elfcore_grok_s390_gs_bc): New function.
(elfcore_grok_note): Call them.
(elfcore_write_s390_gs_cb): New function.
(elfcore_write_s390_gs_bc): New function.
(elfcore_write_register_note): Call them.
binutils/ChangeLog:
* readelf.c (get_note_type): Add NT_S390_GS_CB and NT_S390_GS_BC.
include/ChangeLog:
* elf/common.h (NT_S390_GS_CB): New macro.
(NT_S390_GS_BC): Likewise.
Since it is impossible to read beyond the end of normal files, we only
need to check archive element size in _bfd_generic_get_section_contents
* libbfd.c (_bfd_generic_get_section_contents): Don't call
bfd_get_file_size. Check archive element size.
(_bfd_generic_get_section_contents_in_window): Likewise.
bfd_get_size and bfd_get_file_size should return the unsigned file
size. Otherwise they return negative values for file >= 2GB with
32-bit ufile_ptr.
bfd/
* bfd-in2.h: Regenerated.
* bfdio.c (bfd_get_size): Change return type to ufile_ptr.
(bfd_get_file_size): Likewise.
binutils/
* objdump.c (dump_relocs_in_section): Cast to ufile_ptr when
comparing against bfd_get_file_size return.
Add support for the Imagination interAptiv MR2 MIPS32r3 processor with
the MIPS16e2 ASE as per documentation, including in particular:
1. Support for implementation-specific interAptiv MR2 COPYW and UCOPYW
MIPS16e2 instructions[1], for assembly and disassembly,
2. Support for implementation-specific interAptiv MR2 SAVE and RESTORE
regular MIPS instructions[2], for assembly and disassembly,
3. ELF binary file annotation for the interAptiv MR2 MIPS architecture
extension.
4. Support for interAptiv MR2 architecture selection for assembly, in
the form of the `-march=interaptiv-mr2' command-line option and its
corresponding `arch=interaptiv-mr2' setting for the `.set' and
`.module' pseudo-ops.
5. Support for interAptiv MR2 architecture selection for disassembly,
in the form of the `mips:interaptiv-mr2' target architecture, for
use e.g. with the `-m' command-line option for `objdump'.
Parts of this change by Matthew Fortune and Andrew Bennett.
References:
[1] "MIPS32 interAptiv Multiprocessing System Software User's Manual",
Imagination Technologies Ltd., Document Number: MD00904, Revision
02.01, June 15, 2016, Section 24.3 "MIPS16e2 Implementation Specific
Instructions", pp. 878-883
[2] same, Chapter 25 "Implementation-specific Instructions", pp. 911-917
include/
* elf/mips.h (E_MIPS_MACH_IAMR2): New macro.
(AFL_EXT_INTERAPTIV_MR2): Likewise.
* opcode/mips.h: Document new operand codes defined.
(INSN_INTERAPTIV_MR2): New macro.
(INSN_CHIP_MASK): Adjust accordingly.
(CPU_INTERAPTIV_MR2): New macro.
(cpu_is_member) <CPU_INTERAPTIV_MR2>: New case.
(MIPS16_ALL_ARGS): Rename to...
(MIPS_SVRS_ALL_ARGS): ... this.
(MIPS16_ALL_STATICS): Rename to...
(MIPS_SVRS_ALL_STATICS): ... this.
bfd/
* archures.c (bfd_mach_mips_interaptiv_mr2): New macro.
* cpu-mips.c (I_interaptiv_mr2): New enum value.
(arch_info_struct): Add "mips:interaptiv-mr2" entry.
* elfxx-mips.c (_bfd_elf_mips_mach) <E_MIPS_MACH_IAMR2>: New
case.
(mips_set_isa_flags) <bfd_mach_mips_interaptiv_mr2>: Likewise.
(bfd_mips_isa_ext) <bfd_mach_mips_interaptiv_mr2>: Likewise.
(print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise.
(mips_mach_extensions): Add `bfd_mach_mipsisa32r3' and
`bfd_mach_mips_interaptiv_mr2' entries.
* bfd-in2.h: Regenerate.
opcodes/
* mips-formats.h (INT_BIAS): New macro.
(INT_ADJ): Redefine in INT_BIAS terms.
* mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
(mips_print_save_restore): New function.
(print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
(validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
call.
(print_insn_args): Handle OP_SAVE_RESTORE_LIST.
(print_mips16_insn_arg): Call `mips_print_save_restore' for
OP_SAVE_RESTORE_LIST handling, factored out from here.
* mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
(RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
(mips_builtin_opcodes): Add "restore" and "save" entries.
* mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
(IAMR2): New macro.
(mips16_opcodes): Add "copyw" and "ucopyw" entries.
binutils/
* readelf.c (get_machine_flags) <E_MIPS_MACH_IAMR2>: New case.
(print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise.
* NEWS: Mention Imagination interAptiv MR2 processor support.
gas/
* config/tc-mips.c (validate_mips_insn): Handle
OP_SAVE_RESTORE_LIST specially.
(mips_encode_save_restore, mips16_encode_save_restore): New
functions.
(match_save_restore_list_operand): Factor out SAVE/RESTORE
operand insertion into the instruction word or halfword to these
new functions.
(mips_cpu_info_table): Add "interaptiv-mr2" entry.
* doc/c-mips.texi (MIPS Options): Add `interaptiv-mr2' to the
`-march=' argument list.
Fix incorrect adjustment of diff relocs when relaxing, and thus the
resulting source line to address mismatch.
Fix two issues when adjusting diff relocs to account for
deleted bytes.
1. Don't adjust the difference if the end address is the shrinked
insn's address i.e. use < instead of <=. The relaxation code deletes
count bytes from or after shrinked_insn_address, so the difference
between start_address and end_address should remain unchanged in this
case.
2. Adjust the reloc addend if the difference is to be adjusted and
symval + reloc addend is past the shrinked insn address. This is
because for a typical sym1 - sym2 diff reloc, sym1 is .text +
irel->r_addend, and the addend should be reduced to account for the
shrinked insn.
For example, assume the reloc value is .text + 0x8 with .text = 0, the
diff value in the object file = 0x4, and shrinked_insn_address = 0x4
with count = 0x2. Then the existing code writes 0x2 into the object
file to account for the deleted bytes, as shrinked_insn_address lies
between 0x8 and 0x8 - 0x4 = 0x4, but leaves the addend as is. The next
time the reloc is looked at, the code sees if a shrinked_insn_address
lies between 0x8 and 0x8 - 0x2 = 0x6, instead of 0x6 and 0x4. If there
happens to be one, then the diff value in the object file ends up
getting reduced again.
bfd/
2017-06-27 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
PR ld/13402
* elf32-avr.c (elf32_avr_adjust_diff_reloc_value): Adjust
reloc addend if necessary. Adjust diff only if
shrinked_insn_address < end_address.
ld/
2017-06-27 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
PR ld/13402
* testsuite/ld-avr/pr13402.d: New test.
* testsuite/ld-avr/pr13402.s: New test.
The symbol address in .eh_frame may be adjusted in
_bfd_elf_discard_section_eh_frame, and the content of .eh_frame will be
adjusted in _bfd_elf_write_section_eh_frame. Therefore, we cannot insert
a relocation whose addend symbol is in .eh_frame. Othrewise, the value
may be adjusted twice.
bfd/ChangeLog
2017-06-26 Kuan-Lin Chen <rufus@andestech.com>
* elfnn-riscv.c (perform_relocation): Support the new
R_RISCV_32_PCREL relocation.
(riscv_elf_relocate_section): Likewise.
* elfxx-riscv.c (howto_table): Likewise.
(riscv_reloc_map): Likewise.
* bfd-in2.h (BFD_RELOC_RISCV_32_PCREL): New relocation.
* libbfd.h: Regenerate.
gas/ChangeLog
2017-06-26 Kuan-Lin Chen <rufus@andestech.com>
* config/tc-riscv.c (md_apply_fix) [BFD_RELOC_32]: Convert to a
R_RISCV_32_PCREL relocation.
include/ChangeLog
2017-06-26 Kuan-Lin Chen <rufus@andestech.com>
* elf/riscv.h (R_RISCV_32_PCREL): New.
Make BFD agree with GAS and mark the LSI MiniRISC CW4010 processor core
(for an odd reason referred to as LSI R4010 across our code base) as a
MIPS II processor in BFD as well, fixing a bug that has been there since
forever and addressing linker warnings like:
$ as -m4010 empty.s -o 4010.o
$ ld -r 4010.o -o 4010-r.o
ld: 4010.o: warning: Inconsistent ISA between e_flags and .MIPS.abiflags
$
due to the ISA level being recorded as MIPS III in ELF file header's
`e_flags' vs MIPS II in the MIPS ABI Flags section:
$ readelf -Ah 4010.o
ELF Header:
Magic: 7f 45 4c 46 01 02 01 00 00 00 00 00 00 00 00 00
Class: ELF32
Data: 2's complement, big endian
Version: 1 (current)
OS/ABI: UNIX - System V
ABI Version: 0
Type: REL (Relocatable file)
Machine: MIPS R3000
Version: 0x1
Entry point address: 0x0
Start of program headers: 0 (bytes into file)
Start of section headers: 348 (bytes into file)
Flags: 0x20821000, 4010, o32, mips3
Size of this header: 52 (bytes)
Size of program headers: 0 (bytes)
Number of program headers: 0
Size of section headers: 40 (bytes)
Number of section headers: 11
Section header string table index: 10
Attribute Section: gnu
File Attributes
Tag_GNU_MIPS_ABI_FP: Hard float (double precision)
MIPS ABI Flags Version: 0
ISA: MIPS2
GPR size: 32
CPR1 size: 32
CPR2 size: 0
FP ABI: Hard float (double precision)
ISA Extension: LSI R4010
ASEs:
None
FLAGS 1: 00000000
FLAGS 2: 00000000
$
Available documentation[1][2] clearly indicates the LSI CW4010 processor
is only backwards compatible with the MIPS R4000 processor as far as the
latter's 32-bit instructions are concerned and consequently can only be
considered a MIPS II ISA implementation (with vendor extensions).
This fixes an LD testsuite failure:
FAIL: MIPS incompatible objects: "-march=r4010 -32" "-march=r4650 -32"
triggered for the `mips-sgi-irix5' and `mips-sgi-irix6' targets.
References:
[1] Paul Cobb, Bob Caulk, Joe Cesana, "The MiniRISC CW4010: A
Superscalar MIPS Processor ASIC Core", LSI Logic, July 1995,
presented at Hot Chips VII, Stanford University, Stanford,
California, August 1995
[2] "MiniRISC MR4010 Superscalar Microprocessor Reference Device", LSI
Logic, November 1996, Doc. No. DB09-000028-00, Order No. C15017
bfd/
* cpu-mips.c (arch_info_struct): Mark the 4010 32-bit.
* elfxx-mips.c (mips_set_isa_flags) <bfd_mach_mips4010>: Set
E_MIPS_ARCH_2 rather than E_MIPS_ARCH_3 in `e_flags'.
(mips_mach_extensions): Mark `bfd_mach_mips4010' as extending
`bfd_mach_mips6000' rather than `bfd_mach_mips4000'.
ld/
* testsuite/ld-mips-elf/lsi-4010-isa.d: New test.
* ld/testsuite/ld-mips-elf/mips-elf.exp: Run the new test.
Don't check the section size in bfd_get_full_section_contents since
the size of a decompressed section may be larger than the file size.
Instead, check file size in _bfd_generic_get_section_contents.
PR binutils/21665
* compress.c (bfd_get_full_section_contents): Don't check the
file size here.
* libbfd.c (_bfd_generic_get_section_contents): Check for and
reject a section whoes size + offset is greater than the size
of the entire file.
(_bfd_generic_get_section_contents_in_window): Likewise.
Correct .startof.SECNAME/.sizeof.SECNAME tests for MIPS/IRIX targets,
complementing commit dc74becf49 ("ld: Add tests for -Ur") and commit
da614360f5 ("ld: Add tests for .startof.SECNAME/.sizeof.SECNAME") with
subsequent updates, and in reference to commit cbd0eecf26 ("Always
define referenced __start_SECNAME/__stop_SECNAME") and commit
7dba9362c1 ("Rewrite __start and __stop symbol handling").
These targets set the STT_OBJECT type for non-function symbol
references, according to `elf_frob_symbol' code in gas/config/obj-elf.c:
/* The Irix 5 and 6 assemblers set the type of any common symbol and
any undefined non-function symbol to STT_OBJECT. We try to be
compatible, since newer Irix 5 and 6 linkers care. However, we
only set undefined symbols to be STT_OBJECT if we are on Irix,
because that is the only time gcc will generate the necessary
.global directives to mark functions. */
if (S_IS_COMMON (symp))
symbol_get_bfdsym (symp)->flags |= BSF_OBJECT;
if (strstr (TARGET_OS, "irix") != NULL
&& ! S_IS_DEFINED (symp)
&& (symbol_get_bfdsym (symp)->flags & BSF_FUNCTION) == 0)
symbol_get_bfdsym (symp)->flags |= BSF_OBJECT;
and consequently entries in the symbol table listing from `readelf'
produced with these tests do not match the NOTYPE pattern expected,
causing test suite failures:
FAIL: ld-elf/sizeofa
FAIL: ld-elf/sizeofc
FAIL: ld-elf/startofa
FAIL: ld-elf/startofc
specifically with the `mips-sgi-irix5' and `mips-sgi-irix6' targets.
Given that it does not matter for the feature covered by these tests
whether the type of the symbols produced is STT_NOTYPE or STT_OBJECT
adjust the problematic cases to accept either type, removing the
failures observed.
ld/
* testsuite/ld-elf/sizeofa.d: Also accept the OBJECT type for
the symbols examined.
* testsuite/ld-elf/sizeofc.d: Likewise.
* testsuite/ld-elf/startofa.d: Likewise.
* testsuite/ld-elf/startofc.d: Likewise.
PR binutils/21665
bfd * opncls.c (get_build_id): Check that the section is beig enough
to contain the whole note.
* compress.c (bfd_get_full_section_contents): Check for and reject
a section whoes size is greater than the size of the entire file.
* elf32-v850.c (v850_elf_copy_notes): Allow for the ouput to not
contain a notes section.
binutils* objdump.c (disassemble_section): Skip any section that is bigger
than the entire file.
The recent pgste patch caused several testcases to fail with a
segfault. Fixed with this patch by adding NULL pointer checks.
regression-tested on s390x.
bfd/ChangeLog:
2017-06-26 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* elf64-s390.c (elf_s390_additional_program_headers): Add NULL
pointer checks.
(elf_s390_modify_segment_map): Likewise.
(bfd_elf_s390_set_options): Lisewise.
All sections on a --just-syms bfd are discarded from the output, so
attaching linker created sections to such a bfd results in errors.
In other cases, like the .note.GNU-stack check, it's wrong to have a
--just-syms object potentially affect the output.
bfd/
* elflink.c (_bfd_elf_link_create_dynstrtab): Don't make dynobj
a --just-syms bfd.
(_bfd_elf_size_group_sections): Skip --just-syms bfds.
(bfd_elf_size_dynamic_sections): Ignore .note.GNU-stack and
.preinit_array on --just-syms bfds.
(_bfd_elf_gc_mark_extra_sections): Skip --just-syms bfds.
(elf_gc_sweep, bfd_elf_parse_eh_frame_entries): Likewise.
(bfd_elf_gc_sections, bfd_elf_discard_info): Likewise.
ld/
* emultempl/elf32.em (gld${EMULATION_NAME}_after_open): Skip
--just-syms bfds when looking for a place to attach .note.gnu.build-id
and .eh_frame_hdr sections. Delete dead code.
The out-of-bounds access is reproducible on 'ia64-strip' command
(see sample from https://bugs.gentoo.org/show_bug.cgi?id=622500)
The output file contains less section than original one.
This tricks 'hint' access to go out-of-bounds:
* elf.c (find_link): Bounds check "hint".
=== Context ===
This patch is part of a patch series to add support for ARMv8-R
architecture. Its purpose is to add support for ARMv8-R in the linker.
=== Patch description ===
This patch is composed of 3 changes:
1) The main change is the addition of the logic for merging a file whose
Tag_CPU_arch build attribute is 15 (ARMv8-R). Namely, all pre-ARMv8 are
merged into ARMv8-R as well as ARMv8-R itself. ARMv8-A (14) merges into
ARMv8-A. ARMv8-M Baseline (16) and Mainline (17) are not allowed to
merge merge with ARMv8-R. Note that merging only occurs if the two
profiles are identical or one is S (Application or Realtime) and the
other is R.
2) using_thumb_only, using_thumb2_bl, using_thumb2 and arch_has_arm_nop
are updated according to capabilities of ARMv8-R and their BFD_ASSERT
updated to reflect that the logic is valid for ARMv8-R.
3) 2 build attribute merging tests are added to test the first change.
2017-06-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
* elf32-arm.c (using_thumb_only): Update list of architectures in
BFD_ASSERT for which the logic is valid.
(using_thumb2_bl): Likewise.
(using_thumb2): Likewise and return true for ARMv8-R.
(arch_has_arm_nop): Likewise.
(tag_cpu_arch_combine): New v8r table for ARMv8-R Tag_CPU_arch
merging logic. Update commentis for value 15 of v8m_baseline,
v8m_mainline and v4t_plus_v6_m arrays. Use v8r array to decide
merging of value 15 of Tag_CPU_arch.
ld/
* testsuite/ld-arm/arm-elf.exp (EABI attribute merging 11): New test.
(EABI attribute merging 12): Likewise.
* testsuite/ld-arm/attr-merge-11a.s: New file.
* testsuite/ld-arm/attr-merge-11b.s: New file.
* testsuite/ld-arm/attr-merge-11.attr: New file.
* testsuite/ld-arm/attr-merge-12a.s: New file.
* testsuite/ld-arm/attr-merge-12b.s: New file.
* testsuite/ld-arm/attr-merge-12.attr: New file.
BFD_RELOC_AARCH64_ADR_GOTPAGE should be BFD_RELOC_AARCH64_ADR_GOT_PAGE.
bfd/
* reloc.c (BFD_RELOC_AARCH64_ADR_GOTPAGE): Rename to
BFD_RELOC_AARCH64_ADR_GOT_PAGE
* bfd-in2.h: Regenerated.
Local undefined weak symbol should always be resolved to 0.
* elf32-i386.c (UNDEFINED_WEAK_RESOLVED_TO_ZERO): Resolve
local undefined weak symbol to 0.
* elf64-x86-64.c (UNDEFINED_WEAK_RESOLVED_TO_ZERO): Likewise.
To support IBT in Intel Control-flow Enforcement Technology (CET)
instructions:
https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf
#define GNU_PROPERTY_X86_FEATURE_1_AND 0xc0000002
#define GNU_PROPERTY_X86_FEATURE_1_IBT (1U << 0)
are added to GNU program properties to indicate that all executable
sections are compatible with IBT when ENDBR instruction starts each
valid target where an indirect branch instruction can land.
GNU_PROPERTY_X86_FEATURE_1_IBT is set on output only if it is set on
all relocatable inputs.
The followings changes are made to the Procedure Linkage Table (PLT):
1. For 64-bit x86-64, PLT is changed to
PLT0: push GOT[1]
bnd jmp *GOT[2]
nop
...
PLTn: endbr64
push namen_reloc_index
bnd jmp PLT0
together with the second PLT section:
PLTn: endbr64
bnd jmp *GOT[namen_index]
nop
BND prefix is also added so that IBT-enabled PLT is compatible with MPX.
2. For 32-bit x86-64 (x32) and i386, PLT is changed to
PLT0: push GOT[1]
jmp *GOT[2]
nop
...
PLTn: endbr64 # endbr32 for i386.
push namen_reloc_index
jmp PLT0
together with the second PLT section:
PLTn: endbr64 # endbr32 for i386.
jmp *GOT[namen_index]
nop
BND prefix isn't used since MPX isn't supported on x32 and BND registers
aren't used in parameter passing on i386.
GOT is an array of addresses. Initially, GOT[namen_index] is filled
with the address of the ENDBR instruction of the corresponding entry
in the first PLT section. The function, namen, is called via the
ENDBR instruction in the second PLT entry. GOT[namen_index] is updated
to the actual address of the function, namen, at run-time.
2 linker command line options are added:
1. -z ibtplt: Generate IBT-enabled PLT.
2. -z ibt: Generate GNU_PROPERTY_X86_FEATURE_1_IBT in GNU program
properties as well as IBT-enabled PLT.
bfd/
* elf32-i386.c (elf_i386_lazy_ibt_plt0_entry): New.
(elf_i386_lazy_ibt_plt_entry): Likewise.
(elf_i386_pic_lazy_ibt_plt0_entry): Likewise.
(elf_i386_non_lazy_ibt_plt_entry): Likewise.
(elf_i386_pic_non_lazy_ibt_plt_entry): Likewise.
(elf_i386_eh_frame_lazy_ibt_plt): Likewise.
(elf_i386_lazy_plt_layout): Likewise.
(elf_i386_non_lazy_plt_layout): Likewise.
(elf_i386_link_hash_entry): Add plt_second.
(elf_i386_link_hash_table): Add plt_second and
plt_second_eh_frame.
(elf_i386_allocate_dynrelocs): Use the second PLT if needed.
(elf_i386_size_dynamic_sections): Use .plt.got unwind info for
the second PLT. Check the second PLT.
(elf_i386_relocate_section): Use the second PLT to resolve
PLT reference if needed.
(elf_i386_finish_dynamic_symbol): Fill and use the second PLT if
needed.
(elf_i386_finish_dynamic_sections): Set sh_entsize on the
second PLT. Generate unwind info for the second PLT.
(elf_i386_plt_type): Add plt_second.
(elf_i386_get_synthetic_symtab): Support the second PLT.
(elf_i386_parse_gnu_properties): Support
GNU_PROPERTY_X86_FEATURE_1_AND.
(elf_i386_merge_gnu_properties): Support
GNU_PROPERTY_X86_FEATURE_1_AND. If info->ibt is set, turn
on GNU_PROPERTY_X86_FEATURE_1_IBT
(elf_i386_link_setup_gnu_properties): If info->ibt is set,
turn on GNU_PROPERTY_X86_FEATURE_1_IBT. Use IBT-enabled PLT
for info->ibtplt, info->ibt or GNU_PROPERTY_X86_FEATURE_1_IBT
is set on all relocatable inputs.
* elf64-x86-64.c (elf_x86_64_lazy_ibt_plt_entry): New.
(elf_x32_lazy_ibt_plt_entry): Likewise.
(elf_x86_64_non_lazy_ibt_plt_entry): Likewise.
(elf_x32_non_lazy_ibt_plt_entry): Likewise.
(elf_x86_64_eh_frame_lazy_ibt_plt): Likewise.
(elf_x32_eh_frame_lazy_ibt_plt): Likewise.
(elf_x86_64_lazy_ibt_plt): Likewise.
(elf_x32_lazy_ibt_plt): Likewise.
(elf_x86_64_non_lazy_ibt_plt): Likewise.
(elf_x32_non_lazy_ibt_plt): Likewise.
(elf_x86_64_get_synthetic_symtab): Support the second PLT.
(elf_x86_64_parse_gnu_properties): Support
GNU_PROPERTY_X86_FEATURE_1_AND.
(elf_x86_64_merge_gnu_properties): Support
GNU_PROPERTY_X86_FEATURE_1_AND. If info->ibt is set, turn
on GNU_PROPERTY_X86_FEATURE_1_IBT
(elf_x86_64_link_setup_gnu_properties): If info->ibt is set,
turn on GNU_PROPERTY_X86_FEATURE_1_IBT. Use IBT-enabled PLT
for info->ibtplt, info->ibt or GNU_PROPERTY_X86_FEATURE_1_IBT
is set on all relocatable inputs.
binutils/
* readelf.c (decode_x86_feature): New.
(print_gnu_property_note): Call decode_x86_feature on
GNU_PROPERTY_X86_FEATURE_1_AND.
* testsuite/binutils-all/i386/empty.d: New file.
* testsuite/binutils-all/i386/empty.s: Likewise.
* testsuite/binutils-all/i386/ibt.d: Likewise.
* testsuite/binutils-all/i386/ibt.s: Likewise.
* testsuite/binutils-all/x86-64/empty-x32.d: Likewise.
* testsuite/binutils-all/x86-64/empty.d: Likewise.
* testsuite/binutils-all/x86-64/empty.s: Likewise.
* testsuite/binutils-all/x86-64/ibt-x32.d: Likewise.
* testsuite/binutils-all/x86-64/ibt.d: Likewise.
* testsuite/binutils-all/x86-64/ibt.s: Likewise.
include/
* bfdlink.h (bfd_link_info): Add ibtplt and ibt.
* elf/common.h (GNU_PROPERTY_X86_FEATURE_1_AND): New.
(GNU_PROPERTY_X86_FEATURE_1_IBT): Likewise.
ld/
* Makefile.am (ELF_X86_DEPS): Add $(srcdir)/emulparams/cet.sh.
* Makefile.in: Regenerated.
* NEWS: Mention GNU_PROPERTY_X86_FEATURE_1_IBT, -z ibtplt
and -z ibt.
* emulparams/cet.sh: New file.
* testsuite/ld-i386/ibt-plt-1.d: Likewise.
* testsuite/ld-i386/ibt-plt-1.s: Likewise.
* testsuite/ld-i386/ibt-plt-2.s: Likewise.
* testsuite/ld-i386/ibt-plt-2a.d: Likewise.
* testsuite/ld-i386/ibt-plt-2b.d: Likewise.
* testsuite/ld-i386/ibt-plt-2c.d: Likewise.
* testsuite/ld-i386/ibt-plt-2d.d: Likewise.
* testsuite/ld-i386/ibt-plt-3.s: Likewise.
* testsuite/ld-i386/ibt-plt-3a.d: Likewise.
* testsuite/ld-i386/ibt-plt-3b.d: Likewise.
* testsuite/ld-i386/ibt-plt-3c.d: Likewise.
* testsuite/ld-i386/ibt-plt-3d.d: Likewise.
* testsuite/ld-i386/plt-main-ibt.dd: Likewise.
* testsuite/ld-i386/plt-pie-ibt.dd: Likewise.
* testsuite/ld-i386/property-x86-empty.s: Likewise.
* testsuite/ld-i386/property-x86-ibt.s: Likewise.
* testsuite/ld-i386/property-x86-ibt1a.d: Likewise.
* testsuite/ld-i386/property-x86-ibt1b.d: Likewise.
* testsuite/ld-i386/property-x86-ibt2.d: Likewise.
* testsuite/ld-i386/property-x86-ibt3a.d: Likewise.
* testsuite/ld-i386/property-x86-ibt3b.d: Likewise.
* testsuite/ld-i386/property-x86-ibt4.d: Likewise.
* testsuite/ld-i386/property-x86-ibt5.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-1-x32.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-1.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-1.s: Likewise.
* testsuite/ld-x86-64/ibt-plt-2.s: Likewise.
* testsuite/ld-x86-64/ibt-plt-2a-x32.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-2a.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-2b-x32.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-2b.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-2c-x32.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-2c.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-2d-x32.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-2d.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-3.s: Likewise.
* testsuite/ld-x86-64/ibt-plt-3a-x32.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-3a.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-3b-x32.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-3b.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-3c-x32.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-3c.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-3d-x32.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-3d.d: Likewise.
* testsuite/ld-x86-64/plt-main-ibt-now.rd: Likewise.
* testsuite/ld-x86-64/plt-main-ibt-x32.dd: Likewise.
* testsuite/ld-x86-64/plt-main-ibt.dd: Likewise.
* testsuite/ld-x86-64/property-x86-empty.s: Likewise.
* testsuite/ld-x86-64/property-x86-ibt.s: Likewise.
* testsuite/ld-x86-64/property-x86-ibt1a-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt1a.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt1b-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt1b.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt2-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt2.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt3a-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt3a.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt3b-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt3b.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt4-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt4.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt5-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt5.d: Likewise.
* emulparams/elf32_x86_64.sh: Source emulparams/cet.sh.
(TINY_READONLY_SECTION): Add .plt.sec.
* emulparams/elf_i386.sh: Likewise.
* emulparams/elf_x86_64.sh: Source emulparams/cet.sh.
* ld.texinfo: Document -z ibtplt and -z ibt.
* testsuite/ld-i386/i386.exp: Run IBT and IBT PLT tests.
* testsuite/ld-x86-64/x86-64.exp: Likewise.
* testsuite/ld-x86-64/pr21481b.S (check): Updated for x32.
PR binutils/21649
* som.c (setup_sections): NUL terminate the space_strings buffer.
Check that the space.name field does not index beyond the end of
the space_strings buffer.
PR binutils/21639
* vms-misc.c (_bfd_vms_save_sized_string): Use unsigned int as
type of the size parameter.
(_bfd_vms_save_counted_string): Add second parameter - the maximum
length of the counted string.
* vms.h (_bfd_vms_save_sized_string): Update prototype.
(_bfd_vms_save_counted_string): Likewise.
* vms-alpha.c (_bfd_vms_slurp_eisd): Update calls to
_bfd_vms_save_counted_string.
(_bfd_vms_slurp_ehdr): Likewise.
(_bfd_vms_slurp_egsd): Likewise.
(Parse_module): Likewise.
These don't need a following nop. Also, a localentry:0 plt call
marked with an R_PPC64_TOCSAVE reloc should ignore the tocsave.
There's no need to save r2 in the prologue for such calls.
* elf64-ppc.c (ppc64_elf_size_stubs): Test for localentry:0 plt
calls before tocsave calls.
(ppc64_elf_relocate_section): Allow localentry:0 plt calls without
following nop.
PR binutils/21640
* elf.c (setup_group): Zero the group section pointer list after
allocation so that loops can be caught. Check for NULL pointers
when processing a group list.
Since the BFD section count may not be cleared for shared objects during
linking, we should check the DYNAMIC bit for input shared objects.
bfd/
PR ld/21626
* elf-properties.c (_bfd_elf_link_setup_gnu_properties): Check
the DYNAMIC bit instead of bfd_count_sections.
ld/
PR ld/21626
* testsuite/ld-i386/i386.exp: Run ld/21626 tests.
* testsuite/ld-x86-64/x86-64.exp: Likewise.
PR binutils/21618
* vms-alpha.c (evax_bfd_print_emh): Check for insufficient record
length.
(evax_bfd_print_eeom): Likewise.
(evax_bfd_print_egsd): Check for an overlarge record length.
(evax_bfd_print_etir): Likewise.
PR binutils/21612
* libieee.h (struct common_header_type): Add end_p field.
* ieee.c (this_byte_and_next): Do not advance input_p beyond
end_p.
(read_id): Check for a length that exceeds the remaining bytes in
the input buffer.
(ieee_seek): Initialise end_p.
(ieee_archive_p): Likewise.
(ieee_object_p): Likewise.
PR 21615
* vms-alpha.c (_bfd_vms_slurp_egsd): Use unsigned int for
gsd_size. Check that there are enough bytes remaining to read the
type and size of the next egsd. Check that the size of the egsd
does not exceed the size of the record.
For some pc-relative relocations we want to allow them under PIC mode while
a normal global symbol defined in the same dynamic object can still bind
externally through copy relocation. So, we should not allow pc-relative
relocation against such symbol.
SYMBOL_REFERENCES_LOCAL should be used and is more accurate than the original
individual checks.
bfd/
* elfnn-aarch64.c (elfNN_aarch64_final_link_relocate): Use
SYMBOL_REFERENCES_LOCAL.
ld/
* testsuite/ld-aarch64/aarch64-elf.exp: Update test name
* testsuite/ld-aarch64/pcrel.s: Add new testcases.
* testsuite/ld-aarch64/pcrel_pic_undefined.d: Update the expected
warnings.
* testsuite/ld-aarch64/pcrel_pic_defined_local.d: Rename ...
* testsuite/ld-aarch64/pcrel_pic_defined.d: ... to this.
Update expected warnings.
As discussed at the PR, this patch tries to avoid COPY relocation generation
and propagate the original relocation into runtime if it was relocating on
writable section. The ELIMINATE_COPY_RELOCS has been set to true and it's
underlying infrastructure has been improved so that the COPY reloc elimination
at least working on absoluate relocations (ABS64) on AArch64.
BFD linker copy relocation elimination framwork requires the backend to always
allocate dynrelocs for all those relocation types that are possible to introduce
copy relocations. This is for adjust_dynamic_symbol hook to be able to get all
symbol reference information. Should one symbol is referenced by more than one
relocations, if there is any of them needs copy relocation then linker should
generate it.
bfd/
PR ld/21532
* elfnn-aarch64.c (ELIMINATE_COPY_RELOCS): Set to 1.
(elfNN_aarch64_final_link_relocate): Also propagate relocations to
runtime for if there needs copy relocation elimination.
(need_copy_relocation_p): New function. Return true for symbol with
pc-relative references and if it's against read-only sections.
(elfNN_aarch64_adjust_dynamic_symbol): Use need_copy_relocation_p.
(elfNN_aarch64_check_relocs): Allocate dynrelocs for relocation types
that are related with accessing external objects.
(elfNN_aarch64_gc_sweep_hook): Sync the relocation types with the change
in elfNN_aarch64_check_relocs.
ld/
* testsuite/ld-aarch64/copy-reloc-exe-2.s: New test source file.
* testsuite/ld-aarch64/copy-reloc-2.d: New test.
* testsuite/ld-aarch64/copy-reloc-exe-eliminate.s: New test source file.
* testsuite/ld-aarch64/copy-reloc-eliminate.d: New test.
* testsuite/ld-aarch64/copy-reloc-so.s: Define new global objects.
* testsuite/ld-aarch64/aarch64-elf.exp: Run new tests.
