* obj-evax.h: move openvms definitions from here to tc-alpha.c.
* tc-alpha.c: add support for vms_case_hack like in vax/vms.
(load_expression): track clobbering of base reg before jmp/jsr.
(s_alpha_file): pass case_hack flags and source filename via
symbol table to bfd.
* tc-alpha.h (TC_CONS_FIX_NEW): define
pseudo-op.
(s_space): In m68k MRI mode, align to a word boundary.
* macro.c (define_macro): Add namep parameter. Change all
callers.
* macro.h (define_macro): Update declaration.
(parse_args): Change version printing to match current GNU
standards.
* gasp.c (show_usage): Print bug report address.
(main): Change version printing to match current GNU standards.
* config/tc-arm.c (md_apply_fix3): Update two thumb instruction
slots when processing BL fixups.
* config/tc-arm.c (output_inst): Ensure Thumb BL fixup is marked
on the first half of the instruction.
Thu Sep 12 10:28:44 1996 James G. Smith <jsmith@cygnus.co.uk>
* gas/arm/thumb.s (back): Check assembly of Thumb BL.
mips_cpu is 5000, set interlocks and cop_interlocks.
(mips_ip): Give a better error message if the ISA level is wrong.
(md_parse_option): Recognize -mcpu=[v][r]5000.
* config/tc-d10v.c (d10v_dot_word): New function to support
"@word" with the word pseudo-op.
(md_apply_fix3): Cleanup and changes to support correct sizes
for 16 and 18-bit relocs.
* config/tc-mips.c (load_register): Remove unnecessary code that
was causing the high 32bits of 64bit constants to be lost.
Fixes PR10503. The compiler was producing the assembler code:
dli $3,0xfffffffffffff
when constructing the softfloat library. Unfortunately it was being
incorrectly assembled.
(v850_reloc_prefix): Provide prototype.
(postfix, get_reloc, build_insn): Remove prototypes for nonexistant
functions.
(md_begin, md_assemble, md_apply_fix3): Remove unused variables.
(md_assemble): Add default to case statement.
Minor cleanups.
routines to fetch/store the updated instruction from/to memory.
(v850_insert_operand): If the operand has a specialized insert
routine, call it.
Getting fixups closer. At least br <target> works now.
be like identical function found in tc-ppc.c.
(get_reloc): Removed.
(v850_reloc_prefix): New function, parse lo(), hi() and hi0().
(md_assemble): emit fixups.
(md_pcrel_from): renamed from md_pcrel_from_section, emit proper
displacement.
(md_apply_fix3): handle fixups/relocs.
* config/tc-v850.h (MD_PCREL_FROM_SECTION): Removed definition.
* configure.in (sh-*-elf*): New target.
* config/tc-sh.h (TARGET_ARCH): Define.
(WORKING_DOT_WORD): Define.
(TC_COFF_FIX2RTYPE): Only define if OBJ_COFF.
(BFD_ARCH, COFF_MAGIC, TC_COUNT_RELOC): Likewise.
(TC_RELOC_MANGLE, tc_coff_symbol_emit_hook): Likewise.
(DO_NOT_STRIP, NEED_FX_R_TYPE, TC_KEEP_FX_OFFSET): Likewise.
(TC_COFF_SIZEMACHDEP, tc_frob_file): Likewise.
(SUB_SEGMENT_ALIGN): Likewise.
(RELOC_32): Don't define.
(tc_frob_file_before_adjust): Define if BFD_ASSEMBLER.
(target_big_endian): Declare if OBJ_ELF.
(TARGET_FORMAT): Define if OBJ_ELF.
* config/tc-sh.c: Use BFD reloc codes instead of SH COFF reloc
numbers throughout.
(tc_crawl_symbol_chain): Only define if OBJ_COFF.
(tc_headers_hook, tc_coff_sizemachdep): Likewise.
(struct sh_count_relocs): Define.
(sh_count_relocs): New static function, broken out of
sh_frob_file. Add BFD_ASSEMBLER code.
(sh_frob_section): Likewise.
(sh_frob_file): Call sh_frob_section.
(md_convert_frag): If BFD_ASSEMBLER, change type of headers, and
call section_symbol rather than seg_info (seg)->dot.
(md_section_align): Add OBJ_ELF version.
(SWITCH_TABLE_CONS): Define.
(SWITCH_TABLE): Use SWITCH_TABLE_CONS.
(md_apply_fix): Change parameter types if BFD_ASSEMBLER. Only
handle fx_r_type == 0 if not BFD_ASSEMBLER. Return 0 if
BFD_ASSEMBLER.
(struct reloc_map): Define if not BFD_ASSEMBLER.
(coff_reloc_map): Likewise.
(sh_coff_reloc_mangle): Use coff_reloc_map to convert fx_r_type.
(tc_gen_reloc): New function if BFD_ASSEMBLER.
* write.c (write_relocs): Ifdef out fx_where test which triggers
inappropriately for SH ELF.
(write_object_file): Call tc_frob_file_before_adjust and
obj_frob_file_before_adjust if they are defined.
* write.c (write_object_file): Use BFD_RELOC_16, not
BFD_RELOC_NONE, when calling fix_new_exp for a broken word.
* config/tc-d10v.c (find_opcode): Fix a bug which could generate
the wrong opcode for cases like st2w where there are many forms
of the same instruction.
calling symbol_find_or_make.
* config/tc-ppc.h (md_parse_name): Define.
(ppc_parse_name): Declare.
* config/tc-ppc.c (reg_name_search): Add regs and regcount
parameters.
(register_name): Update call to reg_name_search.
(cr_operand): New static variable.
(cr_names): New static const array.
(ppc_parse_name): New function.
(md_assemble): If PPC_OPERAND_CR is set in the operand flags, set
cr_operand before calling expression.
PR 10460.
* config/tc-d10v.c: Fixed ".word". Fixed problem with range checking
on addresses. Improved error messages.
* doc/c-d10v.texi: Added docs for register pairs.
(add_file): Restore old file merging code, but only merge files if
fMerge is set.
(ecoff_directive_loc): Clear fMerge field of current file.
(ecoff_generate_asm_lineno): Likewise.
any given register table.
(register_name): Pass appropriate table and size to reg_name_search.
(system_register_name): New function.
(SYSREG_NAME_CNT): Define.
(md_assemble): Handle operands which are system registers.
Still working on the parser..
opcode doesn't want a register, then we don't have a match.
(md_assemble): Get size of the instruction from the opcode table.
So we choose the right opcode and so that we get the sizes right.
