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Author SHA1 Message Date
Mike Frysinger
e9b0081f98 sim: d10v: drop global callback state 
Now that we have access to the sim state in all the right places,
use existing sim helpers in place of d10v_callback directly.
 2015-11-15 20:47:24 -05:00
Mike Frysinger
aadc1740c7 sim: d10v: convert to common sim engine logic 
Now that we have access to the sim state everywhere, we can convert to
the common engine logic for overall processing.  This frees us up from
tracking exception state ourselves.
 2015-11-15 20:47:17 -05:00
Mike Frysinger
679546067e sim: d10v: push down sd/cpu vars 
By itself, this commit doesn't really change anything.  It lays the
groundwork for using the cpu state in follow up commits, both for
engine state and for cpu state.  Splitting things up this way so it
is easier to see how things have changed.
 2015-11-15 20:47:03 -05:00
GDB Administrator
a572cc6fd4 Automatic date update in version.in 2015-11-16 00:00:08 +00:00
Mike Frysinger
8ae8f9c382 sim: h8300: convert to common sim_{reason,stop} 
This ends up being pretty easy as the h8300 port already supports
much of the common engine core.
 2015-11-15 08:15:04 -05:00
Mike Frysinger
7eed1055b8 sim: mcore: pull cpu state out of global scope 
This avoids using global variables to hold the cpu state so we can
better integrate with the sim common code.

There's also a minor fix here where we move the pc register back into
the state that is accessible by the asints array.  When it was pulled
out previously, the reg store/fetch functions broke, but no one really
noticed as the mcore gdb port was dropped a while back.
 2015-11-15 08:11:15 -05:00
Mike Frysinger
9ef4651c49 sim: mcore: switch to common sim-reg 
This is not entirely useful as mcore doesn't (yet) store its register
state in the cpu state, but it does allow for switching to the common
code for these functions.
 2015-11-15 07:59:09 -05:00
Mike Frysinger
5809534fe1 sim: mcore: add a fail testcase 2015-11-15 07:55:48 -05:00
Mike Frysinger
02962cd9ea sim: mcore: convert to common reason/resume logic 
Switch over to the common event loop logic so we don't have to maintain
the exception/exit logic ourselves.
 2015-11-15 07:55:13 -05:00
Mike Frysinger
d2dfd24242 sim: clean up redundant objects 
Some of the target makefiles listed objects that were already pulled in
via SIM_NEW_COMMON_OBJS.  Clean those up.
 2015-11-15 02:43:11 -05:00
Mike Frysinger
6e4f085c7f sim: sim-close: unify sim_close logic 
Other than the nice advantage of all sims having to declare one fewer
common function, this also fixes leakage in pretty much every sim.
Many were not freeing any resources, and a few were inconsistent as
to the ones they did.  Now we have a single module that takes care of
all the logic for us.

Most of the non-cgen based ones could be deleted outright.  The cgen
ones required adding a callback to the arch-specific cleanup func.
The few that still have close callbacks are to manage their internal
state.

We do not convert erc32, m32c, ppc, rl78, or rx as they do not use
the common sim core.
 2015-11-15 02:30:19 -05:00
Mike Frysinger
1bd1b71421 sim: m32c: add a basic testsuite 2015-11-15 00:56:09 -05:00
Mike Frysinger
9bea4d16a6 sim: testsuite: support basic vars in flags 
Sometimes in tests, we need supplemental files like linker scripts or
board helper files.  There's no way to set those flags in the tests
currently and relative paths don't work (breaks out of tree builds).

Update the main option parser to replace some strings on the fly.  Now
tests can do things like:

Long term we'll want to switch the framework to use the dejagnu helpers
like dg-xxx that gcc & gdb utilize.  But that'll require more rework.
 2015-11-15 00:43:48 -05:00
Mike Frysinger
c4d4ed4083 sim: drop extern C linkage from most sim interface headers 
Since these headers merely have enum's, drop the extern C linkage
markings.  Helps to reduce the copy & paste spam.
 2015-11-15 00:38:26 -05:00
Tristan Gingold
d8bd95efd8 Bump version to 2.26.51 
bfd/
2015-11-13  Tristan Gingold  <gingold@adacore.com>

	* version.m4: Bump version to 2.26.51
	* configure: Regenerate.

binutils/
2015-11-13  Tristan Gingold  <gingold@adacore.com>

	* configure: Regenerate.

gas/
2015-11-13  Tristan Gingold  <gingold@adacore.com>

	* configure: Regenerate.

gprof/
2015-11-13  Tristan Gingold  <gingold@adacore.com>

	* configure: Regenerate.

ld/
2015-11-13  Tristan Gingold  <gingold@adacore.com>

	* configure: Regenerate.

opcodes/
2015-11-13  Tristan Gingold  <gingold@adacore.com>

	* configure: Regenerate.
 2015-11-14 16:24:39 -08:00
GDB Administrator
79bffa3b90 Automatic date update in version.in 2015-11-15 00:00:08 +00:00
Cary Coutant
db1ff0288b Fix problem where bss symbols for copy relocations are marked local. 
gold/
	PR gold/19244
	PR gold/18548
	* symtab.cc (Symbol_table::do_define_in_output_data): Check for forced
	local symbols only for predefined symbols.
 2015-11-14 11:04:01 -08:00
GDB Administrator
895d4275ba Automatic date update in version.in 2015-11-14 00:00:08 +00:00
Yao Qi
c4312b1985 PR 19051: support of inferior call with gnu vector support on ARM 
This patch teaches GDB to support gnu vector in inferior calls.  As a
result, fails in gdb.base/gnu_vector.exp are fixed.  The calling
convention of gnu vector isn't documented in the AAPCS, because it
is the GCC extension.  I checked the gcc/config/arm/arm.c, understand
how GCC pass arguments and return values, and do the same in GDB side.

The patch is tested with both hard float and soft float on arm-linux.

gdb:

2015-11-13  Yao Qi  <yao.qi@linaro.org>

	PR tdep/19051
	* arm-tdep.c (arm_type_align): Return the right alignment
	value for vector.
	(arm_vfp_cprc_sub_candidate): Return true for 64-bit and
	128-bit vector types.
	(arm_return_in_memory): Handel vector type.
 2015-11-13 15:11:58 +00:00
Yao Qi
b13c8ab2b9 Refactor arm_return_in_memory 
Current arm_return_in_memory isn't friendly to adding new things in it.
Moreover, a lot of stuff are about APCS, which is not used nowadays (AAPCS
is being used).  This patch is to refactor arm_return_in_memory, so that
some code can be shared for both APCS and AAPCS at the beginning of
arm_return_in_memory, and then each ABI (APCS and AAPCS) are processed
separately.

gdb:

2015-11-13  Yao Qi  <yao.qi@linaro.org>

	* arm-tdep.c (arm_return_in_memory): Rewrite it.
	(arm_return_value): Call arm_return_in_memory for
	TYPE_CODE_COMPLEX.
 2015-11-13 15:11:58 +00:00
Yao Qi
c1862d0f60 Remove d10v from testsuite 
This patch removes the leftover of the d10v stuff in the testsuite
directory. The d10v port was removed in GDB 6.7, but I happen to see
that there are still some leftovers about d10v in testsuite.

gdb/testsuite:

2015-11-13  Yao Qi  <yao.qi@linaro.org>

	* gdb.base/call-sc.exp (test_scalar_returns): Remove the
	comments about d10v.
	(test_scalar_returns): Likewise.
	* gdb.base/d10v.ld: Remove.
	* gdb.base/overlays.exp: Remove the target triplet checking for
	d10v-*-*.
	* gdb.base/structs.exp (test_struct_returns): Remove the
	comments about d10v.
	(test_struct_calls): Likewise.
 2015-11-13 15:06:38 +00:00
Yao Qi
77ae9c1933 gdb.base/gnu_vector.exp: Don't test output from the inferior 
gdb.base/gnu_vector.c printf the vector and gdb.base/gnu_vector.exp
expects the output by gdb_test_multiple.  Nowadays, the test doesn't
expect the output from inferior_spawn_id, which is wrong.  Even we
change the test to expect from inferior_spawn_id for the inferior
output, it is still possible the inferior exit before tcl/expect gets
the inferior output.  We see this fail on both s390x-linux and
ppc-linux on buildbot,

  FAIL: gdb.base/gnu_vector.exp: verify vector return value (the program exited)

https://sourceware.org/ml/gdb-testers/2015-q4/msg04922.html
https://sourceware.org/ml/gdb-testers/2015-q4/msg04952.html

In order to address these two shortcomings above in gnu_vector.exp,
this patch rewrites the test a little bit.  Get rid of checking the
inferior output, and instead checking them by printing them.  In this
way, the test can also be run on the target without inferior io
(gdb,noinferiorio is set in the board file).

gdb/testsuite:

2015-11-13  Yao Qi  <yao.qi@linaro.org>

	* gdb.base/gnu_vector.exp: Check the return value by "p res".
	* gdb.base/gnu_vector.c: Don't include stdio.h.
	(main): Don't print res and call add_some_intvecs.
 2015-11-13 15:03:25 +00:00
Tristan Gingold
7feec526b7 Add markers for release 2.26 
binutils/
2015-11-13  Tristan Gingold  <gingold@adacore.com>

	* NEWS: Add marker for 2.26.

gas/
2015-11-13  Tristan Gingold  <gingold@adacore.com>

	* NEWS: Add marker for 2.26.

ld/
2015-11-13  Tristan Gingold  <gingold@adacore.com>

	* NEWS: Add marker for 2.26.
 2015-11-13 09:31:25 +01:00
GDB Administrator
3319bd54ab Automatic date update in version.in 2015-11-13 00:00:07 +00:00
Marcus Shawcroft
06d2788cef Revert "[LD][AARCH64]Add TLSIE relaxation support under large memory model." 
This reverts commit 3ebe65c0ff.

Reverted due to PR19188
 2015-11-12 15:16:40 +00:00
James Greenhalgh
9c352f1c23 [AArch64] Add support for Cortex-A35 
This patch adds support to the AArch64 back-end for the Cortex-A35
processor, as recently announced by ARM. The ARM Cortex-A35 provides
full support for the ARMv8-A architecture, including the CRC extension,
with optional Advanced-SIMD and Floating-Point support. We therefore set
feature flags for this CPU to AARCH64_ARCH_V8 and AARCH64_FEATURE_CRC, in
the same fashion as Cortex-A53 and Cortex-A57.

Tested in a cross environment for AArch64 with no issues.
 2015-11-12 12:04:22 +00:00
Ramana Radhakrishnan
8915a9b7e8 Fix dates in Changelog for previous commit. 
582cfe03cb
 2015-11-12 11:14:29 +00:00
Ramana Radhakrishnan
43cdc0a8fb Add support for Cortex-A35 
2015-11-12  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/tc-arm.c (arm_cpus): Likewise.
	* doc/c-arm.texi (-mcpu=): Likewise.
 2015-11-12 11:12:53 +00:00
Ramana Radhakrishnan
582cfe03cb Fix PR gas/19217 
2015-11-11  Matthew Wahab  <matthew.wahab@arm.com>

	PR gas/19217
	* config/tc-arm.c (move_or_literal_pool): Remove redundant feature
	check.  Fix some code formatting.  Drop use of MOVT.  Add some
	comments.

2015-11-11  Matthew Wahab  <matthew.wahab@arm.com>

	PR gas/19217
        * gas/arm/thumb2_ldr_immediate_armv6t2.d: Update expected output.
 2015-11-12 10:52:03 +00:00
Yao Qi
df3b6708fe Use gdb_byte * instead of void * in push_stack_item 
gdb:

2015-11-12  Yao Qi  <yao.qi@linaro.org>

	* arm-tdep.c (push_stack_item): Change contents type to
	const gdb_byte *.
 2015-11-12 09:14:20 +00:00
Peter Bergner
a680de9a98 Add assembler, disassembler and linker support for power9. 
include/opcode/
	* ppc.h (PPC_OPCODE_POWER9): New define.
	(PPC_OPCODE_VSX3): Likewise.

opcodes/
	* ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
	Add PPC_OPCODE_VSX3 to the vsx entry.
	(powerpc_init_dialect): Set default dialect to power9.
        * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
        insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
        extract_l1 insert_xtq6, extract_xtq6): New static functions.
        (insert_esync): Test for illegal L operand value.
	(DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
	XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
	XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
	XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
	PPCVSX3): New defines.
	(powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
	fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
	<mcrxr>: Use XBFRARB_MASK.
	<addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
	bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
	cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
	cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
	lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
	lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
	modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
	rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
	stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
	subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
	vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
	vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
	vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
	vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
	vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
	vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
	vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
	xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
	xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
	xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
	xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
	xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
	xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
	xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
	xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
	xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
	xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
	xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
	xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
	xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
	<doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
	<tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.

include/elf/
	* ppc.h (R_PPC_REL16DX_HA): New reloction.
	* ppc64.h (R_PPC64_REL16DX_HA): Likewise.

bfd/
	* elf32-ppc.c (ppc_elf_howto_raw): Add R_PPC_REL16DX_HA.
	(ppc_elf_reloc_type_lookup): Handle R_PPC_REL16DX_HA.
	(ppc_elf_addr16_ha_reloc): Likewise.
	(ppc_elf_check_relocs): Likewise.
	(ppc_elf_relocate_section): Likewise.
	(is_insn_dq_form): Handle lxv and stxv instructions.
	* elf64-ppc.c (ppc64_elf_howto_raw): Add R_PPC64_REL16DX_HA.
	(ppc64_elf_reloc_type_lookup): Handle R_PPC64_REL16DX_HA.
	(ppc64_elf_ha_reloc): Likewise.
	(ppc64_elf_check_relocs): Likewise.
	(ppc64_elf_relocate_section): Likewise.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Likewise.
	* reloc.c (BFD_RELOC_PPC_REL16DX_HA): New.

elfcpp/
	* powerpc.h (R_POWERPC_REL16DX_HA): Define.

gas/
	* doc/as.texinfo (Target PowerPC): Document -mpower9 and -mpwr9.
	* doc/c-ppc.texi (PowerPC-Opts):  Likewise.
	* config/tc-ppc.c (md_show_usage): Likewise.
	(md_assemble): Handle BFD_RELOC_PPC_REL16DX_HA.
	(md_apply_fix): Likewise.
	(ppc_handle_align): Handle power9's group ending nop.

gas/testsuite/
	* gas/ppc/altivec3.s: New test.
	* gas/ppc/altivec3.d: Likewise.
	* gas/ppc/vsx3.s: Likewise.
	* gas/ppc/vsx3.d: Likewise.
	* gas/ppc/power9.s: Likewise.
	* gas/ppc/power9.d: Likewise.
	* gas/ppc/ppc.exp: Run them.
	* gas/ppc/power8.s <lxvx, lxvd2x, stxvx, stxvd2x>: Add new tests.
	* gas/ppc/power8.d: Likewise.
	* gas/ppc/vsx.s: <lxvx, stxvx>: Rename invalid mnemonics ...
	<lxvd2x, stxvd2x>: ...to this.
	* gas/ppc/vsx.d: Likewise.

gold/
	* gold/powerpc.cc (Powerpc_relocate_functions::addr16_dq): New function.
	(Powerpc_relocate_functions::addr16dx_ha): Likewise.
	(Target_powerpc::Scan::local): Handle R_POWERPC_REL16DX_HA.
	(Target_powerpc::Scan::global): Likewise.
	(Target_powerpc::Relocate::relocate): Likewise.

ld/testsuite/
	* ld-powerpc/addpcis.d: New test.
	* ld-powerpc/addpcis.s: New test.
	* ld-powerpc/powerpc.exp: Run it.
 2015-11-11 19:52:52 -06:00
GDB Administrator
3604307d2f Automatic date update in version.in 2015-11-12 00:00:09 +00:00
Marcin Kościelnicki
430e004ef7 gdb/testsuite/gdb.trace: Deduplicate set_point assembly. 
The assembly code for emitting the proper tracepointable instruction
was duplicated in many places.  Keep it in one place, to reduce work
needed for new targets.

gdb/testsuite/ChangeLog:

	* gdb.trace/change-loc.h: include "trace-common.h", remove SYMBOL
	macro.
	(func5): Removed.
	(func4): Use FAST_TRACEPOINT_LABEL.
	* gdb.trace/ftrace-lock.c: include "trace-common.h", remove SYMBOL
	macro.
	(func): Removed.
	(thread_function): Use FAST_TRACEPOINT_LABEL.
	* gdb.trace/ftrace.c: include "trace-common.h", remove SYMBOL macro.
	(func): Remove.
	(marker): Use FAST_TRACEPOINT_LABEL.
	* gdb.trace/pendshr1.c: include "trace-common.h", remove SYMBOL macro.
	(pendfunc1): Remove.
	(pendfunc): Use FAST_TRACEPOINT_LABEL.
	* gdb.trace/pendshr2.c: include "trace-common.h", remove SYMBOL macro.
	(foo): Remove.
	(pendfunc2): Use FAST_TRACEPOINT_LABEL.
	* gdb.trace/trace-break.c: include "trace-common.h", remove SYMBOL
	macro.
	(func): Remove.
	(marker): Use FAST_TRACEPOINT_LABEL.
	* gdb.trace/trace-common.h: New header.
	* gdb.trace/trace-condition.c: include "trace-common.h", remove SYMBOL
	macro.
	(func): Remove.
	(marker): Use FAST_TRACEPOINT_LABEL.
	* gdb.trace/trace-mt.c: include "trace-common.h", remove SYMBOL macro.
	(func): Remove.
	(thread_function): Use FAST_TRACEPOINT_LABEL.
 2015-11-11 21:44:04 +01:00
Simon Marchi
4397c913d5 Replace long int * cast with PTRACE_TYPE_RET * 
These casts uses the typedef target type (long int *) instead of the
typedef name.  This was a little mistake in one of the big C++ cast
patches.

gdb/ChangeLog:

	* inf-ptrace.c (inf_ptrace_fetch_register): Change long int *
	cast to PTRACE_TYPE_RET *.
	(inf_ptrace_store_register): Likewise.
 2015-11-11 15:16:05 -05:00
Andrew Burgess
5f515954d1 gdb: Make use of 'add_info' to create info sub-commands. 
Switch to using 'add_info' function for creating basic info
sub-commands.

gdb/ChangeLog:

	* avr-tdep.c (_initialize_avr_tdep): Switch to 'add_info' for creating
	info sub-commands.
	* gnu-nat.c (add_task_commands): Likewise.
	* macrocmd.c (_initialize_macrocmd): Likewise.
 2015-11-11 09:04:05 +00:00
Andrew Burgess
f3575e0837 gdb: Use class_info when creating info commands. 
The 'add_info' function is used for creating info commands, these
commands should be created as 'class_info' rather than 'no_class'.

gdb/ChangeLog:

	* cli/cli-decode.c (add_info): Switch to class_info.
 2015-11-11 09:03:25 +00:00
GDB Administrator
be20f084f1 Automatic date update in version.in 2015-11-11 00:00:08 +00:00
Marcin Kościelnicki
6e7675a70f gdb/testsuite/gdb.trace: Deduplicate pcreg/spreg/fpreg. 
These variables were used in many gdb.trace tests.  Keep them in one place,
to reduce work needed for new targets.

gdb/testsuite/ChangeLog:

	* gdb.trace/backtrace.exp: Use global fpreg/spreg definition, add $
	in front.
	* gdb.trace/change-loc.exp: Use global pcreg definition.
	* gdb.trace/collection.exp: Use global pcreg/fpreg/spreg definition.
	* gdb.trace/entry-values.exp: Use global spreg definition, add $
	in front.
	* gdb.trace/mi-trace-frame-collected.exp: Use global pcreg definition.
	* gdb.trace/pending.exp: Likewise.
	* gdb.trace/report.exp: Use global pcreg/fpreg/spreg definition.
	* gdb.trace/trace-break.exp: Likewise.
	* gdb.trace/trace-condition.exp: Use global pcreg definition, add $
	in front.
	* gdb.trace/unavailable.exp: Use global pcreg/fpreg/spreg definition.
	* gdb.trace/while-dyn.exp: Use global fpreg definition, add $
	in front.
	* lib/trace-support.exp: Define fpreg, spreg, pcreg variables.
 2015-11-10 20:05:49 +01:00
Jim Wilson
6b21c2bf57 Add Qualcomm qdf24xx support. 
gas/
	* config/tc-aarch64.c (aarch64_cpus): Add qdf24xx.
	* config/tc-arm.c (arm_cpus): Likewise.
	* doc/c-arm.texi, doc/c-aarch64.texi: Likewise.
 2015-11-10 09:19:45 -08:00
Nick Clifton
634a9f67d9 Update the RX simulator to handle the latest opcode types. 
* rx.c (id_names): Add nop4, nop5, nop6 and nop7.
	(decode_opcode): Likewise.
	(get_op): Handle RX_Operand_Zero_Indirect.
	Handle RX_Bad_Size and RX_MAX_SIZE.
	(put_op): Likewise.
	(N_MAP): Increase to 90.
 2015-11-10 16:08:35 +00:00
H.J. Lu
18954b29a1 Handle x86 VTINHERIT/VTENTRY relocs when deleting relocations 
* elf32-i386.c (elf_i386_relocate_section): Handle VTINHERIT
	and VTENTRY relocations when deleting relocations.
	* elf64-x86-64.c (elf_x86_64_relocate_section): Likewise.
 2015-11-10 04:27:51 -08:00
H.J. Lu
2d5da47320 Properly move kept relocations when deleting relocations 
* elf32-i386.c (elf_i386_relocate_section): Properly move
	kept relocations when deleting relocations.
	* elf64-x86-64.c (elf_x86_64_relocate_section): Likewise.
 2015-11-10 00:17:59 -08:00
H.J. Lu
60f2e42e00 Fix performance regression on x86 with ld -r 
Similar fix to "commit c316a17c40e44e8798b34ff84130904f2e7a53de".

	* elf32-i386.c (elf_i386_relocate_section): Use read and write
	pointers to reloc array, rather than memmove when deleting a
	reloc.  Don't use RELOC_AGAINST_DISCARDED_SECTION.  Adjust
	reloc counts at end of loop.
	* elf64-x86-64.c (elf_x86_64_relocate_section): Likewise.
 2015-11-10 00:00:04 -08:00
Mike Frysinger
6637a4265e sim: cr16/d10v: localize translation funcs 
These functions are only used in the interp module, so there's no point
in exporting them and declaring them in the external sim interface.
 2015-11-10 02:17:15 -05:00
Alan Modra
c316a17c40 Fix performance regression due to ld -r memmove 
The idea here is that instead of using memmove to shuffle the relocs
array every time one is deleted, to add a "wrel" pointer and copy from
rel[0] to wrel[0] as we go.

	* elf64-ppc.c (ppc64_elf_relocate_section): Use read and write
	pointers to reloc array, rather than memmove when deleting a
	reloc.  Don't use RELOC_AGAINST_DISCARDED_SECTION.  Adjust
	reloc counts at end of loop.
	* elf32-ppc.c (ppc_elf_relocate_section): Likewise.
 2015-11-10 17:14:41 +10:30
Mike Frysinger
1057567ea7 sim: m32c: move test code to testsuite 
Various target code belongs in the testsuite/ subdir, so move the m32c
code to match all the other targets.
 2015-11-10 00:19:49 -05:00
Mike Frysinger
9b4888d516 sim: m32c: drop redundant dependency info 2015-11-10 00:09:58 -05:00
Mike Frysinger
5697b730e2 sim: h8300: drop unused littleendian variable 2015-11-10 00:07:22 -05:00
GDB Administrator
87d094f308 Automatic date update in version.in 2015-11-10 00:00:09 +00:00
Vladimir Radosavljevic
cc203475bd Recognize .pdr debug sections. 
gold/
	* layout.h (Layout::is_debug_info_section): Recognize .pdr debug
	sections.
 2015-11-09 10:46:43 -08:00