* ppc-opc.c: Formatting and comment fixes. Move insert and
extract functions earlier, deleting forward declarations.
(insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
RA_MASK.
This fixes "-M noaliases" disassembly for "c.nop", which is an alias for
"c.addi x0, 0".
opcodes/ChangeLog
2017-08-01 Palmer Dabbelt <palmer@dabbelt.com>
* riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
According to ARMv8-A architecture manual, REG_SP is allowed in CRC32
instructions in Thumb mode. It is REG_PC that will cause unpredictable
behaviours on both ARM and Thumb.
This patch removes the incorrect warning on Thumb mode.
Meanwhile the disassembler is updated to use format "<bitfield>R" instead of
"<bitfield>S". "<bitfield>S" is not used elsewhere. so I have deleted related
code from the disassembler.
gas/
* config/tc-arm.c (do_crc32_1): Remove warning on REG_SP for thumb_mode.
* testsuite/gas/arm/crc32-armv8-a-bad.d: Update exepcted result.
* testsuite/gas/arm/crc32-armv8-r-bad.d: Likewise.
* testsuite/gas/arm/crc32-armv8-a.d: Likewise.
* testsuite/gas/arm/crc32-armv8-r.d: Likewise.
* testsuite/gas/arm/crc32-armv8-ar-bad.s: Update test case.
* testsuite/gas/arm/crc32-armv8-ar.s: Likewise.
* testsuite/gas/arm/crc32-bad.l: Update expected error message.
opcode/
* arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
register operands in CRC instructions.
(print_insn_thumb32): Remove "<bitfield>S" support. Updated the
comments.
Fix build on x86:
opcodes/disassemble.c: In function ‘disassembler’:
opcodes/disassemble.c:113:52: error: unused parameter ‘big’ [-Werror=unused-parameter]
disassembler (enum bfd_architecture a, bfd_boolean big, unsigned long mach,
^~~
opcodes/disassemble.c:113:71: error: unused parameter ‘mach’ [-Werror=unused-parameter]
disassembler (enum bfd_architecture a, bfd_boolean big, unsigned long mach,
^~~~
cc1: all warnings being treated as errors
* disassemble.c (disassembler): Mark big and mach with
ATTRIBUTE_UNUSED.
Fix `set architecture' and `set endian' command disassembly regressions
from commit 39503f8242 ("Delegate opcodes to select disassembler in
GDB"), and commit 003ca0fd22 ("Refactor disassembler selection"), as
well as a MIPS compressed ISA disassembly target regression from commit
6394c60699 ("Don't use print_insn_XXX in GDB"), which caused assertion
failures to trigger.
For example with the `mips-linux-gnu' target we get:
$ cat main.c
int
main (void)
{
return 0;
}
$ gcc -mips32r2 -O2 main.c -o main
$ gcc -mips16 -mips32r2 -O2 main.c -o main16
$ gdb
GNU gdb (GDB) 8.0.50.20170731-git
[...]
(gdb) file main
Reading symbols from main...done.
(gdb) show architecture
The target architecture is set automatically (currently mips:isa32r2)
(gdb) show endian
The target endianness is set automatically (currently big endian)
(gdb) disassemble main
Dump of assembler code for function main:
0x00400500 <+0>: jr ra
0x00400504 <+4>: move v0,zero
End of assembler dump.
(gdb) set architecture mips:isa64r2
The target architecture is assumed to be mips:isa64r2
(gdb) disassemble main
Dump of assembler code for function main:
0x00400500 <+0>:
.../gdb/arch-utils.c:979: internal-error: int default_print_insn(bfd_vma, disassemble_info*): Assertion `info->mach == bfd_get_mach (exec_bfd)' failed.
A problem internal to GDB has been detected,
further debugging may prove unreliable.
Quit this debugging session? (y or n) n
[...]
Command aborted.
(gdb) set architecture auto
The target architecture is set automatically (currently mips:isa32r2)
(gdb) set endian little
The target is assumed to be little endian
(gdb) disassemble main
Dump of assembler code for function main:
0x00400500 <+0>:
.../gdb/arch-utils.c:978: internal-error: int default_print_insn(bfd_vma, disassemble_info*): Assertion `info->endian == (bfd_big_endian (exec_bfd) ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE)' failed.
A problem internal to GDB has been detected,
further debugging may prove unreliable.
Quit this debugging session? (y or n) n
[...]
Command aborted.
(gdb) set endian auto
The target endianness is set automatically (currently big endian)
(gdb) set architecture i386
The target architecture is assumed to be i386
(gdb) disassemble main
Dump of assembler code for function main:
0x00400500 <+0>:
.../gdb/arch-utils.c:976: internal-error: int default_print_insn(bfd_vma, disassemble_info*): Assertion `info->arch == bfd_get_arch (exec_bfd)' failed.
A problem internal to GDB has been detected,
further debugging may prove unreliable.
Quit this debugging session? (y or n) n
[...]
Command aborted.
(gdb) set architecture auto
The target architecture is set automatically (currently mips:isa32r2)
(gdb) file main16
Load new symbol table from "main16"? (y or n) y
Reading symbols from main16...done.
(gdb) disassemble main
Dump of assembler code for function main:
0x00400501 <+0>:
.../gdb/arch-utils.c:979: internal-error: int default_print_insn(bfd_vma, disassemble_info*): Assertion `info->mach == bfd_get_mach (exec_bfd)' failed.
A problem internal to GDB has been detected,
further debugging may prove unreliable.
Quit this debugging session? (y or n) n
Command aborted.
(gdb)
Remove the assertions then, restoring previous semantics:
(gdb) file main
Reading symbols from main...done.
(gdb) set architecture mips:isa64r2
The target architecture is assumed to be mips:isa64r2
(gdb) disassemble main
Dump of assembler code for function main:
0x00400500 <+0>: jr ra
0x00400504 <+4>: move v0,zero
End of assembler dump.
(gdb) set endian little
The target is assumed to be little endian
(gdb) disassemble main
Dump of assembler code for function main:
0x00400500 <+0>: j 0x3800c
0x00400504 <+4>: addiu s0,t0,0
End of assembler dump.
(gdb) set architecture i386
The target architecture is assumed to be i386
(gdb) disassemble main
Dump of assembler code for function main:
0x00400500 <+0>: add %eax,%esp
0x00400502 <+2>: add %cl,(%eax)
0x00400504 <+4>: add %al,(%eax)
0x00400506 <+6>: adc %ah,0x0
End of assembler dump.
(gdb) set architecture auto
The target architecture is set automatically (currently mips:isa32r2)
(gdb) set endian auto
The target endianness is set automatically (currently big endian)
(gdb) file main16
Load new symbol table from "main16"? (y or n) y
Reading symbols from main16...done.
(gdb) disassemble main
Dump of assembler code for function main:
0x00400501 <+0>: jr ra
0x00400503 <+2>: li v0,0
End of assembler dump.
(gdb)
gdb/
* arch-utils.c (default_print_insn): Remove arch/mach/endian
assertions.
opcodes/
* disassemble.c (disassembler): Remove arch/mach/endian
assertions.
The bit pattern comment in "aarch64_opcode_lookup_1" is reversed.
This patch fixed this.
opcode/
* aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
correct the print.
* aarch64-dis-2.c: Regenerated.
With IBM z14 officially announced I can add z14 as CPU name.
No regressions with that patch on s390x.
gas/ChangeLog:
2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/tc-s390.c (s390_parse_cpu): Add z14 as alternate CPU
name.
* doc/as.texinfo: Add z14 to CPU string list.
* doc/c-s390.texi: Likewise.
opcodes/ChangeLog:
2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-mkopc.c (main): Enable z14 as CPU string in the opcode
table.
The following relocation types were added to GCC/binutils:
ARC_JLI_SECTOFF is a relocation type in Metaware that is now used by
GCC as well to adjust the index of function calls to functions with
attribute jli_call_always.
bfd/
2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
John Eric Martin <John.Martin@emmicro-us.com>
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* elf32-arc.c (JLI): Define.
* reloc.c: Add JLI relocations.
gas/
2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/jli-1.d: New file.
* testsuite/gas/arc/jli-1.s: Likewise.
* testsuite/gas/arc/taux.d: Update for jli_base.
include/
2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
John Eric Martin <John.Martin@emmicro-us.com>
* elf/arc-reloc.def: Add JLI relocs howto.
* opcode/arc-func.h (replace_jli): New function.
ld/
2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
John Eric Martin <John.Martin@emmicro-us.com>
* emulparams/arcelf.sh (JLI_START_TABLE): Define.
* scripttempl/elfarc.sc: Handle jlitab section.
* scripttempl/elfarcv2.sc: Likewise.
* testsuite/ld-arc/arc.exp: Add JLI test.
* testsuite/ld-arc/jli-script.ld: New file.
* testsuite/ld-arc/jli-simple.dd: Likewise.
* testsuite/ld-arc/jli-simple.rd: Likewise.
* testsuite/ld-arc/jli-simple.s: Likewise.
* testsuite/ld/testsuite/ld-arc/jli-overflow.s: Likewise.
* testsuite/ld/testsuite/ld-arc/jli-overflow.d: Likewise.
* testsuite/ld/testsuite/ld-arc/jli-overflow.err: Likewise.
opcode/
2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
John Eric Martin <John.Martin@emmicro-us.com>
* arc-opc.c (UIMM10_6_S_JLIOFF): Define.
(UIMM3_23): Adjust accordingly.
* arc-regs.h: Add/correct jli_base register.
* arc-tbl.h (jli_s): Likewise.
When elf section size is beyond unsigned int max value, objdump fails
to disassemble from that section. Ex on PowerPC,
$ objdump -h /proc/kcore
Idx Name Size VMA
4 load2 100000000 c000000000000000
Here, size of load2 section is 0x100000000. Also note that, 0xc00....
address range is kernel space for PowerPC. Now let's try to disassemble
do_sys_open() using /proc/kcore.
$ cat /proc/kallsyms | grep -A1 -w do_sys_open
c00000000036c000 T do_sys_open
c00000000036c2d0 T SyS_open
Before patch:
$ objdump -d --start-address=0xc00000000036c000 --stop-address=0xc00000000036c2d0 /proc/kcore
/proc/kcore: file format elf64-powerpcle
Disassembly of section load2:
c00000000036c000 <load2+0x36c000>:
c00000000036c000: Address 0xc00000000036c000 is out of bounds.
Fix this by changing type of 'buffer_length' from unsigned int to
size_t. After patch:
$ objdump -d --start-address=0xc00000000036c000 --stop-address=0xc00000000036c2d0 /proc/kcore
/proc/kcore: file format elf64-powerpcle
Disassembly of section load2:
c00000000036c000 <load2+0x36c000>:
c00000000036c000: fc 00 4c 3c addis r2,r12,252
c00000000036c004: 00 53 42 38 addi r2,r2,21248
c00000000036c008: a6 02 08 7c mflr r0
include/
* dis-asm.h (struct disassemble_info): Change type of buffer_length
field to size_t.
opcodes/
* dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
max_addr_offset and octets variables to size_t.
88c1242dc0 changed some generated files rather than the source.
* cgen-dis.in: Include disassemble.h, not dis-asm.h.
* m32c-dis.c: Regenerate.
* mep-dis.c: Regenerate.
The instructions are not documented in the Intel SDM but are documented
in the AMD APM as an alias to the group 2, ModRM.reg == 4 variant.
Both AMD and Intel CPUs execute the C[0-1] and D[0-3] instructions as
expected, i.e., like the /4 aliases:
#include <stdio.h>
int main(void)
{
int a = 2;
printf ("a before: %d\n", a);
asm volatile(".byte 0xd0,0xf0" /* SHL %al */
: "+a" (a));
printf("a after : %d\n", a);
return 0;
}
$ ./a.out
a before: 2
a after : 4
This patch adds support mvfr2 control registers for armv8-a as
this was missed from the original port to armv8-a (documented
at G6.2.109 in (Issue B.a) of the ARM-ARM. This was discovered
by an internal user of the GNU toolchain.
I'd like to backport this to the binutils 2.28 and binutils 2.29
release branch if possible (with suitable testing and basically
checking removing the armv8-r parts).
Tristan - are you ok with the backports ?
Applied to trunk.
regards Ramana
2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* gas/config/tc-arm.c (arm_regs): Add MVFR2.
(do_vmrs): Constraint for MVFR2 and armv8.
(do_vmsr): Likewise.
* gas/testsuite/gas/arm/armv8-a+fp.d: Update.
* gas/testsuite/gas/arm/armv8-ar+fp.s: Likewise.
* gas/testsuite/gas/arm/armv8-r+fp.d: Likewise.
* gas/testsuite/gas/arm/vfp-bad.s: Likewise.
* gas/testsuite/gas/arm/vfp-bad.l: Likewise.
* opcodes/arm-dis.c: Support MVFR2 in disassembly
with vmrs and vmsr.
Correct an issue introduced with commit 7361da2c95 ("Add support for
MIPS R6.") and move the LSA and DLSA instructions back to the MSA ASE
instruction block in the regular MIPS opcode table. Adjust formatting
around the "MIPS r6" heading.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
entries to the MSA ASE instruction block.
Add support for the base and Virtualization ASE microMIPS instructions
as per the architecture specifications[1][2][3][4].
Most of this change by Andrew Bennett.
[1] "MIPS Architecture for Programmers Volume II-B: The microMIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00582,
Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit
Instructions", p. 340
[2] "microMIPS32 Architecture for Programmers Volume IV-i:
Virtualization Module of the microMIPS32 Architecture", MIPS
Technologies, Inc., Document Number: MD00848, Revision 1.06,
December 10, 2013, Section 6.1 "Overview", pp. 133, 136
[3] "MIPS Architecture for Programmers Volume II-B: The microMIPS64
Instruction Set", MIPS Technologies, Inc., Document Number: MD00594,
Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit
Instructions", pp. 415, 444
[4] "microMIPS64 Architecture for Programmers Volume IV-i:
Virtualization Module of the microMIPS64 Architecture", MIPS
Technologies, Inc., Document Number: MD00849, Revision 1.06,
December 10, 2013, Section 6.1 "Overview", pp. 134-135, 139-140
binutils/
* NEWS: Mention microMIPS XPA support.
opcodes/
* micromips-opc.c (XPA, XPAVZ): New macros.
(micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
"mthgc0".
gas/
* config/tc-mips.c (mips_ases): Add microMIPS XPA support.
* testsuite/gas/mips/micromips@xpa.d: New test.
* testsuite/gas/mips/mips.exp: Run the new test. Enable
`xpa-virt-err' test for `micromips'.
Add base microMIPS Release 5 ISA support and the ERETNC instruction in
particular, as per the architecture specifications[1][2].
Most of this change by Andrew Bennett.
References:
[1] "MIPS Architecture for Programmers Volume II-B: The microMIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00582,
Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit
Instructions", pp. 266-267
[2] "MIPS Architecture for Programmers Volume II-B: The microMIPS64
Instruction Set", MIPS Technologies, Inc., Document Number: MD00594,
Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit
Instructions", pp. 326-327
binutils/
* NEWS: Mention microMIPS Release 5 ISA support.
opcodes/
* micromips-opc.c (I36): New macro.
(micromips_opcodes): Add "eretnc".
gas/
* testsuite/gas/mips/micromips@r5.d: New test.
* testsuite/gas/mips/mips.exp: Run the new test.
Correct a commit 7d64c587c1 ("Add support for the MIPS eXtended
Physical Address (XPA) ASE.") bug, causing XPA base and Virtualization
ASE instructions to be wrongly always enabled with the selection of the
MIPS32r2 or higher ISA.
For example this source assembles successfully as shown below:
$ cat xpa.s
mfhc0 $2, $1
$ as -32 -mips32 -o xpa.o xpa.s
xpa.s: Assembler messages:
xpa.s:1: Error: opcode not supported on this processor: mips32 (mips32) `mfhc0 $2,$1'
$ as -32 -mips32r2 -o xpa.o xpa.s
$ objdump -d xpa.o
xpa.o: file format elf32-tradbigmips
Disassembly of section .text:
00000000 <.text>:
0: 40420800 mfhc0 v0,c0_random
...
$
To address this issue remove the I33 (INSN_ISA32R2) marking from all XPA
instructions in the opcode table. Additionally, for XPA Virtualization
ASE instructions implement an XPAVZ (ASE_XPA_VIRT) combination ASE flag
and use it in place of IVIRT|XPA (ASE_VIRT|ASE_XPA).
Now the same source is correctly rejected unless the `-mxpa' option is
also used:
$ as -32 -mips32r2 -o xpa.o xpa.s
xpa.s: Assembler messages:
xpa.s:1: Error: opcode not supported on this processor: mips32r2 (mips32r2) `mfhc0 $2,$1'
$ as -32 -mips32r2 -mxpa -o xpa.o xpa.s
$
Add test cases for XPA base and XPA Virtualization ASE instructions.
Parts of this change by Andrew Bennett.
include/
* opcode/mips.h (ASE_XPA_VIRT): New macro.
opcodes/
* mips-dis.c (mips_calculate_combination_ases): Handle the
ASE_XPA_VIRT flag.
(parse_mips_ase_option): New function.
(parse_mips_dis_option): Factor out ASE option handling to the
new function. Call `mips_calculate_combination_ases'.
* mips-opc.c (XPAVZ): New macro.
(mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
"mfhgc0", "mthc0" and "mthgc0".
gas/
* config/tc-mips.c (mips_set_ase): Handle the ASE_XPA_VIRT flag.
* testsuite/gas/mips/xpa.d: Remove `xpa' from `-M' in `objdump'
flags. Add `-mvirt' to `as' flags.
* testsuite/gas/mips/xpa-err.d: New test.
* testsuite/gas/mips/xpa-virt-err.d: New test.
* testsuite/gas/mips/xpa-err.l: New stderr output.
* testsuite/gas/mips/xpa-virt-err.l: New stderr output.
* testsuite/gas/mips/xpa-err.s: New test source.
* testsuite/gas/mips/xpa-virt-err.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
binutils/
* testsuite/binutils-all/mips/mips-xpa-virt-1.d: New test.
* testsuite/binutils-all/mips/mips-xpa-virt-2.d: New test.
* testsuite/binutils-all/mips/mips-xpa-virt-3.d: New test.
* testsuite/binutils-all/mips/mips-xpa-virt-4.d: New test.
* testsuite/binutils-all/mips/mips-xpa-virt.s: New test source.
* testsuite/binutils-all/mips/mips.exp: Run the new tests.
Correct a commit 25499ac7ee ("MIPS16e2: Add MIPS16e2 ASE support")
disassembler bug with the handling of the ASE_MIPS16E2_MT combination
ASE flag, where the calculation uses MIPS ABI Flags directly rather than
calculated internal ASE flags. Consequently code does not correctly set
the ASE_MIPS16E2_MT flag when the MIPS16e2 ASE flag and the MT ASE flag
come from different sources, i.e. one from the BFD chosen and the other
one from MIPS ABI Flags.
Fix this by using internal ASE_MT and ASE_MIPS16E2 flags in a separate
subsequent step, factored out to a dedicated function for use with
future combination ASE flags. Adjust the `mips16e2@mips16e2-mt-sub.d'
test case accordingly, where the MT flag comes from the BFD selected for
the disassembler and the MIPS16e2 flag comes from the ELF binary itself.
opcodes/
* mips-dis.c (mips_calculate_combination_ases): New function.
(mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
calculation to the new function.
(set_default_mips_dis_options): Call the new function.
gas/
* testsuite/gas/mips/mips16e2@mips16e2-mt-sub.d: Adjust for the
ASE_MIPS16E2_MT flag disassembler fix.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e2-mt-sub.d:
Likewise.
This patch updates arc-dis.c:parse_disassembler_options to use a macro
FOR_EACH_DISASSEMBLER_OPTION, which has been introduced in [1], instead of a
homegrown solution to split option string.
[1] https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=65b48a81
opcodes/ChangeLog:
yyyy-mm-dd Anton Kolesov <Anton.Kolesov@synopsys.com>
* arc-dis.c (parse_disassembler_options): Use
FOR_EACH_DISASSEMBLER_OPTION.
There is a bug in handling of cpu=... disassembler option in case there are
other options after it, for example, `cpu=EM,dsp'. In this case `EM,dsp' is
treated as an option value, and strcasecmp reports is as non-equal to "EM".
This is fixed by using disassembler_options_cmp function, which compares string
treating `,' the same way as `\0'.
This function also solves a problem with option order in parse_option.
Previously, if several option had same prefix (e.g. fpud, fpuda), then the
longer one should have been compared first, otherwise when longer option is
passed it would be treated as a short one, because
CONST_STRNEQ ("fpud", "fpuda")
would be true. The order of options was correct for ARC, so there were no
bugs per se, but with disassembler_option_cmp there is no risk of such a bug
being introduced in the future.
opcodes/ChangeLog:
yyyy-mm-dd Anton Kolesov <Anton.Kolesov@synopsys.com>
* arc-dis.c (parse_option): Use disassembler_options_cmp to compare
disassembler option strings.
(parse_cpu_option): Likewise.
binutils/ChangeLog
yyyy-mm-dd Anton Kolesov <Anton.Kolesov@synopsys.com>
* testsuite/binutils-all/arc/double_store.s: New file.
* testsuite/binutils-all/arc/objdump.exp: Tests for disassembler
options.
(do_objfile): New function.
(check_assembly): Likewise.
This patch add assembler and disassembler support for new Dot Product
Extension.
The support can be enabled through the new "+dotprod" extension.
include/
* opcode/arm.h (FPU_NEON_EXT_DOTPROD): New macro.
(FPU_ARCH_DOTPROD_NEON_VFP_ARMV8): New macro.
gas/
* config/tc-arm.c (fpu_neon_ext_dotprod): New variable.
(neon_scalar_for_mul): Improve comments.
(do_neon_dotproduct): New function to encode Dot Product instructions.
(do_neon_dotproduct_s): Wrapper function for signed Dot Product
instructions.
(do_neon_dotproduct_u): Wrapper function for unsigned Dot Product
instructions.
(insns): New entries for vsdot and vudot.
(arm_extensions): New entry for "dotprod".
* doc/c-arm.texi: Document new "dotprod" extension.
* testsuite/gas/arm/dotprod.s: New test source.
* testsuite/gas/arm/dotprod-illegal.s: New test source.
* testsuite/gas/arm/dotprod.d: New test.
* testsuite/gas/arm/dotprod-thumb2.d: New test.
* testsuite/gas/arm/dotprod-illegal.d: New test.
* testsuite/gas/arm/dotprod-legacy-arch.d: New test.
* testsuite/gas/arm/dotprod-illegal.l: New error file.
* testsuite/gas/arm/dotprod-legacy-arch.l: New error file.
opcodes/
* arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
Add support for the Imagination interAptiv MR2 MIPS32r3 processor with
the MIPS16e2 ASE as per documentation, including in particular:
1. Support for implementation-specific interAptiv MR2 COPYW and UCOPYW
MIPS16e2 instructions[1], for assembly and disassembly,
2. Support for implementation-specific interAptiv MR2 SAVE and RESTORE
regular MIPS instructions[2], for assembly and disassembly,
3. ELF binary file annotation for the interAptiv MR2 MIPS architecture
extension.
4. Support for interAptiv MR2 architecture selection for assembly, in
the form of the `-march=interaptiv-mr2' command-line option and its
corresponding `arch=interaptiv-mr2' setting for the `.set' and
`.module' pseudo-ops.
5. Support for interAptiv MR2 architecture selection for disassembly,
in the form of the `mips:interaptiv-mr2' target architecture, for
use e.g. with the `-m' command-line option for `objdump'.
Parts of this change by Matthew Fortune and Andrew Bennett.
References:
[1] "MIPS32 interAptiv Multiprocessing System Software User's Manual",
Imagination Technologies Ltd., Document Number: MD00904, Revision
02.01, June 15, 2016, Section 24.3 "MIPS16e2 Implementation Specific
Instructions", pp. 878-883
[2] same, Chapter 25 "Implementation-specific Instructions", pp. 911-917
include/
* elf/mips.h (E_MIPS_MACH_IAMR2): New macro.
(AFL_EXT_INTERAPTIV_MR2): Likewise.
* opcode/mips.h: Document new operand codes defined.
(INSN_INTERAPTIV_MR2): New macro.
(INSN_CHIP_MASK): Adjust accordingly.
(CPU_INTERAPTIV_MR2): New macro.
(cpu_is_member) <CPU_INTERAPTIV_MR2>: New case.
(MIPS16_ALL_ARGS): Rename to...
(MIPS_SVRS_ALL_ARGS): ... this.
(MIPS16_ALL_STATICS): Rename to...
(MIPS_SVRS_ALL_STATICS): ... this.
bfd/
* archures.c (bfd_mach_mips_interaptiv_mr2): New macro.
* cpu-mips.c (I_interaptiv_mr2): New enum value.
(arch_info_struct): Add "mips:interaptiv-mr2" entry.
* elfxx-mips.c (_bfd_elf_mips_mach) <E_MIPS_MACH_IAMR2>: New
case.
(mips_set_isa_flags) <bfd_mach_mips_interaptiv_mr2>: Likewise.
(bfd_mips_isa_ext) <bfd_mach_mips_interaptiv_mr2>: Likewise.
(print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise.
(mips_mach_extensions): Add `bfd_mach_mipsisa32r3' and
`bfd_mach_mips_interaptiv_mr2' entries.
* bfd-in2.h: Regenerate.
opcodes/
* mips-formats.h (INT_BIAS): New macro.
(INT_ADJ): Redefine in INT_BIAS terms.
* mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
(mips_print_save_restore): New function.
(print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
(validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
call.
(print_insn_args): Handle OP_SAVE_RESTORE_LIST.
(print_mips16_insn_arg): Call `mips_print_save_restore' for
OP_SAVE_RESTORE_LIST handling, factored out from here.
* mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
(RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
(mips_builtin_opcodes): Add "restore" and "save" entries.
* mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
(IAMR2): New macro.
(mips16_opcodes): Add "copyw" and "ucopyw" entries.
binutils/
* readelf.c (get_machine_flags) <E_MIPS_MACH_IAMR2>: New case.
(print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise.
* NEWS: Mention Imagination interAptiv MR2 processor support.
gas/
* config/tc-mips.c (validate_mips_insn): Handle
OP_SAVE_RESTORE_LIST specially.
(mips_encode_save_restore, mips16_encode_save_restore): New
functions.
(match_save_restore_list_operand): Factor out SAVE/RESTORE
operand insertion into the instruction word or halfword to these
new functions.
(mips_cpu_info_table): Add "interaptiv-mr2" entry.
* doc/c-mips.texi (MIPS Options): Add `interaptiv-mr2' to the
`-march=' argument list.
2017-06-23 Andrew Waterman <andrew@sifive.com>
* riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
alias; do not mark SLTI instruction as an alias.
Update x86 assembler and disassembler for CET v2.0:
https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf
1. incsspd and incsspq are changed to take a register opeand with a
different opcode.
2. setssbsy is changed to take no opeand with a different opcode.
gas/
* testsuite/gas/i386/cet-intel.d: Updated.
* testsuite/gas/i386/cet.d: Likewise.
* testsuite/gas/i386/x86-64-cet-intel.d: Likewise.
* testsuite/gas/i386/x86-64-cet.d: Likewise.
* testsuite/gas/i386/cet.s: Update incsspd and setssbsy tests.
* testsuite/gas/i386/x86-64-cet.s: Likewise.
opcodes/
* i386-dis.c (RM_0FAE_REG_5): Removed.
(PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
(PREFIX_MOD_3_0F01_REG_5_RM_0): New.
(PREFIX_MOD_3_0FAE_REG_5): Likewise.
(prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
PREFIX_MOD_3_0F01_REG_5_RM_0.
(prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
PREFIX_MOD_3_0FAE_REG_5.
(mod_table): Update MOD_0FAE_REG_5.
(rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
* i386-opc.tbl: Update incsspd, incsspq and setssbsy.
* i386-tbl.h: Regenerated.
Since there are only 4 bnd registers, return "(bad)" for register
number > 3.
PR binutils/21594
* i386-dis.c (OP_E_register): Check valid bnd register.
(OP_G): Likewise.
PR binutils/21588
* rl78-decode.opc (OP_BUF_LEN): Define.
(GETBYTE): Check for the index exceeding OP_BUF_LEN.
(rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
array.
* rl78-decode.c: Regenerate.
This is a follow-up to
[PATCH 0/6] Unify the disassembler selection in gdb and objdump
https://sourceware.org/ml/binutils/2017-05/msg00192.html
that is, opcodes is able to select the right disassembler, so gdb
doesn't have to select them. Instead, gdb can just use
default_print_insn. As a result, these print_insn_XXX are not used
out of opcodes, so this patch also moves their declarations from
include/dis-asm.h to opcodes/disassemble.h. With this change,
GDB doesn't use any print_insn_XXX directly any more.
gdb:
2017-06-14 Yao Qi <yao.qi@linaro.org>
* aarch64-tdep.c (aarch64_gdb_print_insn): Call
default_print_insn instead of print_insn_aarch64.
* arm-tdep.c (gdb_print_insn_arm): Call
default_print_insn instead of print_insn_big_arm
and print_insn_little_arm.
* i386-tdep.c (i386_print_insn): Call default_print_insn
instead of print_insn_i386.
* ia64-tdep.c (ia64_print_insn): Call
default_print_insn instead of print_insn_ia64.
* mips-tdep.c (gdb_print_insn_mips): Call
default_print_insn instead of print_insn_big_mips
and print_insn_little_mips.
* spu-tdep.c (gdb_print_insn_spu): Call default_print_insn
instead of print_insn_spu.
include:
2017-06-14 Yao Qi <yao.qi@linaro.org>
* dis-asm.h (print_insn_aarch64): Move it to opcodes/disassemble.h.
(print_insn_big_arm, print_insn_big_mips): Likewise.
(print_insn_i386, print_insn_ia64): Likewise.
(print_insn_little_arm, print_insn_little_mips): Likewise.
(print_insn_spu): Likewise.
opcodes:
2017-06-14 Yao Qi <yao.qi@linaro.org>
* aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
* arm-dis.c: Likewise.
* ia64-dis.c: Likewise.
* mips-dis.c: Likewise.
* spu-dis.c: Likewise.
* disassemble.h (print_insn_aarch64): New declaration, moved from
include/dis-asm.h.
(print_insn_big_arm, print_insn_big_mips): Likewise.
(print_insn_i386, print_insn_ia64): Likewise.
(print_insn_little_arm, print_insn_little_mips): Likewise.
PR binutils/21587
* rx-decode.opc: Include libiberty.h
(GET_SCALE): New macro - validates access to SCALE array.
(GET_PSCALE): New macro - validates access to PSCALE array.
(DIs, SIs, S2Is, rx_disp): Use new macros.
* rx-decode.c: Regenerate.
Later CPU generations added optional operands to the ipte/idte
instructions. I've added these with:
https://sourceware.org/ml/binutils/2017-05/msg00316.html ... but
supported the optional operands only with the specific hardware
levels. However, it is more useful to have the optional operands
already in the first versions. Of course they need to be zero there.
Regression-tested with on s390 and s390x. Committed to mainline.
Bye,
-Andreas-
opcodes/ChangeLog:
2017-06-01 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-opc.txt: Support the optional parameters with the first
versions of ipte/idte.
gas/ChangeLog:
2017-06-01 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* testsuite/gas/s390/esa-g5.d: Add ipte tests.
* testsuite/gas/s390/esa-g5.s: Likewise.
* testsuite/gas/s390/zarch-z196.d: Remove ipte tests.
* testsuite/gas/s390/zarch-z196.s: Likewise.
* testsuite/gas/s390/zarch-z990.d: Add idte tests.
* testsuite/gas/s390/zarch-z990.s: Likewise.
* testsuite/gas/s390/zarch-zEC12.d: Remove ipte/idte tests.
* testsuite/gas/s390/zarch-zEC12.s: Likewise.
