* m68k-opc.c (m68k_opcodes): add b, w, or l specifier to coldfire
move insns to handle immediate operands.
From Andreas Schwab:
* m68k-opc.c (m68k_opcodes): Delete duplicate entry for "cmpil".
New macros for building vector instruction opcodes.
(tic80_opcodes): Remove all uses of FMT_SI, FMT_REG, and
FMT_LI, which were unused. The field is now a flags field.
Remove some opcodes that are possible, but illegal, such
as long immediate instructions with doubles for immediate
values. Add "vadd" and "vld" instructions.
(FMT_UNUSED, FMT_SI, FMT_LI, FMT_REG): Delete.
(TIC80_VECTOR): Define a flag bit for the flags. This one means
that the opcode can have two vector instructions in a single
32 bit word and we have to encode/decode both.
auxiliary_filters, and make it char **.
* lexsup.c (parse_args): Handle -f by setting up an array.
* emultempl/elf32.em (gld${EMULATION_NAME}_before_allocation): Use
new name of auxiliary_filters.
the order more logical. Move the shift alias instructions ("rotl",
"shl", "ins", "rotr", "extu", "exts", "srl", and "sra" to be
interspersed with the regular sr.x and sl.x instructions. Add
and test new instruction opcodes for "sl", "sli", "sr", "sri", "st",
"sub", "subu", "swcr", and "trap".
* mn10300-tdep.c: made a lot more generic, ripping out code
from copied target (no more mn10300_scan_prologue,
init_extra_frame_info, and mn10300_fix_call_dummy calls)
* config/mn10300/tm-mn10300.h: undefine INIT_EXTRA_FRAME_INFO
and INIT_FRAME_PC macros
as floats.
* tic80-opc.c (SPFI): Add single precision floating point
immediate operand type.
(ROTATE): Add rotate operand type for shifts.
(ENDMASK): Add for shifts.
(n): Macro for the 'n' bit.
(i): Macro for the 'i' bit.
(PD): Macro for the 'PD' field.
(P2): Macro for the 'P2' field.
(P1): Macro for the 'P1' field.
(tic80_operands): Add entries for "exts", "extu", "fadd",
"fcmp", and "fdiv".
FP_REGISTER_BYTES to compute offsets into the saved frame,
since it fails for SPARC targets configured without any
FP regs. Instead, use DUMMY_STACK_REG_BUF_SIZE.
--------------------------------------------------------------------
(labels, current_label): New static variables.
(md_assemble): Mark current_label as text, and clear it.
(m68k_frob_label): New function.
(m68k_flush_pending_output): New function.
(m68k_frob_symbol): New function.
* config/tc-m68k.h (tc_frob_label): Define.
(md_flush_pending_output): Define.
(tc_frob_symbol): Don't warn, just call m68k_frob_symbol.
(tc_frob_coff_symbol): Likewise.
PR 11417.
Use bfd_elf_generic_reloc as special function for all relocs.
(bfd_elf32_mn10200_reloc): Remove unnecessary function.
Working on relocs for the mn10200.
(print_insn_tic80): If R_SCALED then print ":s" modifier for operand.
* tic80-opc.c (REG0, REG22, REG27, SSOFF, LSOFF): Names
changed to REG_0, REG_22, REG_DEST, OFF_SS, OFF_SL respectively.
(SICR, LICR, REGM_SI, REGM_LI): Names changed to CR_SI, CR_LI,
REG_BASE_M_SI, REG_BASE_M_LI respectively.
(REG_SCALED, LSI_SCALED): New operand types.
(E): New macro for 'E' bit at bit 27.
(tic80_opcodes): Add and test dld, dld.u, dst, estop, and etrap
opcodes, including the various size flavors (b,h,w,d) for
the direct load and store instructions.
in an instruction.
* tic80-dis.c (print_insn_tic80): Change comma and paren handling.
Use M_SI and M_LI macros to check for ":m" modifier for GPR operands.
* tic80-opc.c (tic80_operands): Add REGM_SI and REGM_LI operands.
(F, M_REG, M_LI, M_SI, SZ_REG, SZ_LI, SZ_SI, D, S): New bit-twiddlers.
(MASK_LI_M, MASK_SI_M, MASK_REG_M): Remove and replace in opcode
masks with "MASK_* & ~M_*" to get the M bit reset.
(tic80_opcodes): Add bsr, bsr.a, cmnd, cmp, dcachec, and dcachef.
