Commit Graph

82 Commits

Author SHA1 Message Date
Andrew Cagney
1e851d2c82 Fix a number of problems in the r5900 specific p* (parallel) instructions.
In particular a host endian dependency one fixed resolved most problems.
1997-07-11 03:07:29 +00:00
Jeff Law
6443523484 * gencode.c (build_instruction): Handle "pext5" according to
version 1.95 of the r5900 ISA.
Fixes pr12413 (c/h from toshiba).
1997-07-02 18:41:22 +00:00
Jeff Law
649625bb8e * gencode.c (build_instruction): Handle "ppac5" according to
version 1.95 of the r5900 ISA.
fixes pr12407 (c/h from toshiba).
1997-07-02 18:29:16 +00:00
Jeff Law
05d1322f2c * interp.c (sim_engine_run): Reset the ZERO register to zero
regardless of FEATURE_WARN_ZERO.
1997-07-02 18:13:00 +00:00
Jeff Law
ae19b07bf8 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
Fix for pr12402 (c/h from toshiba).
1997-07-02 17:57:56 +00:00
Andrew Cagney
56e7c84918 o Fixes to repeated watchpoints
o	Add mips ISA instructions needed to handle interrupts
1997-06-03 23:03:50 +00:00
Andrew Cagney
c7cebfa32c o Fix padd insn
o	Take an interrupt when an int event occures.
1997-06-02 15:00:43 +00:00
Andrew Cagney
2f2e6c5d5b Extend xor-endian and per-cpu support in core module.
Allow negated test when watching value within core.
1997-05-27 06:48:20 +00:00
Gavin Romig-Koch
d3d2a9f718 ifdef out uses of simSTOP, simSTEP and simBE when DEBUG is defined. 1997-05-22 13:30:01 +00:00
Andrew Cagney
50a2a69182 Watchpoint interface. 1997-05-21 06:54:13 +00:00
Andrew Cagney
2e61a3ad9c Graft sim/common event and other code onto the mips simulator. 1997-05-19 13:30:30 +00:00
David Edelsohn
3be0e22896 * tconfig.in (SIM_HAVE_BIENDIAN): Define. 1997-04-24 00:42:50 +00:00
Gavin Romig-Koch
d654ba0acf for DIV: check for div by zero and int overflow 1997-04-21 21:26:17 +00:00
David Edelsohn
9d52bcb7f0 * Makefile.in (SIM_OBJS): Add sim-load.o.
* interp.c: #include bfd.h.
	(target_byte_order): Delete.
	(sim_kind, myname, big_endian_p): New static locals.
	(sim_open): Set sim_kind, myname.  Move call to set_endianness to
	after argument parsing.  Recognize -E arg, set endianness accordingly.
	(sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
	load file into simulator.  Set PC from bfd.
	(sim_create_inferior): Return SIM_RC.  Delete arg start_address.
	(set_endianness): Use big_endian_p instead of target_byte_order.
1997-04-17 10:23:48 +00:00
Andrew Cagney
87e43259f1 Cleanups to compile under FreeBSD 1997-04-17 06:05:19 +00:00
Andrew Cagney
08db4a658e Get configure to define RETSIGTYPE 1997-04-07 05:58:59 +00:00
David Edelsohn
8a7c3105b5 * interp.c (sim_open): New arg `kind'. 1997-04-02 23:39:50 +00:00
David Edelsohn
fbda74b1c1 * aclocal.m4: Check for stdlib.h, string.h, strings.h, unistd.h.
(sim-debug): Allow arguments.  Define WITH_DEBUG in addition to
	-DDEBUG.
	* configure: Regenerated to track ../common/aclocal.m4 changes.
1997-04-02 23:17:50 +00:00
Andrew Cagney
a35e91c3c7 New file common/sim-config.c sets/checks simulator configuration options.
Update common/aclocal.m4 to better work with sim-config.[hc].
1997-04-02 05:04:25 +00:00
Gavin Romig-Koch
6efa34d87a Add/use pr_uword64 for SIM_ADDR independent values. 1997-03-17 16:02:13 +00:00
Andrew Cagney
a77aa7ec4b * configure: Re-generate.
* Make-common.in (CSEARCH): Do not include the gdb directory in
        the search path.
        * Make-common.in (SIM_ENDIAN, SIM_HOSTENDIAN, SIM_INLINE,
        SIM_WARNING): Drop, requiring the simulator specific Makefile.in
        to explicitly incorporate these.

        * aclocal.m4 (--enable-sim-alignment); New option. Strongly
        specify the alignment restrictions of the target architecture -
        without this option all alignment restrictions are accomodated.
        (--enable-sim-assert): New option.  Conditionally compile in
        assertion statements.
        (--enable-sim-float): New option. Strongly specify the target's
        floating point support.
        (--enable-sim-hardware): New option.  Specify the hardware devices
        included in the simulation.
        (--enable-sim-packages): New option.  Specify the hardware
        packages included in the simulation.
        (--enable-sim-regparm): New option.  Specify that parameters be
        passed in registers instead of on the stack.
        (--enable-sim-reserved-bits): New option. Specify that reserved
        bits within an instruction are are correctly set.
        (--enable-sim-smp): New option. Specify the level of SMP support
        to be included in the simulator.
        (--enable-sim-stdcall): New option.  Specify an alternative
        function call convention.
        (--enable-sim-xor-endian): New option.  Configure xor-endian
        support used by some targets to implement bi-endian support.
1997-03-17 15:29:29 +00:00
Michael Meissner
601fb8aea6 Regenerate simulator configure scripts; Remove d10v traps 1-3, Make 15 the system call trap, keeping 0 temporarily 1997-03-14 16:21:57 +00:00
David Edelsohn
53b9417eb3 * interp.c (sim_open): New SIM_DESC result. Argument is now
in argv form.
	(other sim_*): New SIM_DESC argument.
1997-03-13 20:55:26 +00:00
Gavin Romig-Koch
c94db67a25 Correct the overloaded DOUBLEWORD problem 1997-02-26 23:49:19 +00:00
Dawn Perchik
4580503f2c start-sanitize-r5900
* gencode.c: #ifdef out offending code until a permanent fix
	can be added.  Code is causing build errors for non-5900 mips targets.
end-sanitize-r5900
1997-02-25 07:04:39 +00:00
Gavin Romig-Koch
528031fd49 Correct test for ISA dependent bits 1997-02-20 15:48:57 +00:00
Mark Alexander
7e05106dc8 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors. 1997-02-19 22:44:02 +00:00
Gavin Romig-Koch
2d18fbc668 Correct flags for PMADDUW insn 1997-02-18 22:15:04 +00:00
Ian Lance Taylor
bd2f63470e * gencode.c (build_mips16_operands): Correct computation of base
address for extended PC relative instruction.
1997-02-13 19:08:55 +00:00
Gavin Romig-Koch
276c2d7dc8 Add r5900 1997-02-11 13:26:34 +00:00
Ian Lance Taylor
da0bce9c27 * interp.c (mips16_entry): Add support for floating point cases.
(SignalException): Pass floating point cases to mips16_entry.
	(ValueFPR): Don't restrict fmt_single and fmt_word to even
	registers.
	(StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
	or fmt_word.
	(COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
	and then set the state to fmt_uninterpreted.
	(COP_SW): Temporarily set the state to fmt_word while calling
	ValueFPR.
1997-02-06 22:19:05 +00:00
Ian Lance Taylor
6389d8561c * gencode.c (build_instruction): The high order may be set in the
comparison flags at any ISA level, not just ISA 4.
1997-02-04 21:48:54 +00:00
David Edelsohn
19c5af72af * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
COMMON_{PRE,POST}_CONFIG_FRAG instead.
	* configure.in: sinclude ../common/aclocal.m4.
	* configure: Regenerated.
1997-02-04 21:42:27 +00:00
Ian Lance Taylor
736a306cb2 * configure: Rebuild after change to aclocal.m4. 1997-01-31 16:12:09 +00:00
Stu Grossman
ae0d7848d8 * ../common/aclocal.m4 (COMMON_MAKEFILE_FRAG): Quote a couple of $'s in
comments and single quotes.  Fixes a problem found on hpux.
1997-01-24 18:44:29 +00:00
Stu Grossman
a695143eae * configure: Remove targ-vals.def when doing distclean. (Change
is actually in ../common/aclocal.m4.)
1997-01-24 00:44:03 +00:00
Stu Grossman
2757866e9e * configure: Remove Make-common.in from dependencies. (Actually in
../common/aclocal.m4).
1997-01-24 00:04:57 +00:00
Stu Grossman
295dbbe44c * configure configure.in Makefile.in: Update to new configure
scheme which is more compatible with WinGDB builds.
	* configure.in:  Improve comment on how to run autoconf.
	* configure:  Re-run autoconf to get new ../common/aclocal.m4.
	* Makefile.in:  Use autoconf substitution to install common
	makefile fragment.
1997-01-23 22:09:52 +00:00
Jim Wilson
b99125bc1c For NEC 4300 project, fix last remaining host/target endianness problem
* gencode.c (build_instruction): Use BigEndianCPU instead of
	ByteSwapMem.
1997-01-08 20:40:40 +00:00
Mark Alexander
e1db0d47c5 * interp.c (sim_monitor): Make output to stdout visible in
wingdb's I/O log window.
1997-01-03 06:28:21 +00:00
Mark Alexander
2902e8ab51 * support.h: Undo previous change to SIGTRAP
and SIGQUIT values.
1996-12-31 15:05:46 +00:00
Ian Lance Taylor
7e6c297e82 * interp.c (store_word, load_word): New static functions.
(mips16_entry): New static function.
	(SignalException): Look for mips16 entry and exit instructions.
	(simulate): Use the correct index when setting fpr_state after
	doing a pending move.
1996-12-30 22:37:30 +00:00
Mark Alexander
0049ba7a8d * interp.c: Fix byte-swapping code throughout to work on
both little- and big-endian hosts.
1996-12-29 17:47:25 +00:00
Mark Alexander
2510786bd4 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
with gdb/config/i386/xm-windows.h.
1996-12-29 17:20:47 +00:00
Mark Alexander
39bf0ef4e6 * gencode.c (build_instruction): Work around MSVC++ code gen bug
that messes up arithmetic shifts.
1996-12-28 06:51:58 +00:00
Angela Marie Thomas
280f90e1a0 add flush_cache PMON routine 1996-12-25 06:14:26 +00:00
Stu Grossman
dbeec76839 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
SIGTRAP and SIGQUIT for _WIN32.
1996-12-20 19:05:28 +00:00
Ian Lance Taylor
deffd638b5 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
force a 64 bit multiplication.
	(build_instruction) [OR]: In mips16 mode, don't do anything if the
	destination register is 0, since that is the default mips16 nop
	instruction.
1996-12-19 19:08:46 +00:00
Ian Lance Taylor
063443cf01 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
(build_endian_shift): Don't check proc64.
	(build_instruction): Always set memval to uword64.  Cast op2 to
	uword64 when shifting it left in memory instructions.  Always use
	the same code for stores--don't special case proc64.
1996-12-16 21:47:23 +00:00
Ian Lance Taylor
aaff84371e * gencode.c (build_mips16_operands): Fix base PC value for PC
relative operands.
	(build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
	jal instruction.
	* interp.c (simJALDELAYSLOT): Define.
 	(JALDELAYSLOT): Define.
	(INDELAYSLOT, INJALDELAYSLOT): Define.
	(simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1996-12-16 20:01:15 +00:00