o When unpacking an r5900 FP value,
was not treating IEEE-NaN's as very
large values.
o When packing an r5900 FP result from an infinite
precision intermediate value was saturating
to IEEE-MAX instead of r5900-MAX
o The least significant bit of the FP status
register did not stick to one.
[ChangeLog]
Mon Apr 13 16:28:52 1998 Frank Ch. Eigler <fche@cygnus.com>
* interp.c (decode_coproc): Add proper 1000000 bit-string at top
of VU lower instruction.
VCALLMS-related were found/fixed.
[ChangeLog.sky]
* sky-vu.c ({read,write}_vu_special_reg): Add CMSAR[01] as special
registers for a VU. Behavior not as mandated.
({read,write}_vu_{misc,special}_reg): Create sim_io_error upon
access to unknown register. Behavior not as mandated.
* sky-vu.h (anonymous register numbering enum): Add CMSAR[01].
* sky-libvpe.c (indebug): Cache $ENV{'SKY_DEBUG'}.
[ChangeLog]
* Makefile.in (SIM_SKY_OBJS): Added sky-vudis.o.
* interp.c (decode_coproc): Refer to VU CIA as a "special"
register, not as a "misc" register. Aha. Add activity
assertions after VCALLMS* instructions.
work!
[ChangeLog.sky]
* sky-vu.h (vu_device): Represent "macro instruction just stuffed
into fetch buffer" condition with new "m" bit. Rename old "m" to
"l".
* sky-libvpe.c (indebug): Save snapshot of environment value;
workaround for suspected memory corruption.
(fetch_inst): Respect new "m" macro-instruction flag for reporting
successful fetch to caller.
(exec_inst): Disassemble instruction here instead of fetch time.
Renamed old "m" -> "l" flag in VU state to track interlock
release.
(vpecallms_cycle): Call exec_inst only if fetch_inst did some
work.
* sky-vu.c (vu_attach, vu[01]_device): Revamped initialization to
ensure complete clear of tail part of struct at attach time.
(vu0_busy): Fix thinko.
(vu0_macro_issue): Adapt to new "l" flag.
(vu0_micro_interlock_released): Ditto.
(write_vu_special_reg): Ditto.
(read_vu_special_reg): Compute VBS0/VBS1 bits more explicitly.
The other VU status bits are not yet computed.
[ChangeLog]
* interp.c (decode_coproc): Do not apply superfluous E (end) flag
to upper code of generated VU instruction.
masking facility for PATH3 transfers.
[ChangeLog.sky]
Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com>
* sky-libvpe.c (exec-inst): Added "M" bit detection for upper
instruction.
* sky-pke.c (pke_check_stall): Added more assertions.
(pke_code_mskpath3): Use new GPUIF M3P control register.
* sky-pke.h (VU[01]_CIA): New macros that give VU CIA
pseudo-register addresses.
* sky-vu.h (vu_device, VectorUnitState): Merged structs.
(VectorUnitState.mflag): New field.
(VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers.
* sky-vu.c (vu0_busy): New function.
(vu0_q_busy): New function.
(vu0_macro_issue): New function.
(vu0_micro_interlock_released): New function.
(vu0_busy_in_{micro,macro}_mode): Deleted stubs.
(vu0_macro_hazard_check): Deleted stubs.
(vu_attach): Adapted code to merged device & state struct.
(read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register.
[ChangeLog]
start-sanitize-sky
Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com>
* interp.c (*): Adapt code to merged VU device & state structs.
(decode_coproc): Execute COP2 each macroinstruction without
pipelining, by stepping VU to completion state. Adapted to
read_vu_*_reg style of register access.
* mips.igen ([SL]QC2): Removed these COP2 instructions.
* r5900.igen ([SL]QC2): Transplanted these COP2 instructions here.
* sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards.
end-sanitize-sky
into single PKE-style vu.[ch].
[ChangeLog]
Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com>
start-sanitize-sky
* Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o.
* interp.c (sim_{load,store}_register): Use new vu[01]_device
static to access VU registers.
(decode_coproc): Added skeleton of sky COP2 (VU) instruction
decoding. Work in progress.
* mips.igen (LDCzz, SDCzz): Removed *5900 case for this
overlapping/redundant bit pattern.
(LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in
progress.
* sim-main.h (status_CU[012]): Added COP[n]-enabled flags for
status register.
end-sanitize-sky
* interp.c (cop_lq, cop_sq): New functions for future 128-bit
access to coprocessor registers.
* sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above.
[ChangeLog.sky]
* sky-engine.c (engine_run): Adapted from vu[01] -> vu merge.
* sky-hardware.c (register_devices): Ditto
* sky-pke.c (pke_fifo_*): Made these functions private again, now
that the GPUIF code does not use them.
* sky-pke.h (pke_fifo_*): Removed newly private declarations.
* sky-vu.c (*): Major rework: merge of old sky-vu0.c and
sky-vu1.c. Management of two VU devices parallels two PKEs.
Work in progress.
* sky-vu.h (*): Other half of merge.
(vu_device): New struct, parallel to pke_device.
the stand-alone executable.
[in ChangeLog.sky:]
* sky-gpuif.c (call_gs): Call properly into GPU2 library if
configured --with-sim-gpu2. Use SKY_GPU2_REFRESH symbol as
placeholder for future GPU2-refresh policy.
[in ChangeLog:]
* Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
configurable settings for stand-alone simulator.
start-sanitize-sky
* configure.in: Added --with-sim-gpu2 option to specify path of
sky GPU2 library. Triggers -DSKY_GPU2 for sky-gpuif.c, and
links/compiles stand-alone simulator with this library.
* interp.c (MEM_SIZE): Increased default sky memory size to 16MB.
end-sanitize-sky
* configure.in: Added X11 search, just in case.
* configure: Regenerated.
* Makefile.in (vr4320.igen) : Added.
* configure.in (mips64vr4320-*-*): Added.
* configure : Rebuilt.
* mips.igen : Correct the bfd-names in the mips-ISA model entries.
Add the vr4320 model entry and mark the vr4320 insn as necessary.
little struct.
interp.c: Update. Also add floating point Max/Min functions.
mips.igen: Remove r5900 tag from any floating point instructions.
r5900.igen: Rewrite. Implement *all* floating point insns (except ld/st).
r5400.igen: Tag mdmx functions as being mdmx specific.
update v850, tic80 and mips simulators.
IGEN - Prepend prefix to more generated symbols and macros
(idecode_issue, instruction_word).
IGEN - Add -Wnowith option to supress warnings about word size
inflicts in input files.
MIPS - Clean up Makefile.in, m16.igen, m16.dc (new), m16run.c (new) so
that a mips16 simulator built using IGEN can be compiled.
Use the bfd-processor name in the sim-engine switch.
Add nr_cpus argument to sim_engine_run.
tic80, v850, d30v, mips, common:
Update
mips: Fill in bfd-processor field of model records so that
they match ../bfd/archures.
For sim/mips, enable multi-sim support when mips64vr5400-elf is target.
For sim/igen, allow specification of a default machine (will need
more work later).
(ANDI): Was missing mipsIV model, fix assembler syntax.
(do_c_cond_fmt): New function.
(C.cond.fmt): Handle mips I-III which do not support CC field
separatly.
(bc1): Handle mips IV which do not have a delaed FCC separatly.
(SDR): Mask paddr when BigEndianMem, not the converse as specified
in IV3.2 spec.
(DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
vr5000 which saves LO in a GPR separatly.
* configure.in (enable-sim-igen): For vr5000, select vr5000
specific instructions.
* configure: Re-generate.
MIPS simulator so that correctly writes the value of CIA back int PC
(the global previously used) when the simulation halts.
Fix implementation of DELAY_SLOT and NULLIFY_NEXT_INSTRUCTION macros.
calls) and sim_open so that they uses the virtual memory data transfer
functions sim_read & sim_write. This eliminates all code (other than
in load_memory & store_memory) that makes assumptions about the
implementation of the underlying memory model.
When address translation of insn fetch fails raise exception immediatly.
Use address_word as type of all address variables (instead of unsigned64),
the former is configured as either 32 or 64 bit type.
Always compile fpu code (no #if has fpu)
