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e407c74b5b
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2010 Commits

Author SHA1 Message Date
Nick Clifton
e407c74b5b * archures.c: Add support for MIPS r5900 
* bfd-in2.h: Add support for MIPS r5900
	* config.bfd: Add support for Sony Playstation 2
	* cpu-mips.c: Add support for MIPS r5900
	* elfxx-mips.c: Add support for MIPS r5900 (extension of r4000)

	* config/tc-mips.c: Add support for MIPS r5900
	Add M_LQ_AB and M_SQ_AB to support large values for instructions lq and sq.
	* config/tc-mips.c (can_swap_branch_p, get_append_method): Detect some conditional short loops to fix a bug on the r5900 by NOP in the branch delay slot.
	* config/tc-mips.c (M_MUL): Support 3 operands in multu on r5900.
	* config/tc-mips.c (M_TRUNCWS): Support trunc.w.s on r5900 in MIPS ISA I.
	* config/tc-mips.c (s_mipsset): Force 32 bit floating point on r5900.
	* configure.in: Detect CPU type when target string contains r5900 (e.g. mips64r5900el-linux-gnu).

	* config/tc-mips.c (mips_ip): Check parameter range of instructions mfps and mtps on r5900.

	* elf/mips.h: Add MIPS machine variant number for r5900 which is compatible with old Playstation 2 software.
	* opcode/mips.h: Add support for r5900 instructions including lq and sq.

	* configure.tgt: Support ELF files for Sony Playstation 2 (for ps2dev and ps2sdk).
	* emulparams/elf32lr5900n32.sh: Create linker script for Sony Playstation 2 ELF files using MIPS ABI n32.
	* emulparams/elf32lr5900.sh: Create linker script for Sony Playstation 2 ELF files using MIPS ABI o32.
	* Makefile.am: Add linker scripts for Sony Playstation 2 ELF files.

	* opcodes/mips-dis.c: Add names for CP0 registers of r5900.
	* opcodes/mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for instructions sq and lq.

	* opcodes/mips-opc.c: Add support for MIPS r5900 CPU.
	Add support for 128 bit MMI (Multimedia Instructions).
	Add support for EE instructions (Emotion Engine).
	Disable unsupported floating point instructions (64 bit and undefined compare operations).
	Enable instructions of MIPS ISA IV which are supported by r5900.
	Disable 64 bit co processor instructions.
	Disable 64 bit multiplication and division instructions.
	Disable instructions for co-processor 2 and 3, because these are not supported (preparation for later VU0 support (Vector Unit)).
	Disable cvt.w.s because this behaves like trunc.w.s and the correct execution can't be ensured on r5900.
	Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This will confuse less developers and compilers.
 2013-01-04 17:22:53 +00:00
Yufeng Zhang
fb098a1efc opcodes/ 
2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-opc.c (aarch64_print_operand): Change to print
	AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
	in comment.
	* aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
	from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
	OP_MOV_IMM_WIDE.

gas/testsuite/

2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>

	* gas/aarch64/int-insns.d: Update.
	* gas/aarch64/mov.d: Update.
	* gas/aarch64/reloc-insn.d: Update.

ld/testsuite/

2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>

	* ld-aarch64/emit-relocs-264.d: Append the '-Mno-aliases' option to
	the objdump directive.
	* ld-aarch64/emit-relocs-266.d: Ditto.
	* ld-aarch64/emit-relocs-268.d: Ditto.
	* ld-aarch64/emit-relocs-269.d: Ditto.
	* ld-aarch64/emit-relocs-270.d: Ditto.
	* ld-aarch64/emit-relocs-271.d: Ditto.
	* ld-aarch64/emit-relocs-272.d: Ditto.
 2013-01-04 14:59:33 +00:00
Nick Clifton
a32c3ff848 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP, 
PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.

        * gas/aarch64/system.d: Update.
 2013-01-04 13:32:06 +00:00
H.J. Lu
6265840747 Update copyright year to 2013 
binutils/

2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* version.c (print_version): Update copyright year to 2013.

gas/

2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* as.c (parse_args): Update copyright year to 2013.

ld/

2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* ldver.c (ldversion): Update copyright year to 2013.

opcodes/

2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (process_copyright): Update copyright year to 2013.
 2013-01-02 17:15:38 +00:00
Nick Clifton
bab4becb12 opcodes/ChangeLog 
* cr16-dis.c (match_opcode,make_instruction: Remove static declaration.
	(dwordU,wordU): Moved typedefs to opcode/cr16.h
	(cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'

bfd/Changelog
	* config.bfd (cr16*-*-uclinux*): New target support.

include/opcode/ChangeLog
	* cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
	(make_instruction,match_opcode): Added function prototypes.
	(cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
 2013-01-02 13:13:36 +00:00
Nick Clifton
5bf135a788 Add copyright notices 2012-12-17 16:56:12 +00:00
Alan Modra
943d398f4c PR binutils/14950 
* ppc-opc.c (insert_sci8, extract_sci8): Rewrite.
	(insert_sci8n, extract_sci8n): Likewise.
 2012-12-13 07:46:13 +00:00
Nick Clifton
752937aa0c Add copyright notices 2012-12-10 12:48:03 +00:00
Joern Rennecke
02a79b89fd 2012-11-30 Oleg Raikhman <oleg@adapteva.com> 
Joern Rennecke  <joern.rennecke@embecosm.com>

cpu:
        * epiphany.cpu (keyword gr-names): Move sb/sl/ip after r9/r10/r12.
        (load_insn): Add NO-DIS attribute to x, p, d, dpm, dl0, dl0.l.
        (testset-insn): Add NO_DIS attribute to t.l.
        (store-insn): Add NO-DIS attribute to x.l, p.l, d.l, dpm.l, dl0.l.
        (move-insns): Add NO-DIS attribute to cmov.l.
        (op-mmr-movts): Add NO-DIS attribute to movts.l.
        (op-mmr-movfs): Add NO-DIS attribute to movfs.l.
        (op-rrr): Add NO-DIS attribute to .l.
        (shift-rrr): Add NO-DIS attribute to .l.
        (op-shift-rri): Add NO-DIS attribute to i32.l.
        (bitrl, movtl): Add NO-DIS attribute.
        (op-iextrrr): Add NO-DIS attribute to .l
        (op-two_operands-float, op-fabs-float): Add NO-DIS attribute to f32.l.
        (op-fix2float-float, op-float2fix-float, op-fextop-float): Likewise.

opcodes:
        * epiphany-desc.c, epiphany-desc.h, epiphany-opc.c: Regenerate.
 2012-11-30 17:54:58 +00:00
Roland McGrath
cdaaa29dd6 opcodes/ 
* s390-mkopc.c (file_header): Add const.
 2012-11-29 23:42:03 +00:00
Michael Eager
94dda8b768 opcodes/Changelog: 
* microblaze-opc.h: Rename INST_TYPE_RD_R1_SPECIAL to
	INST_TYPE_R1_R2_SPECIAL
	* microblaze-dis.c (print_insn_microblaze): Same.
gas/Changelog
	* gas/config/tc-microblaze.c: Rename INST_TYPE_RD_R1_SPECIAL to
	INST_TYPE_R1_R2_SPECIAL, don't set RD for wic.
 2012-11-29 21:09:01 +00:00
Alan Modra
776fc41826 include/opcode/ 
* ppc.h (ppc_parse_cpu): Update prototype.
opcodes/
	* ppc-dis.c (ppc_parse_cpu): Add "sticky" param.  Track bits
	set from ppc_opts.sticky in it.  Delete "retain_mask".
	(powerpc_init_dialect): Choose default dialect from info->mach
	before parsing -M options.  Handle more bfd_mach_ppc variants.
	Update common default to power7.
gas/
	* config/tc-ppc.c (sticky): New var.
	(md_parse_option, ppc_machine): Update ppc_parse_cpu calls.
gas/testsuite/
	* gas/ppc/astest2.d: Pass -Mppc to objdump.
ld/testsuite/
	* ld-powerpc/plt1.d: Update for default "at" branch hints.
	* ld-powerpc/tlsexe.d: Likewise.
	* ld-powerpc/tlsexetoc.d: Likewise.
	* ld-powerpc/tlsopt1.d: Likewise.
	* ld-powerpc/tlsopt1_32.d: Likewise.
	* ld-powerpc/tlsopt2.d: Likewise.
	* ld-powerpc/tlsopt2_32.d: Likewise.
	* ld-powerpc/tlsopt4.d: Likewise.
	* ld-powerpc/tlsopt4_32.d: Likewise.
	* ld-powerpc/tlsso.d: Likewise.
	* ld-powerpc/tlstocso.d: Likewise.
 2012-11-23 03:28:13 +00:00
Michael Eager
abe9f67d45 Add swap byte (swapb) and swap halfword (swaph) opcodes. 
binutils/opcodes
          * microblaze-opc.h (op_code_struct): Add swapb, swaph Increase MAX_OPCODES.
          * microblaze-opcm.h (microblaze_instr): Likewise
binutils/gas/testsuite
          * gas/microblaze/allinsn.s: Add swapb, swaph
          * gas/microblaze/allinsn.d: Likewise
 2012-11-21 17:54:11 +00:00
Michael Eager
0db4b3260c Add stack high register and stack low register for MicroBlaze 
hardware assisted stack protection, stores stack low / stack high limits
for detecting stack overflow / underflow

binutils/opcodes
          * microblaze-opcm.h: Add REG_SLR_MASK, REG_SHR_MASK, REG_SHR and REG_SLR
          * microblaze-dis.c (get_field_special): Handle REG_SLR_MASK and REG_SHR_MASK
binutils/gas
          * config/tc-microblaze.c (parse_reg): Parse REG_SLR, REG_SHR
binutils/gas
          * gas/microblaze/allinsn.s: Test use of SHR, SLR
          * gas/microblaze/allinsn.d: Likewise
 2012-11-21 17:34:14 +00:00
H.J. Lu
9b30cccca9 Fix opcode for 64-bit jecxz 
gas/testsuite/

	PR gas/14859
	* gas/i386/x86-64-opcode.s: Add jecxz.
	* gas/i386/x86-64-opcode.d: Updated.

opcodes/

	PR gas/14859
	* i386-opc.tbl: Fix opcode for 64-bit jecxz.
	* i386-tbl.h: Regenerated.
 2012-11-20 14:21:33 +00:00
Andreas Krebbel
0b7fe784ac 2012-11-20 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> 
* s390-opc.txt: Fix srstu and strag opcodes.

2012-11-20  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>

	* gas/s390/zarch-z9-109.d: Fix srstu opcode.
	* gas/s390/zarch-z900.d: Replace lasp with strag.
 2012-11-20 11:58:30 +00:00
Michael Eager
d3da77419a opcodes/ 
* microblaze-opc.h: Define new instruction type INST_TYPE_IMM5,
	update OPCODE_MASK_H13S, add OPCODE_MASK_HN, define MIN_IMM5 / MAX_IMM5,
	and increase MAX_OPCODES.
	(op_code_struct):  add mbar and sleep
	* microblaze-opcm.h (microblaze_instr): add mbar
	Define IMM_MBAR and IMM5_MBAR_MASK
	* microblaze-dis.c: Add get_field_imm5_mbar
	(print_insn_microblaze): Add support for INST_TYPE_IMM5 and INST_TYPE_NONE

gas/
	* config/tc-microblaze.c (md_assemble): Add support for INST_TYPE_IMM5

gas/testsuite/
	* gas/microblaze/allinsn.s: Add mbar and sleep
	* gas/microblaze/allinsn.d: Likewise
 2012-11-14 17:05:24 +00:00
Michael Eager
ed8ec0ec78 Add clz opcode. 
opcodes/
	* microblaze-opc.h: Increase MAX_OPCODES (op_code_struct):  add clz insn
	* microblaze-opcm.h (microblaze_instr): add clz

gas/testsuite/
	* gas/microblaze/allinsn.s: Add clz insn
	* gas/microblaze/allinsn.d: Likewise
 2012-11-14 16:45:01 +00:00
Michael Eager
e692c2171e Add the endian reversing versions of load/store instructions; 
2012-11-14  Edgar E. Iglesias <edgar.iglesias@gmail.com>

	* microblaze-opc.h: Increase MAX_OPCODES (op_code_struct):  add lbur,
	lhur, lwr, sbr, shr, swr
	* microblaze-opcm.h (microblaze_instr): add lbur, lhur, lwr, sbr, shr,
	swr

2012-11-14  David Holsgrove  <david.holsgrove@xilinx.com>

	* gas/microblaze/allinsn.exp: New file - test newly added opcodes
	* gas/microblaze/allinsn.s: Likewise
	* gas/microblaze/allinsn.d: Likewise
 2012-11-14 16:19:30 +00:00
Nick Clifton
de863c7475 2012-11-09 Nick Clifton <nickc@redhat.com> 
* Makefile.am (ALL_MACHINES): Add cpu-v850-rh850.lo.
	(ALL_MACHINES_CFILES): Add cpu-v850-rh850.c.
	* archures.c (bfd_arch_info): Add bfd_v850_rh850_arch.
	* config.bfd: Likewise.
	* configure.in: Add bfd_elf32_v850_rh850_vec.
	* cpu-v850.c: Update printed description.
	* cpu-v850_rh850.c: New file.
	* elf32-v850.c (v850_elf_check_relocs): Add support for RH850 ABI
	relocs.
	(v850_elf_perform_relocation): Likewise.
	(v850_elf_final_link_relocate): Likewise.
	(v850_elf_relocate_section): Likewise.
	(v850_elf_relax_section): Likewise.
	(v800_elf_howto_table): New.
	(v850_elf_object_p): Add support for RH850 ABI values.
	(v850_elf_final_write_processing): Likewise.
	(v850_elf_merge_private_bfd_data): Likewise.
	(v850_elf_print_private_bfd_data): Likewise.
	(v800_elf_reloc_map): New.
	(v800_elf_reloc_type_lookup): New.
	(v800_elf_reloc_name_lookup): New.
	(v800_elf_info_to_howto): New.
	(bfd_elf32_v850_rh850_vec): New.
	(bfd_arch_v850_rh850): New.
	* targets.c (_bfd_targets): Add bfd_elf32_v850_rh850_vec.
	* Makefile.in: Regenerate.
	* bfd-in2.h: Regenerate.
	* configure: Regenerate.

	* readelf.c (get_machine_flags): Add support for E_FLAG_RX_ABI.
	(guess_is_rela): Add EM_V800.
	(dump_relocations): Likewise.
	(get_machine_name): Update EM_V800.
	(get_machine_flags): Add support for RH850 ABI flags.
	(is_32bit_abs_reloc): Add support for RH850 ABI reloc.

	* config/tc-v850.c (v850_target_arch): New.
	(v850_target_format): New.
	(set_machine): Use v850_target_arch.
	(md_begin): Likewise.
	(md_show_usage): Document new switches.
	(md_parse_option): Add -mgcc-abi, -mrh850-abi, -m8byte-align and
	-m4byte-align.
	* config/tc-v850.c (TARGET_ARCH) Use v850_target_arch.
	(TARGET_FORMAT): Use v850_target_format.
	* doc/c-v850.texi: Document new options.

	* v850.h: Add RH850 ABI values.

	* Makefile.am: (ALL_EMULATION_SOURCES): Add ev850_rh850.c.
	* Makefile.in: Regenerate.
	* configure.tgt (v850*-*-*): Make v850_rh850 the default
	emulation. Add vanilla v850 as an extra emulation.
	* emulparams/v850_rh850.sh: New file.
	* scripttempl/v850_rh850.sc: New file.

	* configure.in: Add bfd_v850_rh850_arch.
	* configure: Regenerate.
	* disassemble.c (disassembler): Likewise.
 2012-11-09 17:36:19 +00:00
H.J. Lu
5bb3703f01 Remove trailing redundant `;' 
bfd/

	* aout-tic30.c (MY_final_link_callback): Remove trailing
	redundant `;'.
	* coff-h8500.c (extra_case): Likewise.
	(bfd_coff_reloc16_get_value): Likewise.
	* dwarf2.c (_bfd_dwarf2_cleanup_debug_info): Likewise.
	* elf.c (_bfd_elf_slurp_version_tables): Likewise.
	* elf32-frv.c (elf32_frv_relocate_section): Likewise.
	* elf32-v850.c (v850_elf_perform_relocation): Likewise.
	* opncls.c (bfd_calc_gnu_debuglink_crc32): Likewise.
	* plugin.c (add_symbols): Likewise.
	* reloc.c (bfd_check_overflow): Likewise.
	* vms-lib.c (_bfd_vms_lib_archive_p): Likewise.

binutils/

	* coffgrok.c (coff_grok): Remove trailing redundant `;'.
	* resrc.c (open_input_stream): Likewise.

gas/

	* config/atof-ieee.c (gen_to_words): Remove trailing redundant
	`;'.
	* config/atof-vax.c (flonum_gen2vax): Likewise.
	* config/tc-d10v.c (write_2_short): Likewise.
	* config/tc-i386-intel.c (i386_intel_simplify): Likewise.
	* config/tc-s390.c (tc_s390_force_relocation): Likewise.
	* config/tc-v850.c (md_parse_option): Likewise.
	* config/tc-xtensa.c (find_address_of_next_align_frag): Likewise.
	* dwarf2dbg.c (out_header): Likewise.
	* symbols.c (dollar_label_name): Likewise.
	(fb_label_name): Likewise.

ld/

	* testplug.c (record_add_file): Remove trailing redundant `;'.

opcodes/

	* aarch64-opc.h (gen_mask): Remove trailing redundant `;'.
	* ia64-gen.c (fetch_insn_class): Likewise.
 2012-11-09 08:29:34 +00:00
Alan Modra
6febeb7413 Regenerate. 2012-11-08 03:03:26 +00:00
Alan Modra
d17dce5567 * configure.in: Apply 2012-09-10 change to config.in here. 2012-11-05 10:45:32 +00:00
Andreas Krebbel
aac129d776 2012-10-26 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> 
* s390-mkopc.c: Accept empty lines in s390-opc.txt.
	* s390-opc.c: Add M_20OPT field. New instruction formats RRF_RURR2 and RRF_RMRR.
	* s390-opc.txt: Add new instructions.  New instruction type for lptea.

2012-10-26  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>

	* gas/testsuite/gas/s390/zarch-z10.d: Refreshed.
	* gas/testsuite/gas/s390/zarch-z10.s: Refreshed.
	* gas/testsuite/gas/s390/zarch-z196.d: Refreshed.
	* gas/testsuite/gas/s390/zarch-z196.s: Refreshed.
	* gas/testsuite/gas/s390/zarch-z9-109.d: Refreshed.
	* gas/testsuite/gas/s390/zarch-z990.d: Refreshed.
	* gas/testsuite/gas/s390/zarch-z990.s: Refreshed.
	* gas/testsuite/gas/s390/zarch-zEC12.d: Refreshed.
	* gas/testsuite/gas/s390/zarch-zEC12.s: Refreshed.
 2012-10-26 09:41:55 +00:00
Christian Groessler
747a4ac1f4 gas/testsuite: 
* gas/z8k/z8k.exp: Run translate-ops test.
        * gas/z8k/translate-ops.s: New file.
        * gas/z8k/translate-ops.d: New file.

opcodes:

        * z8kgen.c (struct op): Fix encoding for translate opcodes (trdb,
        trdrb, trib, trirb, trtdb, trtdrb, trtib, trtirb).  Remove
        non-existing opcode trtrb.
        * z8k-opc.h: Regenerate.
 2012-10-26 08:14:07 +00:00
Alan Modra
62082a42b9 * ppc-opc (powerpc_opcodes): "lfdp" and "stfdp" use DS offset. 2012-10-26 03:38:20 +00:00
Roland McGrath
6c067bbb1a gas/testsuite/ 
* gas/i386/rex.s: Add test of REX prefix before fsave (i.e. fwait).
	* gas/i386/rex.d: Update.

opcodes/
	* i386-dis.c (ckprefix): When bailing out for fwait with prefixes,
	set rex_used to rex.
 2012-10-24 21:41:33 +00:00
Peter Bergner
ab4437c322 opcodes/ 
* ppc-opc.c (powerpc_opcodes) <vcfpsxws>: Fix opcode spelling.

gas/testsuite/
	* gas/ppc/altivec.s <vcfpsxws>: Fix opcode spelling.
 2012-10-22 16:04:28 +00:00
Tom Tromey
9a176a4afc * tic54x-dis.c (print_instruction): Don't use K&R style. 
(print_parallel_instruction, sprint_dual_address)
	(sprint_indirect_address, sprint_direct_address, sprint_mmr)
	(sprint_cc2, sprint_condition): Likewise.
 2012-10-18 15:28:06 +00:00
Kai Tietz
4ad3b7ef02 * aarch64-asm.c (aarch64_ins_ldst_reglist): Initialize 
value with a default.
        (do_special_encoding): Likewise.
        (aarch64_ins_ldst_elemlist): Pre-initialize QSsize, and opcodeh2
        variables with default.
        * arc-dis.c (write_comments_): Don't use strncat due
        size of state->commentBuffer pointer isn't predictable.
 2012-10-18 06:53:16 +00:00
Yufeng Zhang
b7a54b5525 Updated the system register table. 
opcodes/

* aarch64-opc.c (aarch64_sys_regs): Add rmr_el1, rmr_el2 and
rmr_el3; remove daifset and daifclr.

gas/testsuite/

* gas/aarch64/sysreg-1.s: Add tests of rmr_el1, rmr_el2 and rmr_el3.
* gas/aarch64/sysreg-1.d: Update.
* gas/aarch64/illegal.s: Add tests of daifset and daifclr.
* gas/aarch64/illegal.d: Update.
 2012-10-15 15:07:49 +00:00
Yufeng Zhang
9b61754a3f Added the changelog for the previous commit. 2012-10-15 14:57:31 +00:00
Yufeng Zhang
9de794e148 Added missing alignment check to load/store uimm12 immediate offset. 
opcodes/

* aarch64-opc.c (operand_general_constraint_met_p): Change to check
the alignment of addr.offset.imm instead of that of shifter.amount for
operand type AARCH64_OPND_ADDR_UIMM12.

gas/testsuite/

* gas/aarch64/illegal-2.s: Add test case.
* gas/aarch64/illegal-2.l: Likewise.
 2012-10-15 14:52:06 +00:00
Richard Earnshaw
f8ece37fb1 2012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 
* arm-dis.c: Use preferred form of vrint instruction variants
	for disassembly.

2012-10-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* gas/arm/armv8-a+fp.d: Use preferred form of vrint instruction
	variants for disassembly.
	* gas/arm/armv8-a+fp.s: Likewise.
	* gas/arm/armv8-a+simd.d: Likewise.
	* gas/arm/armv8-a+simd.s: Likewise.
 2012-10-11 15:33:08 +00:00
Nagajyothi Eggone
5e5c50d37b Add AMD bdver3 support. 
gas/

	* config/tc-i386.c (cpu_arch): Add CPU_BDVER3_FLAGS.
	* doc/c-i386.texi: Add -march=bdver3 option.

gas/testsuite/

	* gas/i386/i386.exp: Run bdver3 test cases.
	* gas/i386/nops-1-bdver3.d: New.
	* gas/i386/arch-10-bdver3.d: New.
	* gas/i386/x86-64-nops-1-bdver3.d: New.
	* gas/i386/x86-64-arch-2-bdver3.d: New.

opcodes/

	* i386-gen.c (cpu_flag_init): Add CPU_BDVER3_FLAGS.
	* i386-init.h: Regenerated.
 2012-10-09 08:43:06 +00:00
Peter Bergner
c7a5aa9c64 opcodes/ 
* ppc-dis.c (ppc_opts) <altivec>: Use PPC_OPCODE_ALTIVEC2;
	* ppc-opc.c (VBA): New define.
	(powerpc_opcodes) <vcuxwfp, vcsxwfp, vcfpuxws, vcfpsxsw, vmr, vnot,
	mfppr, mfppr32, mtppr, mtppr32>: New extended mnemonics.

gas/testsuite/
	* gas/ppc/power7.d: Add tests for mfppr, mfppr32, mtppr and mtppr32.
	* gas/ppc/power7.s: Likewise.
	* gas/ppc/altivec.d: Add tests for all legacy Altivec instructions.
	* gas/ppc/altivec.s: Likewise.
	* gas/ppc/altivec2.d: New test file.
	* gas/ppc/altivec2.s: Likewise.
	* gas/ppc/ppc.exp: Run it.
 2012-10-05 14:06:20 +00:00
Nick Clifton
04ee5257d6 * v850-dis.c (disassemble): Place square parentheses around second 
register operand of clr1, not1, set1 and tst1 instructions.

	* config/tc-v850.c (v850_insert_operand): Use a static buffer for
	the error message.

	* gas/v850/v850e1.d: Fix expected disassembly of clr1, not1, set1
	and tst1 insns.
 2012-10-04 10:30:06 +00:00
Andreas Krebbel
cfc7277920 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> 
* config/tc-s390.c (s390_parse_cpu): Add new option zEC12.
	* doc/as.texinfo: Document new option zEC12.
	* doc/c-s390.texi: Likewise.

2012-10-04  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>

	* gas/s390/s390.exp: Run zEC12 tests.
	* gas/s390/zarch-zEC12.d: New file.
	* gas/s390/zarch-zEC12.s: New file.

2012-10-04  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>

	* s390-mkopc.c: Support new option zEC12.
	* s390-opc.c: Add new instruction formats.
	* s390-opc.txt: Add new instructions for zEC12.

2012-10-04  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>

	* s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
 2012-10-04 08:47:36 +00:00
Anthony Green
1415a2a767 Don't abort() when disassembling bad moxie instructions. 2012-09-28 03:53:39 +00:00
H.J. Lu
160a30bb92 Add missing Cpu flags in bd and bt cores 
gas/testsuite/

2012-09-25  Saravanan Ekanathan <saravanan.ekanathan@amd.com>

	* gas/i386/arch-10-bdver1.d: New file to test bdver1 core.
	* gas/i386/x86-64-arch-2-bdver1.d: Likewise.
	* gas/i386/i386.exp: Run bdver1 testcases.
	* gas/i386/arch-10-bdver2.d: Updated -march flags.
	* gas/i386/arch-10-btver1.d: Likewise.
	* gas/i386/arch-10-btver2.d: Likewise.
	* gas/i386/x86-64-arch-2-bdver2.d: Likewise.
	* gas/i386/x86-64-arch-2-btver1.d: Likewise.
	* gas/i386/x86-64-arch-2-btver2.d: Likewise.

opcodes/

2012-09-25  Saravanan Ekanathan <saravanan.ekanathan@amd.com>

	* gas/i386/arch-10-bdver1.d: New file to test bdver1 core.
	* gas/i386/x86-64-arch-2-bdver1.d: Likewise.
	* gas/i386/i386.exp: Run bdver1 testcases.
	* gas/i386/arch-10-bdver2.d: Updated -march flags.
	* gas/i386/arch-10-btver1.d: Likewise.
	* gas/i386/arch-10-btver2.d: Likewise.
	* gas/i386/x86-64-arch-2-bdver2.d: Likewise.
	* gas/i386/x86-64-arch-2-btver1.d: Likewise.
	* gas/i386/x86-64-arch-2-btver2.d: Likewise.
 2012-09-25 13:12:34 +00:00
H.J. Lu
60aa667ec4 Replace CpuSSE3 with CpuCX16 for cmpxchg16b 
gas/

	* config/tc-i386.c (cpu_arch): Add .cx16.
	* doc/c-i386.texi: Document .cx16.

gas/testsuite/

	* gas/i386/x86-64-arch-2.s: Add test for cmpxchg16b.
	* gas/i386/x86-64-arch-2.d: Update correspondingly.
	* gas/i386/x86-64-arch-2-bdver2.d: Likewise.
	* gas/i386/x86-64-arch-2-btver1.d: Likewise.
	* gas/i386/x86-64-arch-2-btver2.d: Likewise.
	* gas/i386/x86-64-arch-2-lzcnt.d: Likewise.
	* gas/i386/x86-64-arch-2-prefetchw.d: Likewise.
	* gas/i386/ilp32/x86-64-arch-2.d: Likewise.

opcodes/

	* i386-gen.c (cpu_flag_init): Add CpuCX16 to CPU_NOCONA_FLAGS,
	CPU_CORE_FLAGS, CPU_CORE2_FLAGS, CPU_COREI7_FLAGS,
	CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS,
	CPU_BTVER2_FLAGS.  Add CPU_CX16_FLAGS.
	(cpu_flags): Add CpuCX16.
	* i386-opc.h (CpuCX16): New.
	(i386_cpu_flags): Add cpucx16.
	* i386-opc.tbl: Replace CpuSSE3 with CpuCX16 for cmpxchg16b.
	* i386-tbl.h: Regenerate.
	* i386-init.h: Likewise.
 2012-09-20 11:53:33 +00:00
Richard Earnshaw
4b8c8c02e9 2012-09-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 
opcodes:
	* arm-dis.c: Changed ldra and strl-form mnemonics
	to lda and stl-form.
gas:
	* config/tc-arm.c: Changed ldra and strl-form mnemonics
	to lda and stl-form for armv8.
gas/testsuite:
	* gas/arm/armv8-a-bad.l: Updated for changed mnemonics.
	* gas/arm/armv8-a-bad.s: Likewise.
	* gas/arm/armv8-a.d: Likewise.
	* gas/arm/armv8-a.s: Likewise.
	* gas/arm/inst.s: Added test for ldrt encoding compatibly with ldralt.
	* gas/arm/inst.d: Updated.
 2012-09-18 14:52:43 +00:00
Maciej W. Rozycki
83ea18d0a3 opcodes/ 
* micromips-opc.c (micromips_opcodes): Correct the encoding of
	the "swxc1" instruction.

	gas/testsuite/
	* gas/mips/micromips.d: Correct the disassembly of SWXC1.
	* gas/mips/micromips-trap.d: Likewise.
	* gas/mips/micromips@24k-triple-stores-1.d: Likewise.
	* gas/mips/micromips@mips4-fp.d: Likewise.
 2012-09-18 14:19:04 +00:00
Richard Earnshaw
062f38fa2f 2012-09-17 Yufeng Zhang <yufeng.zhang@arm.com> 
* aarch64-asm.c (aarch64_ins_imm_half): Remove ATTRIBUTE_UNUSED from
	the parameter 'inst'.
	(aarch64_ins_addr_simm): Add ATTRIBUTE_UNUSED to the parameter 'inst'.
	(convert_mov_to_movewide): Change to assert (0) when
	aarch64_wide_constant_p returns FALSE.
 2012-09-17 17:43:42 +00:00
David Edelsohn
b132a67daa * configure: Regenerate. 2012-09-15 00:07:05 +00:00
Anthony Green
1f9b75dde1 Fix moxie disassembly for new branch semantics 2012-09-14 10:49:03 +00:00
Anthony Green
e202fa84e7 Bi-endian patches for moxie 2012-09-13 22:24:51 +00:00
Alan Modra
1d43092daf missed from 2012-08-15 change 2012-09-10 23:57:09 +00:00
Alan Modra
00716ab174 * config.in: Disable sanity check for kfreebsd. 2012-09-10 22:30:57 +00:00
H.J. Lu
6d2920c847 Regenerate binutils configure 
bfd/

2012-09-10  H.J. Lu  <hongjiu.lu@intel.com>

	* configure: Regenerated.

binutils/

2012-09-10  H.J. Lu  <hongjiu.lu@intel.com>

	* configure: Regenerated.

etc/

2010-11-20  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>

	* Makefile.in (install-strip): New target.

gas/

2012-09-10  H.J. Lu  <hongjiu.lu@intel.com>

	* configure: Regenerated.

gold/

2012-09-09  Alan Modra  <amodra@gmail.com>

	* target.h (Target::gc_mark_symbol, do_gc_mark_symbol): New functions.

gprof/

2012-09-10  H.J. Lu  <hongjiu.lu@intel.com>

	* configure: Regenerated.

intl/

2010-06-27  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>

	PR bootstrap/44621

ld/

2012-09-10  H.J. Lu  <hongjiu.lu@intel.com>

	* configure: Regenerated.

libiberty/

2011-08-28  H.J. Lu  <hongjiu.lu@intel.com>

	* argv.c (dupargv): Replace malloc with xmalloc.  Don't check

opcodes/

2012-09-10  H.J. Lu  <hongjiu.lu@intel.com>

	* configure: Regenerated.
 2012-09-10 17:00:44 +00:00