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e21126b7b3
1007 Commits
| Author | SHA1 | Message | Date | |
|---|---|---|---|---|
Alan Modra
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e21126b7b3 |
Documentation fix
PR 22544 * doc/as.texinfo (8byte): Correct. |
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Jim Wilson
|
fed44c60b3 |
Fix for texinfo 4.8.
gas/ * doc/c-riscv.texi (RISC-V-Directives): Move @section immediately after @node. |
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Jim Wilson
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b57e49f726 |
Update and clean up RISC-V gas documentation.
gas/ * doc/as.texinfo (RISC-V): Alphabetize RISC-V entries. Change RISC-V-Opts to RISC-V-Options. Delete redundant space. Add -fpic and related options to option list. * doc/c-riscv.texi: (RISC-V-Options): Renamed from RISC-V-Opts. (RISC-V Options): Renamed from Options. Add missing period. (-fpic): Also mention -fPIC. (RISC-V Directives): New node. |
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Jim Wilson
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f923328821 |
In x86 -n docs, mention that you need an explicit nop fill byte.
gas/ PR gas/22464 * doc/c-i386.texi (-n): Clarify docs. |
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Jim Wilson
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2ca23e65f5 |
Update docs on filling text with nops.
gas/ * doc/as.texinfo (.align): Change some to most for text nop fill. (.balign, .p2align): Likewise. |
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Tamar Christina
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d0f7791c66 |
Add new AArch64 FP16 FM{A|S} instructions.
This patch separates the new FP16 instructions backported from Armv8.4-a to Armv8.2-a into a new flag order to distinguish them from the rest of the already existing optional FP16 instructions in Armv8.2-a. The new flag "+fp16fml" is available from Armv8.2-a and implies +fp16 and is mandatory on Armv8.4-a. gas/ * config/tc-aarch64.c (fp16fml): New. * doc/c-aarch64.texi (fp16fml): New. * testsuite/gas/aarch64/armv8_2-a-crypto-fp16.d (fp16): Make fp16fml. * testsuite/gas/aarch64/armv8_3-a-crypto-fp16.d (fp16): Make fp16fml. include/ * opcode/aarch64.h: (AARCH64_FEATURE_F16_FML): New. (AARCH64_ARCH_V8_4): Enable AARCH64_FEATURE_F16_FML by default. opcodes/ * aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML and AARCH64_FEATURE_F16. |
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Tamar Christina
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68ffd9368a |
Update documentation for Arvm8.4-A changes to AArch64.
gas/ 2017-11-16 Tamar Christina <tamar.christina@arm.com> * doc/c-aarch64.texi (armv8.4-a, sha2, sha3, sm4): New. (dotprod): Update default note. |
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Tamar Christina
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01f4802036 |
Separate the new FP16 instructions backported from Armv8.4-a to Armv8.2-a into a new flag order to distinguish them from the rest of the already existing optional FP16 instructions in Armv8.2-a.
The new flag "+fp16fml" is available from Armv8.2-a and implies +fp16 and is mandatory from Armv8.4-a. gas/ * config/tc-arm.c (arm_ext_fp16_fml, fp16fml): New. (do_neon_fmac_maybe_scalar_long): Use arm_ext_fp16_fml. * doc/c-arm.texi (fp16, fp16fml): New. * testsuite/gas/arm/armv8_2-a-fp16.d (fp16): Make fp16fml. * testsuite/gas/arm/armv8_3-a-fp16.d (fp16): Make fp16fml. * testsuite/gas/arm/armv8_2-a-fp16-illegal.d (fp16): Make fp16fml. * testsuite/gas/arm/armv8_2-a-fp16-thumb2.d (fp16): Make fp16fml. include/ * opcode/arm.h: (ARM_EXT2_FP16_FML): New. (ARM_AEXT2_V8_4A): Add ARM_EXT2_FP16_FML. |
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Jiong Wang
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dec41383ff |
Adds command line support for Armv8.4-A, via the new command line option -march=armv8.4-a. Add support for "+dotprod" ARM feature (required for ARMv8.4-A). Add assembler and disassembler support for new FP16 instructions introduced in Armv8.4-A
gas * config/tc-arm.c (arm_extensions): (arm_archs): New entry for "armv8.4-a". Add FPU_ARCH_DOTPROD_NEON_VFP_ARMV8. (arm_ext_v8_2): New variable. (enum arm_reg_type): New enumeration REG_TYPE_NSD. (reg_expected_msgs): New entry for REG_TYPE_NSD. (parse_typed_reg_or_scalar): Handle REG_TYPE_NSD. (parse_scalar): Support REG_TYPE_VFS. (enum operand_parse_code): New enumerations OP_RNSD and OP_RNSD_RNSC. (parse_operands): Handle OP_RNSD and OP_RNSD_RNSC. (NEON_SHAPE_DEF): New entries for DHH and DHS. (neon_scalar_for_fmac_fp16_long): New function to generate Rm encoding for new FP16 instructions in ARMv8.2-A. (do_neon_fmac_maybe_scalar_long): New function to encode new FP16 instructions in ARMv8.2-A. (do_neon_vfmal): Wrapper function for vfmal. (do_neon_vfmsl): Wrapper function for vfmsl. (insns): New entries for vfmal and vfmsl. * doc/c-arm.texi (-march): Document "armv8.4-a". * testsuite/gas/arm/dotprod-mandatory.d: New test. * testsuite/gas/arm/armv8_2-a-fp16.s: New test source. * testsuite/gas/arm/armv8_2-a-fp16-illegal.s: New test source. * testsuite/gas/arm/armv8_2-a-fp16.d: New test. * testsuite/gas/arm/armv8_3-a-fp16.d: New test. * testsuite/gas/arm/armv8_4-a-fp16.d: New test. * testsuite/gas/arm/armv8_2-a-fp16-thumb2.d: New test. * testsuite/gas/arm/armv8_2-a-fp16-illegal.d: New test. * testsuite/gas/arm/armv8_2-a-fp16-illegal.l: New error file. opcodes * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new FP16 instructions, including vfmal.f16 and vfmsl.f16. include * opcode/arm.h (ARM_AEXT2_V8_4A): Include Dot Product feature. (ARM_EXT2_V8_4A): New macro. (ARM_AEXT2_V8_4A): Likewise. (ARM_ARCH_V8_4A): Likewise. |
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Siddhesh Poyarekar
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7605d94453 |
Add option for Qualcomm Saphira part
This adds an option for the Qualcomm saphira core, the corresponding gcc patch is here: https://gcc.gnu.org/ml/gcc-patches/2017-10/msg02055.html This was tested with an aarch64 build and make check and also by building and running SPEC2006. gas/ * config/tc-aarch64.c (aarch64_cpus): Add saphira. * doc/c-aarch64.texi: Likewise. |
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Igor Tsimbalist
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ee6872beb1 |
Enable Intel AVX512_BITALG instructions.
Intel has disclosed a set of new instructions. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf gas/ * config/tc-i386.c (cpu_arch): Add .avx512_bitalg. (cpu_noarch): noavx512_bitalg. * doc/c-i386.texi: Document .avx512_bitalg, noavx512_bitalg. * testsuite/gas/i386/i386.exp: Add AVX512_BITALG tests. * testsuite/gas/i386/avx512f_bitalg-intel.d: New test. * testsuite/gas/i386/avx512f_bitalg.d: Likewise. * testsuite/gas/i386/avx512f_bitalg.s: Likewise. * testsuite/gas/i386/avx512vl_bitalg-intel.d: Likewise. * testsuite/gas/i386/avx512vl_bitalg.d: Likewise. * testsuite/gas/i386/avx512vl_bitalg.s: Likewise. * testsuite/gas/i386/x86-64-avx512f_bitalg-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512f_bitalg.d: Likewise. * testsuite/gas/i386/x86-64-avx512f_bitalg.s: Likewise. * testsuite/gas/i386/x86-64-avx512vl_bitalg-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512vl_bitalg.d: Likewise. * testsuite/gas/i386/x86-64-avx512vl_bitalg.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F. (enum): Add EVEX_W_0F3854_P_2. * i386-dis-evex.h (evex_table): Updated. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG, CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS. (cpu_flags): Add CpuAVX512_BITALG. * i386-opc.h (enum): Add CpuAVX512_BITALG. (i386_cpu_flags): Add cpuavx512_bitalg.. * i386-opc.tbl: Add Intel AVX512_BITALG instructions. * i386-init.h: Regenerate. * i386-tbl.h: Likewise. |
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Igor Tsimbalist
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8cfcb7659c |
Enable Intel AVX512_VNNI instructions.
Intel has disclosed a set of new instructions. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf gas/ * config/tc-i386.c (cpu_arch): Add .avx512_vnni. (cpu_noarch): Add noavx512_vnni. * doc/c-i386.texi: Document .avx512_vnni. * testsuite/gas/i386/i386.exp: Add AVX512_VNNI tests. * testsuite/gas/i386/avx512vnni-intel.d: New test. * testsuite/gas/i386/avx512vnni.d: Likewise. * testsuite/gas/i386/avx512vnni.s: Likewise. * testsuite/gas/i386/avx512vnni_vl-intel.d: Likewise. * testsuite/gas/i386/avx512vnni_vl.d: Likewise. * testsuite/gas/i386/avx512vnni_vl.s: Likewise. * testsuite/gas/i386/x86-64-avx512vnni-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512vnni.d: Likewise. * testsuite/gas/i386/x86-64-avx512vnni.s: Likewise. * testsuite/gas/i386/x86-64-avx512vnni_vl-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512vnni_vl.d: Likewise. * testsuite/gas/i386/x86-64-avx512vnni_vl.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851. * i386-dis-evex.h (evex_table): Updated. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI, CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS. (cpu_flags): Add CpuAVX512_VNNI. * i386-opc.h (enum): Add CpuAVX512_VNNI. (i386_cpu_flags): Add cpuavx512_vnni. * i386-opc.tbl Add Intel AVX512_VNNI instructions. * i386-init.h: Regenerate. * i386-tbl.h: Likewise. |
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Igor Tsimbalist
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ff1982d53a |
Enable Intel VPCLMULQDQ instruction.
Intel has disclosed a set of new instructions. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf gas/ * config/tc-i386.c (cpu_arch): Add VPCLMULQDQ. * doc/c-i386.texi: Document VPCLMULQDQ. * testsuite/gas/i386/i386.exp: Run VPCLMULQDQ tests. * testsuite/gas/i386/avx512f_vpclmulqdq-intel.d: New test. * testsuite/gas/i386/avx512f_vpclmulqdq-wig.s: Ditto. * testsuite/gas/i386/avx512f_vpclmulqdq-wig1-intel.d: Ditto. * testsuite/gas/i386/avx512f_vpclmulqdq-wig1.d: Ditto. * testsuite/gas/i386/avx512f_vpclmulqdq.d: Ditto. * testsuite/gas/i386/avx512f_vpclmulqdq.s: Ditto. * testsuite/gas/i386/avx512vl_vpclmulqdq-intel.d: Ditto. * testsuite/gas/i386/avx512vl_vpclmulqdq-wig.s: Ditto. * testsuite/gas/i386/avx512vl_vpclmulqdq-wig1-intel.d: Ditto. * testsuite/gas/i386/avx512vl_vpclmulqdq-wig1.d: Ditto. * testsuite/gas/i386/avx512vl_vpclmulqdq.d: Ditto. * testsuite/gas/i386/avx512vl_vpclmulqdq.s: Ditto. * testsuite/gas/i386/vpclmulqdq-intel.d: Ditto. * testsuite/gas/i386/vpclmulqdq.d: Ditto. * testsuite/gas/i386/vpclmulqdq.s: Ditto. * testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig.s: Ditto. * testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig1-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig1.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.s: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig.s: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig1-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig1.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.s: Ditto. * testsuite/gas/i386/x86-64-vpclmulqdq-intel.d: Ditto. * testsuite/gas/i386/x86-64-vpclmulqdq.d: Ditto. * testsuite/gas/i386/x86-64-vpclmulqdq.s: Ditto. opcodes/ * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44. (enum): Remove VEX_LEN_0F3A44_P_2. (vex_len_table): Ditto. (enum): Remove VEX_W_0F3A44_P_2. (vew_w_table): Ditto. (prefix_table): Adjust instructions (see prefixes above). * i386-dis-evex.h (evex_table): Add new instructions (see prefixes above). * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ. (bitfield_cpu_flags): Ditto. * i386-opc.h (enum): Ditto. (i386_cpu_flags): Ditto. (CpuUnused): Comment out to avoid zero-width field problem. * i386-opc.tbl (vpclmulqdq): New instruction. * i386-init.h: Regenerate. * i386-tbl.h: Ditto. |
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Igor Tsimbalist
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8dcf1fadf2 |
Enable Intel VAES instructions.
Intel has disclosed a set of new instructions. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf gas/ * config/tc-i386.c (cpu_arch): Add VAES. * doc/c-i386.texi: Document VAES. * testsuite/gas/i386/i386.exp: Run VAES tests. * testsuite/gas/i386/avx512f_vaes-intel.d: New test. * testsuite/gas/i386/avx512f_vaes-wig.s: Ditto. * testsuite/gas/i386/avx512f_vaes-wig1-intel.d: Ditto. * testsuite/gas/i386/avx512f_vaes-wig1.d: Ditto. * testsuite/gas/i386/avx512f_vaes.d: Ditto. * testsuite/gas/i386/avx512f_vaes.s: Ditto. * testsuite/gas/i386/avx512vl_vaes-intel.d: Ditto. * testsuite/gas/i386/avx512vl_vaes-wig.s: Ditto. * testsuite/gas/i386/avx512vl_vaes-wig1-intel.d: Ditto. * testsuite/gas/i386/avx512vl_vaes-wig1.d: Ditto. * testsuite/gas/i386/avx512vl_vaes.d: Ditto. * testsuite/gas/i386/avx512vl_vaes.s: Ditto. * testsuite/gas/i386/vaes-intel.d: Ditto. * testsuite/gas/i386/vaes.d: Ditto. * testsuite/gas/i386/vaes.s: Ditto. * testsuite/gas/i386/x86-64-avx512f_vaes-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vaes-wig.s: Ditto. * testsuite/gas/i386/x86-64-avx512f_vaes-wig1-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vaes-wig1.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vaes.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vaes.s: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vaes-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vaes-wig.s: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vaes-wig1-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vaes-wig1.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vaes.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vaes.s: Ditto. * testsuite/gas/i386/x86-64-vaes-intel.d: Ditto. * testsuite/gas/i386/x86-64-vaes.d: Ditto. * testsuite/gas/i386/x86-64-vaes.s: Ditto. opcodes/ * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF. (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2, VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2. (vex_len_table): Ditto. (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2, VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2. (vew_w_table): Ditto. (prefix_table): Adjust instructions (see prefixes above). * i386-dis-evex.h (evex_table): Add new instructions (see prefixes above). * i386-gen.c (cpu_flag_init): Add VAES. (bitfield_cpu_flags): Ditto. * i386-opc.h (enum): Ditto. (i386_cpu_flags): Ditto. * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions. * i386-init.h: Regenerate. * i386-tbl.h: Ditto. |
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Igor Tsimbalist
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48521003d5 |
Enable Intel GFNI instructions.
Intel has disclosed a set of new instructions. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf gas/ * config/tc-i386.c (cpu_arch): Add .gfni. * doc/c-i386.texi: Document .gfni. * testsuite/gas/i386/i386.exp: Add GFNI tests. * testsuite/gas/i386/avx.s: New GFNI test. * testsuite/gas/i386/x86-64-avx.s: Likewise. * testsuite/gas/i386/avx.d: Adjust. * testsuite/gas/i386/avx-intel.d: Likewise * testsuite/gas/i386/ilp32/x86-64-avx-intel.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-avx.d: Likewise. * testsuite/gas/i386/avx512f_gfni-intel.d: New test. * testsuite/gas/i386/avx512f_gfni.d: Likewise. * testsuite/gas/i386/avx512f_gfni.s: Likewise. * testsuite/gas/i386/avx512vl_gfni-intel.d: Likewise. * testsuite/gas/i386/avx512vl_gfni.d: Likewise. * testsuite/gas/i386/avx512vl_gfni.s: Likewise. * testsuite/gas/i386/gfni-intel.d: Likewise. * testsuite/gas/i386/gfni.d: Likewise. * testsuite/gas/i386/gfni.s: Likewise. * testsuite/gas/i386/x86-64-avx512f_gfni-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512f_gfni.d: Likewise. * testsuite/gas/i386/x86-64-avx512f_gfni.s: Likewise. * testsuite/gas/i386/x86-64-avx512vl_gfni-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512vl_gfni.d: Likewise. * testsuite/gas/i386/x86-64-avx512vl_gfni.s: Likewise. * testsuite/gas/i386/x86-64-avx_gfni-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx_gfni.d: Likewise. * testsuite/gas/i386/x86-64-avx_gfni.s: Likewise. * testsuite/gas/i386/x86-64-gfni-intel.d: Likewise. * testsuite/gas/i386/x86-64-gfni.d: Likewise. * testsuite/gas/i386/x86-64-gfni.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF. (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2. (prefix_table): Updated (see prefixes above). (three_byte_table): Likewise. (vex_w_table): Likewise. * i386-dis-evex.h: Likewise. * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI. (cpu_flags): Add CpuGFNI. * i386-opc.h (enum): Add CpuGFNI. (i386_cpu_flags): Add cpugfni. * i386-opc.tbl: Add Intel GFNI instructions. * i386-init.h: Regenerate. * i386-tbl.h: Likewise. |
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Igor Tsimbalist
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53467f5707 |
Enable Intel AVX512_VBMI2 instructions.
Intel has disclosed a set of new instructions. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf gas/ * config/tc-i386.c (cpu_arch): Add .avx512_vbmi2. (cpu_noarch): noavx512_vbmi2. * doc/c-i386.texi: Document .avx512_vbmi2, noavx512_vbmi2. * testsuite/gas/i386/i386.exp: Add AVX512_VBMI2 tests. * testsuite/gas/i386/avx512vbmi2-intel.d: New test. * testsuite/gas/i386/avx512vbmi2.d: Likewise. * testsuite/gas/i386/avx512vbmi2.s: Likewise. * testsuite/gas/i386/avx512vbmi2_vl-intel.d: Likewise. * testsuite/gas/i386/avx512vbmi2_vl.d: Likewise. * testsuite/gas/i386/avx512vbmi2_vl.s: Likewise. * testsuite/gas/i386/x86-64-avx512vbmi2-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512vbmi2.d: Likewise. * testsuite/gas/i386/x86-64-avx512vbmi2.s: Likewise. * testsuite/gas/i386/x86-64-avx512vbmi2_vl-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512vbmi2_vl.d: Likewise. * testsuite/gas/i386/x86-64-avx512vbmi2_vl.s: Likewise. opcodes/ * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode. Define EXbScalar and EXwScalar for OP_EX. (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71, PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73. (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2, EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2, EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2, EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2. (intel_operand_size): Handle b_scalar_mode and w_scalar_mode. (OP_E_memory): Likewise. * i386-dis-evex.h: Updated. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2, CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS. (cpu_flags): Add CpuAVX512_VBMI2. * i386-opc.h (enum): Add CpuAVX512_VBMI2. (i386_cpu_flags): Add cpuavx512_vbmi2. * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions. * i386-init.h: Regenerate. * i386-tbl.h: Likewise. |
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Nick Clifton
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808811a369 |
Improve handling of REPT pseudo op with a negative count.
PR 22324 * read.c (s_rept): Use size_t type for count parameter. (do_repeat): Change type of count parameter to size_t. Issue an error is the count parameter is negative. (do_repeat_with_expression): Likewise. * read.h: Update prototypes for do_repeat and do_repeat_with_expression. * doc/as.texinfo (Rept): Document that a zero count is allowed but negative counts are not. * config/tc-rx.c (rx_rept): Use size_t type for count parameter. * config/tc-tic54x.c (tic54x_loop): Cast count parameter to size_t type. * testsuite/gas/macros/end.s: Add a test using a negative repeat count. * testsuite/gas/macros/end.l: Add expected error message. |
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Jozef Lawrynowicz
|
7ef3addbe1 |
Improve MSP430 section placement.
ld * emultempl/msp430.em (change_output_section): New function.
(move_prefixed_section): New function.
(add_region_prefix): New function.
(msp430_elf_after_open): New function.
(gld${EMULATION_NAME}_add_options): Implement.
(gld${EMULATION_NAME}_list_options): Implement.
(gld${EMULATION_NAME}_handle_option): Implement.
* ld.texinfo: Document new options.
* testsuite/ld-msp430-elf/main-bss-lower.d: New.
* testsuite/ld-msp430-elf/main-bss-upper.d: New.
* testsuite/ld-msp430-elf/main-const-lower.d: New.
* testsuite/ld-msp430-elf/main-const-upper.d: New.
* testsuite/ld-msp430-elf/main-text-lower.d: New.
* testsuite/ld-msp430-elf/main-text-upper.d: New.
* testsuite/ld-msp430-elf/main-var-lower.d: New.
* testsuite/ld-msp430-elf/main-var-upper.d: New.
* testsuite/ld-msp430-elf/main-with-data-bss-unique-sec.s: New.
* testsuite/ld-msp430-elf/main-with-data-bss.s: New.
* testsuite/ld-msp430-elf/main-with-text-rodata-unique-sec.s: New.
* testsuite/ld-msp430-elf/main-with-text-rodata.s: New.
* testsuite/ld-msp430-elf/msp430-elf.exp: New.
* testsuite/ld-msp430-elf/msp430-no-lower.ld: New.
* testsuite/ld-msp430-elf/msp430.ld: New.
* emultempl/msp430.em (data_statement_size): New.
(eval_upper_either_sections): New.
(eval_lower_either_sections): New.
(intermediate_relax_sections): New.
(msp430_elf_after_allocation): New.
* emultempl/msp430.em (gld${EMULATION_NAME}_place_orphan): Always
place sections in the lower region.
gas * config/tc-msp430.c (md_parse_option): Define high data and high
bss symbols if -mdata-region is passed.
Define -mdata-region open.
* doc/c-msp430.texi: Document -mdata-region.
* testsuite/gas/msp430/high-data-bss-sym.d: New test.
* testsuite/gas/msp430/high-data-bss-sym.s: New.
* testsuite/gas/msp430/msp430.exp: Add -mdata-region tests.
|
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Alexander Fedotov
|
7408194835 |
[PowerPC VLE] Add SPE2 and EFS2 instructions support
include/ * opcode/ppc.h: (spe2_opcodes, spe2_num_opcodes): New. (PPC_OPCODE_SPE2): New define. (PPC_OPCODE_EFS2): Likewise. (SPE2_XOP): Likewise. (SPE2_XOP_TO_SEG): Likewise. opcodes/ * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "e200z4" entry. New entries efs2 and spe2. Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry. (SPE2_OPCD_SEGS): New macro. (spe2_opcd_indices): New. (disassemble_init_powerpc): Handle SPE2 opcodes. (lookup_spe2): New function. (print_insn_powerpc): call lookup_spe2. * ppc-opc.c (insert_evuimm1_ex0): New function. (extract_evuimm1_ex0): Likewise. (insert_evuimm_lt8): Likewise. (extract_evuimm_lt8): Likewise. (insert_off_spe2): Likewise. (extract_off_spe2): Likewise. (insert_Ddd): Likewise. (extract_Ddd): Likewise. (DD): New operand. (EVUIMM_LT8): Likewise. (EVUIMM_LT16): Adjust. (MMMM): New operand. (EVUIMM_1): Likewise. (EVUIMM_1_EX0): Likewise. (EVUIMM_2): Adjust. (NNN): New operand. (VX_OFF_SPE2): Likewise. (BBB): Likewise. (DDD): Likewise. (VX_MASK_DDD): New mask. (HH): New operand. (VX_RA_CONST): New macro. (VX_RA_CONST_MASK): Likewise. (VX_RB_CONST): Likewise. (VX_RB_CONST_MASK): Likewise. (VX_OFF_SPE2_MASK): Likewise. (VX_SPE_CRFD): Likewise. (VX_SPE_CRFD_MASK VX): Likewise. (VX_SPE2_CLR): Likewise. (VX_SPE2_CLR_MASK): Likewise. (VX_SPE2_SPLATB): Likewise. (VX_SPE2_SPLATB_MASK): Likewise. (VX_SPE2_OCTET): Likewise. (VX_SPE2_OCTET_MASK): Likewise. (VX_SPE2_DDHH): Likewise. (VX_SPE2_DDHH_MASK): Likewise. (VX_SPE2_HH): Likewise. (VX_SPE2_HH_MASK): Likewise. (VX_SPE2_EVMAR): Likewise. (VX_SPE2_EVMAR_MASK): Likewise. (PPCSPE2): Likewise. (PPCEFS2): Likewise. (vle_opcodes): Add EFS2 and some missing SPE opcodes. (powerpc_macros): Map old SPE instructions have new names with the same opcodes. Add SPE2 instructions which just are mapped to SPE2. (spe2_opcodes): Add SPE2 opcodes. gas/ * config/tc-ppc.c: (md_parse_option): Add mspe2 switch. (md_show_usage): Document -mspe2. (ppc_setup_opcodes): Handle spe2_opcodes. * doc/as.texinfo: Document -mspe2. * doc/c-ppc.texi: Likewise. * testsuite/gas/ppc/efs.d: New file. * testsuite/gas/ppc/efs.s: Likewise. * testsuite/gas/ppc/efs2.d: Likewise. * testsuite/gas/ppc/efs2.s: Likewise. * testsuite/gas/ppc/ppc.exp: Run new tests. * testsuite/gas/ppc/spe.d: New file. * testsuite/gas/ppc/spe.s: Likewise. * testsuite/gas/ppc/spe2-checks.d: Likewise. * testsuite/gas/ppc/spe2-checks.l: Likewise. * testsuite/gas/ppc/spe2-checks.s: Likewise. * testsuite/gas/ppc/spe2.d: Likewise. * testsuite/gas/ppc/spe2.s: Likewise. * testsuite/gas/ppc/spe_ambiguous.d: Likewise. * testsuite/gas/ppc/spe_ambiguous.s: Likewise. |
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Ramana Radhakrishnan
|
8975f86409 |
[Patch AArch64] Turn lr, fp, ip0 and ip1 into proper aliases
We got a report from the linux-arm-kernel folks about getting spurious warnings when building the kernel with binutils 2.29. See https://www.spinics.net/lists/arm-kernel/msg599929.html which boils down to this testcase. $> cat /tmp/tst.s lr .req x30 /tmp/tst.s: Assembler messages: /tmp/tst.s:1: Warning: ignoring attempt to redefine built-in register 'lr' Instead let's treat this as a proper alias at startup time thus avoiding the problem and treating these as proper aliases rather than new registers. This means that attempts to redefine the alias with the same "name" will provoke no warning and attempts to redefine the alias to something else will provoke the above mentioned warning. Tested make check-gas and no regressions. Ok to apply to trunk (and backport to 2.29 branch)? Regards Ramana |
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Alexandre Oliva
|
ba8826a82a |
This patch introduces support for specifing views in .loc directives, so that the compiler can use the assembler to generate line number information and have the assembler determine view numbers to multiple views at the same program counter.
binutils* dwarf.c (struct State_Machine_Registers): Add view field. (reset_state_machine): Reset view. (process_extended_line_op): Reset view when appropriate. (display_debug_lines_raw): Increment or reset view when appropriate. Print nonzero views. Support print view resets, disabled by default. (display_debug_lines_decoded): Likewise. Disambiguate op_code tests, enabling printing of end_sequence. * testsuite/binutils-all/dw2-1.W: Add nonzero views. * testsuite/binutils-all/dw2-3.W: Likewise. * testsuite/binutils-all/dw2-3gabi.W: Likewise. * testsuite/binutils-all/dw5.W: Add end sequence lines. * testsuite/binutils-all/i386/compressed-1a.d: Add nonzero views. * testsuite/binutils-all/libdw2-compressedgabi.out: Likewise. * testsuite/binutils-all/objdump.W: Likewise. * testsuite/binutils-all/objdump.WL: Add end sequence lines. * testsuite/binutils-all/x86-64/compressed-1a.d: Add nonzero views. gas * doc/as.texinfo (.loc): Document view support. * dwarf2dbg.c (unused): Check offset of next in struct line_entry. (current): Initialize view. (force_reset_view, view_assert_failed): New variables. (reverse_line_entry_list): New function. (set_or_check_view): Likewise. (dwarf2_gen_line_info_1): Call it. (dwarf2_where): Set view to NULL. (dwarf2_emit_insn): Return early when called before first file. (dwarf2_directive_loc): Add view support. Emit insn immediately when view option is given. (process_entries): Avoid set_address to reset view when a known address change already implies the view reset. (dwarf2dbg_final_check): New function. * dwarf2dbg.h (struct dwarf2_line_info): Add view. (dwarf2dbg_final_check): Declare. * read.c (s_leb128): Parse expression as deferred. * testsuite/gas/all/gas.exp: Run sleb128-9. * testsuite/gas/all/sleb128-9.d: New. * testsuite/gas/all/sleb128-9.l: New. * testsuite/gas/all/sleb128-9.s: New. * testsuite/gas/elf/dwarf2-1.d: Add nonzero views. * testsuite/gas/elf/dwarf2-2.d: Likewise. * testsuite/gas/elf/dwarf2-5.d: New. * testsuite/gas/elf/dwarf2-5.s: New. * testsuite/gas/elf/dwarf2-6.d: New. * testsuite/gas/elf/dwarf2-6.s: New. * testsuite/gas/elf/dwarf2-7.d: New. * testsuite/gas/elf/dwarf2-7.s: New. * testsuite/gas/elf/dwarf2-8.d: New. * testsuite/gas/elf/dwarf2-8.l: New. * testsuite/gas/elf/dwarf2-8.s: New. * testsuite/gas/elf/dwarf2-9.d: New. * testsuite/gas/elf/dwarf2-9.l: New. * testsuite/gas/elf/dwarf2-9.s: New. * testsuite/gas/elf/dwarf2-10.d: New. * testsuite/gas/elf/dwarf2-10.l: New. * testsuite/gas/elf/dwarf2-10.s: New. * testsuite/gas/elf/dwarf2-11.d: New. * testsuite/gas/elf/dwarf2-11.s: New. * testsuite/gas/elf/dwarf2-12.d: New. * testsuite/gas/elf/dwarf2-12.s: New. * testsuite/gas/elf/dwarf2-13.d: New. * testsuite/gas/elf/dwarf2-13.s: New. * testsuite/gas/elf/dwarf2-14.d: New. * testsuite/gas/elf/dwarf2-14.s: New. * testsuite/gas/elf/dwarf2-15.d: New. * testsuite/gas/elf/dwarf2-15.s: New. * testsuite/gas/elf/dwarf2-16.d: New. * testsuite/gas/elf/dwarf2-16.s: New. * testsuite/gas/elf/dwarf2-17.d: New. * testsuite/gas/elf/dwarf2-17.s: New. * testsuite/gas/elf/dwarf2-18.d: New. * testsuite/gas/elf/dwarf2-18.s: New. * testsuite/gas/elf/elf.exp: Run dwarf2-5..18 tests. * testsuite/gas/i386/dw2-compress-1.d: Add nonzero views. * testsuite/gas/i386/dw2-compressed-1.d: Likewise. * testsuite/gas/i386/ilp32/lns/lns-duplicate.d: Likewise. * testsuite/gas/lns/lns-big-delta.d: Likewise. * testsuite/gas/lns/lns-duplicate.d: Likewise. * testsuite/gas/mips/loc-swap-2.d: Likewise. * testsuite/gas/mips/loc-swap-3.d: Likewise. * testsuite/gas/mips/loc-swap.d: Likewise. * testsuite/gas/mips/micromips@loc-swap-2.d: Likewise. * testsuite/gas/mips/micromips@loc-swap.d: Likewise. * testsuite/gas/mips/mips16@loc-swap-2.d: Likewise. * testsuite/gas/mips/mips16@loc-swap.d: Likewise. * testsuite/gas/mips/mips16e@loc-swap.d: Likewise. * write.c (write_object_file): Check pending view asserts. (cvt_frag_to_fill): Complain about undefined leb128 operand. |
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Andreas Krebbel
|
47826cdbec |
S/390: Support z14 as CPU name.
With IBM z14 officially announced I can add z14 as CPU name. No regressions with that patch on s390x. gas/ChangeLog: 2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config/tc-s390.c (s390_parse_cpu): Add z14 as alternate CPU name. * doc/as.texinfo: Add z14 to CPU string list. * doc/c-s390.texi: Likewise. opcodes/ChangeLog: 2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * s390-mkopc.c (main): Enable z14 as CPU string in the opcode table. |
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Georg-Johann Lay
|
f27dadca0a |
Update assembler documentation on some AVR cores.
PR 21472 * config/tc-avr.c (mcu_types): Add entries for: attiny212, attiny214, attiny412, attiny414, attiny814, attiny1614, attiny1616, attiny1617, attiny3214, attiny3216, attiny3217. (md_show_usage): Adjust doc for "avrxmega3". * doc/c-avr.texi (AVR options) [-mmcu=]: Adjust doc for avrxmega3. Add MCUs: attiny212, attiny214, attiny412, attiny414, attiny416, attiny417, attiny814, attiny816, attiny817, attiny1614, attiny1616, attiny1617, attiny3214, attiny3216, attiny3217. |
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James Greenhalgh
|
15a7695fdc |
[ARM] Add support for Cortex-A55 and Cortex-A75.
This patch adds support for the ARM Cortex-A55 and Cortex-A75 processors. The ARM Cortex-A55 and Cortex-A75 procsessors implement the ARMv8-A architecture, with support for the ARMv8.1-A and ARMv8.2-A extensions, including support for the 16-bit floating point extensions. The 16-bit floating-point extensions are optional, and we haven't defined an option mapping straight to them thus far, so this patch first needs to add one of those in include/opcode/arm.h, then we can simply add the CPU names as usual in config/tc-arm.c . Tested on arm-none-eabi. 2017-07-05 James Greenhalgh <james.greenhalgh@arm.com> * config/tc-arm.c (arm_cpus): Add Cortex-A55 and Cortex-A75. * doc/c-arm.texi (-mcpu): Document Cortex-A55 and Cortex-A75. |
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|
Georg-Johann Lay
|
32f76c6773 |
Add support for a __gcc_isr pseudo isntruction to the AVR assembler.
PR gas/21683
include * opcode/avr.h (AVR_INSN): Add one for __gcc_isr.
gas * doc/c-avr.texi (AVR Options) <-mgcc-isr>: Document it.
(AVR Pseudo Instructions): New node.
* config/tc-avr.h (md_pre_output_hook): Define to avr_pre_output_hook.
(md_undefined_symbol): Define to avr_undefined_symbol.
(avr_pre_output_hook, avr_undefined_symbol): New protos.
* config/tc-avr.c (struc-symbol.h): Include it.
(ISR_CHUNK_Done, ISR_CHUNK_Prologue, ISR_CHUNK_Epilogue): New enums.
(avr_isr, avr_gccisr_opcode)
(avr_no_sreg_hash, avr_no_sreg): New static variables.
(avr_opt_s) <have_gccisr>: Add field.
(avr_opt): Add initializer for have_gccisr.
(enum options) <OPTION_HAVE_GCCISR>: Add enum.
(md_longopts) <"mgcc-isr">: Add entry.
(md_show_usage): Document -mgcc-isr.
(md_parse_option) [OPTION_HAVE_GCCISR]: Handle it.
(md_undefined_symbol): Remove.
(avr_undefined_symbol, avr_pre_output_hook): New fuctions.
(md_begin) <avr_no_sreg_hash, avr_gccisr_opcode>: Initialize them.
(avr_operand) <pregno>: Add argument and set *pregno if function
is called for a register constraint.
[N]: Handle constraint.
(avr_operands) <avr_operand>: Pass 5th parameter to calls.
[avr_opt.have_gccisr]: Call avr_update_gccisr. Call
avr_gccisr_operands instead of avr_operands.
(avr_update_gccisr, avr_emit_insn, avr_patch_gccisr_frag)
(avr_gccisr_operands, avr_check_gccisr_done): New static functions.
* testsuite/gas/avr/gccisr-01.d: New test.
* testsuite/gas/avr/gccisr-01.s: New test.
* testsuite/gas/avr/gccisr-02.d: New test.
* testsuite/gas/avr/gccisr-02.s: New test.
* testsuite/gas/avr/gccisr-03.d: New test.
* testsuite/gas/avr/gccisr-03.s: New test.
|
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|
Tamar Christina
|
65a55fbbd9 |
[AArch64] Add dot product support for AArch64 to binutils
gas/ * config/tc-aarch64.c (aarch64_reg_parse_32_64): Accept 4B. (aarch64_features): Added dotprod. * doc/c-aarch64.texi: Added dotprod. * testsuite/gas/aarch64/dotproduct.d: New. * testsuite/gas/aarch64/dotproduct.s: New. opcodes/ * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod. * aarch64-dis.c (aarch64_ext_reglane): Likewise. * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New. (aarch64_feature_dotprod, DOT_INSN): New. (udot, sdot): New. * aarch64-dis-2.c: Regenerated. include/ * opcode/aarch64.h: (AARCH64_FEATURE_DOTPROD): New. (aarch64_insn_class): Added dotprod. |
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|
Jiong Wang
|
c604a79ad4 |
[ARM] Assembler and disassembler support Dot Product Extension
This patch add assembler and disassembler support for new Dot Product Extension. The support can be enabled through the new "+dotprod" extension. include/ * opcode/arm.h (FPU_NEON_EXT_DOTPROD): New macro. (FPU_ARCH_DOTPROD_NEON_VFP_ARMV8): New macro. gas/ * config/tc-arm.c (fpu_neon_ext_dotprod): New variable. (neon_scalar_for_mul): Improve comments. (do_neon_dotproduct): New function to encode Dot Product instructions. (do_neon_dotproduct_s): Wrapper function for signed Dot Product instructions. (do_neon_dotproduct_u): Wrapper function for unsigned Dot Product instructions. (insns): New entries for vsdot and vudot. (arm_extensions): New entry for "dotprod". * doc/c-arm.texi: Document new "dotprod" extension. * testsuite/gas/arm/dotprod.s: New test source. * testsuite/gas/arm/dotprod-illegal.s: New test source. * testsuite/gas/arm/dotprod.d: New test. * testsuite/gas/arm/dotprod-thumb2.d: New test. * testsuite/gas/arm/dotprod-illegal.d: New test. * testsuite/gas/arm/dotprod-legacy-arch.d: New test. * testsuite/gas/arm/dotprod-illegal.l: New error file. * testsuite/gas/arm/dotprod-legacy-arch.l: New error file. opcodes/ * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot. |
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Maciej W. Rozycki
|
38bf472a15 |
MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor support
Add support for the Imagination interAptiv MR2 MIPS32r3 processor with
the MIPS16e2 ASE as per documentation, including in particular:
1. Support for implementation-specific interAptiv MR2 COPYW and UCOPYW
MIPS16e2 instructions[1], for assembly and disassembly,
2. Support for implementation-specific interAptiv MR2 SAVE and RESTORE
regular MIPS instructions[2], for assembly and disassembly,
3. ELF binary file annotation for the interAptiv MR2 MIPS architecture
extension.
4. Support for interAptiv MR2 architecture selection for assembly, in
the form of the `-march=interaptiv-mr2' command-line option and its
corresponding `arch=interaptiv-mr2' setting for the `.set' and
`.module' pseudo-ops.
5. Support for interAptiv MR2 architecture selection for disassembly,
in the form of the `mips:interaptiv-mr2' target architecture, for
use e.g. with the `-m' command-line option for `objdump'.
Parts of this change by Matthew Fortune and Andrew Bennett.
References:
[1] "MIPS32 interAptiv Multiprocessing System Software User's Manual",
Imagination Technologies Ltd., Document Number: MD00904, Revision
02.01, June 15, 2016, Section 24.3 "MIPS16e2 Implementation Specific
Instructions", pp. 878-883
[2] same, Chapter 25 "Implementation-specific Instructions", pp. 911-917
include/
* elf/mips.h (E_MIPS_MACH_IAMR2): New macro.
(AFL_EXT_INTERAPTIV_MR2): Likewise.
* opcode/mips.h: Document new operand codes defined.
(INSN_INTERAPTIV_MR2): New macro.
(INSN_CHIP_MASK): Adjust accordingly.
(CPU_INTERAPTIV_MR2): New macro.
(cpu_is_member) <CPU_INTERAPTIV_MR2>: New case.
(MIPS16_ALL_ARGS): Rename to...
(MIPS_SVRS_ALL_ARGS): ... this.
(MIPS16_ALL_STATICS): Rename to...
(MIPS_SVRS_ALL_STATICS): ... this.
bfd/
* archures.c (bfd_mach_mips_interaptiv_mr2): New macro.
* cpu-mips.c (I_interaptiv_mr2): New enum value.
(arch_info_struct): Add "mips:interaptiv-mr2" entry.
* elfxx-mips.c (_bfd_elf_mips_mach) <E_MIPS_MACH_IAMR2>: New
case.
(mips_set_isa_flags) <bfd_mach_mips_interaptiv_mr2>: Likewise.
(bfd_mips_isa_ext) <bfd_mach_mips_interaptiv_mr2>: Likewise.
(print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise.
(mips_mach_extensions): Add `bfd_mach_mipsisa32r3' and
`bfd_mach_mips_interaptiv_mr2' entries.
* bfd-in2.h: Regenerate.
opcodes/
* mips-formats.h (INT_BIAS): New macro.
(INT_ADJ): Redefine in INT_BIAS terms.
* mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
(mips_print_save_restore): New function.
(print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
(validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
call.
(print_insn_args): Handle OP_SAVE_RESTORE_LIST.
(print_mips16_insn_arg): Call `mips_print_save_restore' for
OP_SAVE_RESTORE_LIST handling, factored out from here.
* mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
(RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
(mips_builtin_opcodes): Add "restore" and "save" entries.
* mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
(IAMR2): New macro.
(mips16_opcodes): Add "copyw" and "ucopyw" entries.
binutils/
* readelf.c (get_machine_flags) <E_MIPS_MACH_IAMR2>: New case.
(print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise.
* NEWS: Mention Imagination interAptiv MR2 processor support.
gas/
* config/tc-mips.c (validate_mips_insn): Handle
OP_SAVE_RESTORE_LIST specially.
(mips_encode_save_restore, mips16_encode_save_restore): New
functions.
(match_save_restore_list_operand): Factor out SAVE/RESTORE
operand insertion into the instruction word or halfword to these
new functions.
(mips_cpu_info_table): Add "interaptiv-mr2" entry.
* doc/c-mips.texi (MIPS Options): Add `interaptiv-mr2' to the
`-march=' argument list.
|
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Thomas Preud'homme
|
0cda1e190d |
[ARM] Add support for ARM Cortex-R52 processor
=== Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to add support for ARM Cortex-R52 processor. === Patch description === This patch adds support for Cortex-R52 as an ARMv8-R processor with CRC extensions. 2017-06-26 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * NEWS: Mention support of ARM Cortex-R52 processor. * config/tc-arm.c (arm_cpus): Add entry for ARM Cortex-R52 processor. * doc/c-arm.texi: Mention support for -mcpu=cortex-r52. |
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|
Thomas Preud'homme
|
ced40572e4 |
[ARM] Add support for ARMv8-R in assembler and readelf
=== Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to add support for ARMv8-R in GAS: instructions, build attributes and readelf. === Patch description === Although some differences exist for system registers, from GAS point of view ARMv8-R supports the same instructions as ARMv8-A Aarch32 state and a subset of its extensions. This patch therefore introduce a new feature bit to distinguish the availability of the pan, ras and rdma extensions between ARMv8-A and ARMv8-R and allow crypto, fp and simd extensions to be used by ARMv8-R. Most of the changes are then in the testsuite to (i) rename source files and error output to be shared between ARMv8-A and ARMv8-R, (ii) rename files with expected output for ARMv8-A build attributes and (iii) add new files with expected output for ARMv8-R build attributes. 2017-06-24 Thomas Preud'homme <thomas.preudhomme@arm.com> binutils/ * readelf.c (arm_attr_tag_CPU_arch): Fill value for ARMv8-R. gas/ * NEWS: Mention support for ARMv8-R architecture. * config/tc-arm.c (arm_archs): Add entry for ARMv8-R. (arm_extensions): Restrict pan, ras and rdma extension to ARMv8-A and make crypto, fp and simd extensions available to ARMv8-R. (cpu_arch_ver): Add entry for ARMv8-R. (aeabi_set_public_attributes): Update gas_assert for Tag_DIV_use logic. * testsuite/gas/arm/armv8-a+fp.s: Rename into ... * testsuite/gas/arm/armv8-ar+fp.s: This. Remove .arch directive. * testsuite/gas/arm/armv8-a+fp.d: Specify source to assemble and architecture to assemble for. * testsuite/gas/arm/armv8-r+fp.d: New. * testsuite/gas/arm/armv8-a+simd.s: Rename into ... * testsuite/gas/arm/armv8-ar+simd.s: This. Remove .arch directive. * testsuite/gas/arm/armv8-a+simd.d: Specify source to assemble and architecture to assemble for. * testsuite/gas/arm/armv8-r+simd.d: New. * testsuite/gas/arm/armv8-a-bad.s: Rename into ... * testsuite/gas/arm/armv8-ar-bad.s: This. Remove .arch directive. * testsuite/gas/arm/armv8-a-bad.l: Rename into ... * testsuite/gas/arm/armv8-ar-bad.l: This. Decrement line number by 1. * testsuite/gas/arm/armv8-a-bad.d: Specify source to assemble, architecture to assemble for and adjust error output file. * testsuite/gas/arm/armv8-r-bad.d: New. * testsuite/gas/arm/armv8-a-barrier.s: Rename into ... * testsuite/gas/arm/armv8-ar-barrier.s: This. * testsuite/gas/arm/armv8-a-barrier-arm.d: Adjust source. * testsuite/gas/arm/armv8-a-barrier-thumb.d: Likewise. * testsuite/gas/arm/armv8-r-barrier-arm.d: New. * testsuite/gas/arm/armv8-r-barrier-thumb.d: New. * testsuite/gas/arm/armv8-a-it-bad.s: Rename into ... * testsuite/gas/arm/armv8-ar-it-bad.s: This. Remove .arch directive. * testsuite/gas/arm/armv8-a-it-bad.l: Rename into ... * testsuite/gas/arm/armv8-ar-it-bad.l: This. Decrement line number by 1. * testsuite/gas/arm/armv8-a-it-bad.d: Specify source to assemble, architecture to assemble for and adjust error output file. * testsuite/gas/arm/armv8-r-it-bad.d: New. * testsuite/gas/arm/armv8-a.s: Rename into ... * testsuite/gas/arm/armv8-ar.s: This. Remove .arch directive. * testsuite/gas/arm/armv8-a.d: Specify source to assemble and architecture to assemble for. * testsuite/gas/arm/armv8-r.d: New. * testsuite/gas/arm/attr-march-armv8-r+crypto.d: New. * testsuite/gas/arm/attr-march-armv8-r+fp.d: New. * testsuite/gas/arm/attr-march-armv8-r+simd.d: New. * testsuite/gas/arm/attr-march-armv8-r.d: New. * testsuite/gas/arm/crc32.s: Rename into ... * testsuite/gas/arm/crc32-armv8-ar.s: This. * testsuite/gas/arm/crc32.d: Rename into ... * testsuite/gas/arm/crc32-armv8-a.d: This. Specify source to assemble. * testsuite/gas/arm/crc32-armv8-r.d: New. * testsuite/gas/arm/crc32-bad.s: Rename into ... * testsuite/gas/arm/crc32-armv8-ar-bad.s: This. * testsuite/gas/arm/crc32-bad.d: Rename into ... * testsuite/gas/arm/crc32-armv8-a-bad.d: This. Specify source to assemble. * testsuite/gas/arm/crc32-armv8-r-bad.d: New. * testsuite/gas/arm/mask_1.s: Rename into ... * testsuite/gas/arm/mask_1-armv8-ar.s: This. * testsuite/gas/arm/mask_1.d: Rename into ... * testsuite/gas/arm/mask_1-armv8-a.d: This. Specify source to assemble. * testsuite/gas/arm/mask_1-armv8-r.d: new. include/ * elf/arm.h (TAG_CPU_ARCH_V8R): New macro. * opcode/arm.h (ARM_EXT2_V8A): New macro. (ARM_AEXT2_V8A): Rename into ... (ARM_AEXT2_V8AR): This. (ARM_AEXT2_V8A): New macro. (ARM_AEXT_V8R): New macro. (ARM_AEXT2_V8R): New macro. (ARM_ARCH_V8R): New macro. |
||
|
James Greenhalgh
|
1e29262747 |
Add support for the Cortex-A55 and Cortex-A75 versions of the AArch64 architecture.
* config/tc-aarch64.c (aarch64_cpus): Add cortex-a55 and cortex-a75. * doc/c-aarch64.texi (-mcpu): Document cortex-a55 and cortex-a75. |
||
Jim Wilson
|
61756f84ee |
Drop arm support for falkor/qdf24xx targets, not present in released hardware.
gas/ * config/tc-arm.c (arm_cpus): Delete falkor and qdf24xx entries. * doc/c-arm.texi (-mcpu): Likewise. |
||
Jose E. Marchesi
|
6451799480 |
binutils: support for the SPARC M8 processor
This patch adds support for the new SPARC M8 processor (implementing OSA
2017) to binutils.
New instructions:
- Dictionary Unpack
+ dictunpack
- Partitioned Compare with shifted result
+ Signed variants: fpcmp{le,gt,eq,ne}{8,16,32}shl
+ Unsigned variants: fpcmpu{le,gt}{8,16,32}shl
- Partitioned Dual-Equal compared, with shifted result
+ fpcmpde{8,16,32}shl
- Partitioned Unsigned Range Compare, with shifted result
+ fpcmpur{8,16,32}shl
- 64-bit shifts on Floating-Point registers
+ fps{ll,ra,rl}64x
- Misaligned loads and stores
+ ldm{sh,uh,sw,uw,x,ux}
+ ldm{sh,uh,sw,uw,x,ux}a
+ ldmf{s,d}
+ ldmf{s,d}a
+ stm{h,w,x}
+ stm{h,w,x}a
+ stmf{s,d}
+ stmf{s,d}a
- Oracle Numbers
+ on{add,sub,mul,div}
- Reverse Bytes/Bits
+ revbitsb
+ revbytes{h,w,x}
- Run-Length instructions
+ rle_burst
+ rle_length
- New crypto instructions
+ sha3
- Instruction to read the new register %entropy
+ rd %entropy
New Alternate Address Identifiers:
- 0x24, #ASI_CORE_COMMIT_COUNT
- 0x24, #ASI_CORE_SELECT_COUNT
- 0x48, #ASI_ARF_ECC_REG
- 0x53, #ASI_ITLB_PROBE
- 0x58, #ASI_DSFAR
- 0x5a, #ASI_DTLB_PROBE_PRIMARY
- 0x5b, #ASI_DTLB_PROBE_REAL
- 0x64, #ASI_CORE_SELECT_COMMIT_NHT
The new assembler command-line options for selecting the M8 architecture
are:
-Av9m8 or -Asparc6 for 64-bit binaries.
-Av8plusm8 for 32-bit (v8+) binaries.
The corresponding disassembler command-line options are:
-msparc:v9m8 for 64-bit binaries.
-msparc:v8plusm8 for 32-bit (v8+) binaries.
Tested for regressions in the following targets:
sparc-aout sparc-linux sparc-vxworks sparc64-linux
bfd/ChangeLog:
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* archures.c (bfd_mach_sparc_v9m8): Define.
(bfd_mach_sparc_v8plusm8): Likewise.
(bfd_mach_sparc_v9_p): Adjust to M8.
(bfd_mach_sparc_64bit_p): Likewise.
* aoutx.h (machine_type): Handle bfd_mach_sparc_v9m8 and
bfd_mach_sparc_v8plusm8.
* bfd-in2.h: Regenerated.
* cpu-sparc.c (arch_info_struct): Entries for sparc:v9m8 and
sparc:v8plusm8.
* elfxx-sparc.c (_bfd_sparc_elf_object_p): Handle
bfd_mach_sparc_v8plusm8 and bfd_mach_sparc_v9m8 using the new hw
capabilities ONADDSUB, ONMUL, ONDIV, DICTUNP, FPCPSHL, RLE and
SHA3.
* elf32-sparc.c (elf32_sparc_final_write_processing): Handle
bfd_mach_sparc_v8plusm8.
binutils/ChangeLog:
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* NEWS: Mention the SPARC M8 support.
gas/ChangeLog:
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_arch_table): Entries for `sparc6',
`v9m8' and `v8plusm8'.
(sparc_md_end): Handle SPARC_OPCODE_ARCH_M8.
(get_hwcap_name): Support the M8 hardware capabilities.
(sparc_ip): Handle new operand types.
* doc/c-sparc.texi (Sparc-Opts): Document -Av9m8, -Av8plusm8 and
-Asparc6, and the corresponding -xarch aliases.
* testsuite/gas/sparc/sparc6.s: New file.
* testsuite/gas/sparc/sparc6.d: Likewise.
* testsuite/gas/sparc/sparc6-diag.s: Likewise.
* testsuite/gas/sparc/sparc6-diag.l: Likewise.
* testsuite/gas/sparc/fpcmpshl.s: Likewise.
* testsuite/gas/sparc/fpcmpshl.d: Likewise.
* testsuite/gas/sparc/fpcmpshl-diag.s: Likewise.
* testsuite/gas/sparc/fpcmpshl-diag.l: Likewise.
* testsuite/gas/sparc/ldm-stm.s: Likewise.
* testsuite/gas/sparc/ldm-stm.d: Likewise.
* testsuite/gas/sparc/ldm-stm-diag.s: Likewise.
* testsuite/gas/sparc/ldm-stm-diag.l: Likewise.
* testsuite/gas/sparc/ldmf-stmf.s: Likewise.
* testsuite/gas/sparc/ldmf-stmf.d: Likewise.
* testsuite/gas/sparc/ldmf-stmf-diag.s: Likewise.
* testsuite/gas/sparc/ldmf-stmf-diag.l: Likewise.
* testsuite/gas/sparc/on.s: Likewise.
* testsuite/gas/sparc/on.d: Likewise.
* testsuite/gas/sparc/on-diag.s: Likewise.
* testsuite/gas/sparc/on-diag.l: Likewise.
* testsuite/gas/sparc/rle.s: Likewise.
* testsuite/gas/sparc/rle.d: Likewise.
* testsuite/gas/sparc/sparc.exp (gas_64_check): Run new tests.
* testsuite/gas/sparc/rdasr.s: Add test for RDENTROPY.
* testsuite/gas/sparc/rdasr.d: Likewise.
include/ChangeLog:
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* elf/sparc.h (ELF_SPARC_HWCAP2_SPARC6): Define.
(ELF_SPARC_HWCAP2_ONADDSUB): Likewise.
(ELF_SPARC_HWCAP2_ONMUL): Likewise.
(ELF_SPARC_HWCAP2_ONDIV): Likewise.
(ELF_SPARC_HWCAP2_DICTUNP): Likewise.
(ELF_SPARC_HWCAP2_FPCMPSHL): Likewise.
(ELF_SPARC_HWCAP2_RLE): Likewise.
(ELF_SPARC_HWCAP2_SHA3): Likewise.
* opcode/sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_M8
and adjust SPARC_OPCODE_ARCH_MAX.
(HWCAP2_SPARC6): Define.
(HWCAP2_ONADDSUB): Likewise.
(HWCAP2_ONMUL): Likewise.
(HWCAP2_ONDIV): Likewise.
(HWCAP2_DICTUNP): Likewise.
(HWCAP2_FPCMPSHL): Likewise.
(HWCAP2_RLE): Likewise.
(HWCAP2_SHA3): Likewise.
(OPM): Likewise.
(OPMI): Likewise.
(ONFCN): Likewise.
(REVFCN): Likewise.
(SIMM10): Likewise.
opcodes/ChangeLog:
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
(X_IMM2): Define.
(compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
bfd_mach_sparc_v9m8.
(print_insn_sparc): Handle new operand types.
* sparc-opc.c (MASK_M8): Define.
(v6): Add MASK_M8.
(v6notlet): Likewise.
(v7): Likewise.
(v8): Likewise.
(v9): Likewise.
(v9a): Likewise.
(v9b): Likewise.
(v9c): Likewise.
(v9d): Likewise.
(v9e): Likewise.
(v9v): Likewise.
(v9m): Likewise.
(v9andleon): Likewise.
(m8): Define.
(HWS_VM8): Define.
(HWS2_VM8): Likewise.
(sparc_opcode_archs): Add entry for "m8".
(sparc_opcodes): Add OSA2017 and M8 instructions
dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
fpx{ll,ra,rl}64x,
ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
(asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
ASI_CORE_SELECT_COMMIT_NHT.
|
||
|
Maciej W. Rozycki
|
25499ac7ee |
MIPS16e2: Add MIPS16e2 ASE support
Add MIPS16e2 ASE support as per the architecture specification[1],
including in particular:
1. A new ELF ASE flag to mark MIPS16e2 binaries.
2. MIPS16e2 instruction assembly support, including a relaxation update
to use LUI rather than an LI/SLL instruction pair for loading the
high part of 32-bit addresses.
3. MIPS16e2 instruction disassembly support, including updated rules for
extended forms of instructions that are now subdecoded and therefore
do not alias to the original MIPS16 ISA revision instructions even
for encodings that are not valid in the MIPS16e2 instruction set.
Add `-mmips16e2' and `-mno-mips16e2' GAS command-line options and their
corresponding `mips16e2' and `no-mips16e2' settings for the `.set' and
`.module' pseudo-ops. Control the availability of the MT ASE subset of
the MIPS16e2 instruction set with a combination of these controls and
the preexisting MT ASE controls.
Parts of this change by Matthew Fortune and Andrew Bennett.
References:
[1] "MIPS32 Architecture for Programmers: MIPS16e2 Application-Specific
Extension Technical Reference Manual", Imagination Technologies
Ltd., Document Number: MD01172, Revision 01.00, April 26, 2016
include/
* elf/mips.h (AFL_ASE_MIPS16E2): New macro.
(AFL_ASE_MASK): Adjust accordingly.
* opcode/mips.h: Document new operand codes defined.
(mips_operand_type): Add OP_REG28 enum value.
(INSN2_SHORT_ONLY): Update description.
(ASE_MIPS16E2, ASE_MIPS16E2_MT): New macros.
bfd/
* elfxx-mips.c (print_mips_ases): Handle MIPS16e2 ASE.
opcodes/
* mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
(mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
(print_insn_arg) <OP_REG28>: Add handler.
(validate_insn_args) <OP_REG28>: Handle.
(print_mips16_insn_arg): Handle MIPS16 instructions that require
32-bit encoding and 9-bit immediates.
(print_insn_mips16): Handle MIPS16 instructions that require
32-bit encoding and MFC0/MTC0 operand decoding.
* mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
<'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
(RD_C0, WR_C0, E2, E2MT): New macros.
(mips16_opcodes): Add entries for MIPS16e2 instructions:
GP-relative "addiu" and its "addu" spelling, "andi", "cache",
"di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
"lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
"movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
"pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
instructions, "swl", "swr", "sync" and its "sync_acquire",
"sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
"xori", "dmt", "dvpe", "emt" and "evpe". Add split
regular/extended entries for original MIPS16 ISA revision
instructions whose extended forms are subdecoded in the MIPS16e2
ISA revision: "li", "sll" and "srl".
binutils/
* readelf.c (print_mips_ases): Handle MIPS16e2 ASE.
* NEWS: Mention MIPS16e2 ASE support.
gas/
* config/tc-mips.c (RELAX_MIPS16_ENCODE): Add `e2' flag.
(RELAX_MIPS16_E2): New macro.
(RELAX_MIPS16_PIC, RELAX_MIPS16_SYM32, RELAX_MIPS16_NOMACRO)
(RELAX_MIPS16_USER_SMALL, RELAX_MIPS16_USER_EXT)
(RELAX_MIPS16_DSLOT, RELAX_MIPS16_JAL_DSLOT)
(RELAX_MIPS16_EXTENDED, RELAX_MIPS16_MARK_EXTENDED)
(RELAX_MIPS16_CLEAR_EXTENDED, RELAX_MIPS16_ALWAYS_EXTENDED)
(RELAX_MIPS16_MARK_ALWAYS_EXTENDED)
(RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED, RELAX_MIPS16_MACRO)
(RELAX_MIPS16_MARK_MACRO, RELAX_MIPS16_CLEAR_MACRO): Shift bits.
(mips16_immed_extend): New prototype.
(options): Add OPTION_MIPS16E2 and OPTION_NO_MIPS16E2 enum
values.
(md_longopts): Add "mmips16e2" and "mno-mips16e2" options.
(mips_ases): Add "mips16e2" entry.
(mips_set_ase): Handle MIPS16e2 ASE.
(insn_insert_operand): Explicitly handle immediates with MIPS16
instructions that require 32-bit encoding.
(is_opcode_valid_16): Pass enabled ASE bitmask on to
`opcode_is_member'.
(validate_mips_insn): Explicitly handle immediates with MIPS16
instructions that require 32-bit encoding.
(operand_reg_mask) <OP_REG28>: Add handler.
(match_reg28_operand): New function.
(match_operand) <OP_REG28>: Add handler.
(append_insn): Pass ASE_MIPS16E2 setting to RELAX_MIPS16_ENCODE.
(match_mips16_insn): Handle MIPS16 instructions that require
32-bit encoding and `V' and `u' operand codes.
(mips16_ip): Allow any characters except from `.' in opcodes.
(mips16_immed_extend): Handle 9-bit immediates. Do not shuffle
immediates whose width is not one of these listed.
(md_estimate_size_before_relax): Handle MIPS16e2 relaxation.
(mips_relax_frag): Likewise.
(md_convert_frag): Likewise.
(mips_convert_ase_flags): Handle MIPS16e2 ASE.
* doc/as.texinfo (Target MIPS options): Add `-mmips16e2' and
`-mno-mips16e2' options.
(-mmips16e2, -mno-mips16e2): New options.
* doc/c-mips.texi (MIPS Options): Add `-mmips16e2' and
`-mno-mips16e2' options.
(MIPS ASE Instruction Generation Overrides): Add `.set mips16e2'
and `.set nomips16e2'.
|
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|
Maciej W. Rozycki
|
32035f5151 |
MIPS/GAS/doc: Refer to .module' rather than .set'
Complement commit
|
||
Claudiu Zissulescu
|
53a346d823 |
[ARC] Object attributes.
gas/ 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/attr-arc600.d: New file. * testsuite/gas/arc/attr-arc600_mul32x16.d: Likewise. * testsuite/gas/arc/attr-arc600_norm.d: Likewise. * testsuite/gas/arc/attr-arc601.d: Likewise. * testsuite/gas/arc/attr-arc601_mul32x16.d: Likewise. * testsuite/gas/arc/attr-arc601_mul64.d: Likewise. * testsuite/gas/arc/attr-arc601_norm.d: Likewise. * testsuite/gas/arc/attr-arc700.d: Likewise. * testsuite/gas/arc/attr-arcem.d: Likewise. * testsuite/gas/arc/attr-archs.d: Likewise. * testsuite/gas/arc/attr-autodetect-1.d: Likewise. * testsuite/gas/arc/attr-autodetect-1.s: Likewise. * testsuite/gas/arc/attr-cpu-a601.d: Likewise. * testsuite/gas/arc/attr-cpu-a601.s: Likewise. * testsuite/gas/arc/attr-cpu-a700.d: Likewise. * testsuite/gas/arc/attr-cpu-a700.s: Likewise. * testsuite/gas/arc/attr-cpu-em.d: Likewise. * testsuite/gas/arc/attr-cpu-em.s: Likewise. * testsuite/gas/arc/attr-cpu-hs.d: Likewise. * testsuite/gas/arc/attr-cpu-hs.s: Likewise. * testsuite/gas/arc/attr-em.d: Likewise. * testsuite/gas/arc/attr-em4.d: Likewise. * testsuite/gas/arc/attr-em4_dmips.d: Likewise. * testsuite/gas/arc/attr-em4_fpuda.d: Likewise. * testsuite/gas/arc/attr-em4_fpus.d: Likewise. * testsuite/gas/arc/attr-hs.d: Likewise. * testsuite/gas/arc/attr-hs34.d: Likewise. * testsuite/gas/arc/attr-hs38.d: Likewise. * testsuite/gas/arc/attr-hs38_linux.d: Likewise. * testsuite/gas/arc/attr-mul64.d: Likewise. * testsuite/gas/arc/attr-name.d: Likewise. * testsuite/gas/arc/attr-name.s: Likewise. * testsuite/gas/arc/attr-nps400.d: Likewise. * testsuite/gas/arc/attr-override-mcpu.d: Likewise. * testsuite/gas/arc/attr-override-mcpu.s * testsuite/gas/arc/attr-quarkse_em.d: Likewise. * testsuite/gas/arc/blank.s: Likewise. * testsuite/gas/elf/section2.e-arc: Likewise. * testsuite/gas/arc/cpu-pseudop-1.d: Update test. * testsuite/gas/arc/cpu-pseudop-2.d: Likewise. * testsuite/gas/arc/nps400-0.d: Likewise. * testsuite/gas/elf/elf.exp: Set target_machine for ARC. * config/tc-arc.c (opcode/arc-attrs.h): Include. (ARC_GET_FLAG, ARC_SET_FLAG, streq): Define. (arc_attribute): Declare new function. (md_pseudo_table): Add arc_attribute. (cpu_types): Rename default cpu features. (selected_cpu): Set the default OSABI flag. (mpy_option): New variable. (pic_option): Likewise. (sda_option): Likewise. (tls_option): Likewise. (feature_type, feature_list): Remove. (arc_initial_eflag): Likewise. (attributes_set_explicitly): New variable. (arc_check_feature): Check also for the conflicting features. (arc_select_cpu): Refactor assignment of selected_cpu.eflags. (arc_option): Remove setting of private flags and architecture. (check_cpu_feature): Refactor feature names. (autodetect_attributes): New function. (assemble_tokens): Use above function. (md_parse_option): Refactor feature names. (arc_attribute): New function. (arc_set_attribute_int): Likewise. (arc_set_attribute_string): Likewise. (arc_stralloc): Likewise. (arc_set_public_attributes): Likewise. (arc_md_end): Likewise. (arc_copy_symbol_attributes): Likewise. (rc_convert_symbolic_attribute): Likewise. * config/tc-arc.h (md_end): Define. (CONVERT_SYMBOLIC_ATTRIBUTE): Likewise. (TC_COPY_SYMBOL_ATTRIBUTES): Likewise. * doc/c-arc.texi: Document ARC object attributes. binutils/ 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> * readelf.c (decode_ARC_machine_flags): Recognize OSABI v4. (get_arc_section_type_name): New function. (get_section_type_name): Use the above function. (display_arc_attribute): New function. (process_arc_specific): Likewise. (process_arch_specific): Handle ARC specific information. * testsuite/binutils-all/strip-3.d: Consider ARC.attributes section. include/ 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> * elf/arc.h (SHT_ARC_ATTRIBUTES): Define. (Tag_ARC_*): Define. (E_ARC_OSABI_V4): Define. (E_ARC_OSABI_CURRENT): Reassign it. (TAG_CPU_*): Define. * opcode/arc-attrs.h: New file. * opcode/arc.h (insn_subclass_t): Assign enum values. (insn_subclass_t): Update enum with QUARKSE1, QUARKSE2, and LL64. (ARC_EA, ARC_CD, ARC_LLOCK, ARC_ATOMIC, ARC_MPY, ARC_MULT) (ARC_NPS400, ARC_DPFP, ARC_SPFP, ARC_FPU, ARC_FPUDA, ARC_SWAP) (ARC_NORM, ARC_BSCAN, ARC_UIX, ARC_TSTAMP, ARC_VBFDW) (ARC_BARREL, ARC_DSPA, ARC_SHIFT, ARC_INTR, ARC_DIV, ARC_XMAC) (ARC_CRC): Delete. bfd/ 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> * elf32-arc.c (FEATURE_LIST_NAME): Define. (CONFLICT_LIST): Likewise. (opcode/arc-attrs.h): Include. (arc_elf_print_private_bfd_data): Print OSABI v4 flag. (arc_extract_features): New file. (arc_stralloc): Likewise. (arc_elf_merge_attributes): Likewise. (arc_elf_merge_private_bfd_data): Use object attributes. (bfd_arc_get_mach_from_attributes): New function. (arc_elf_object_p): Use object attributes. (arc_elf_final_write_processing): Likewise. (elf32_arc_obj_attrs_arg_type): New function. (elf32_arc_obj_attrs_handle_unknown): Likewise. (elf32_arc_section_from_shdr): Likewise. (elf_backend_obj_attrs_vendor): Define. (elf_backend_obj_attrs_section): Likewise. (elf_backend_obj_attrs_arg_type): Likewise. (elf_backend_obj_attrs_section_type): Likewise. (elf_backend_obj_attrs_handle_unknown): Likewise. (elf_backend_section_from_shdr): Likewise. ld/ 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/ld-arc/attr-merge-0.d: New file. * testsuite/ld-arc/attr-merge-0.s: Likewise. * testsuite/ld-arc/attr-merge-0e.s: Likewise. * testsuite/ld-arc/attr-merge-1.d: Likewise. * testsuite/ld-arc/attr-merge-1.s: Likewise. * testsuite/ld-arc/attr-merge-1e.s: Likewise. * testsuite/ld-arc/attr-merge-2.d: Likewise. * testsuite/ld-arc/attr-merge-2.s: Likewise. * testsuite/ld-arc/attr-merge-3.d: Likewise. * testsuite/ld-arc/attr-merge-3.s: Likewise. * testsuite/ld-arc/attr-merge-3e.s: Likewise. * testsuite/ld-arc/attr-merge-4.s: Likewise. * testsuite/ld-arc/attr-merge-5.d: Likewise. * testsuite/ld-arc/attr-merge-5a.s: Likewise. * testsuite/ld-arc/attr-merge-5b.s: Likewise. * testsuite/ld-arc/attr-merge-conflict-isa.d: Likewise. * testsuite/ld-arc/attr-merge-err-isa.d: Likewise. * testsuite/ld-arc/attr-merge-incompatible-cpu.d: Likewise. * testsuite/ld-arc/got-01.d: Update test. * testsuite/ld-arc/attr-merge-err-quarkse.d: New file. * testsuite/ld-arc/attr-quarkse.s: Likewise. * testsuite/ld-arc/attr-quarkse2.s: Likewise. opcodes/ 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> * arc-dis.c (parse_option): Update quarkse_em option.. * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to QUARKSE1. (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2. |
||
H.J. Lu
|
a91e1603af |
Support ELF SHF_GNU_MBIND and PT_GNU_MBIND_XXX
Mark an ALLOC section, which should be placed in special memory area,
with SHF_GNU_MBIND. Its sh_info field indicates the special memory
type. GNU_MBIND section names start with ".mbind" so that they are
placed as orphan sections by linker. All input GNU_MBIND sections
with the same sh_type, sh_flags and sh_info are placed in one output
GNU_MBIND section. In executable and shared object, create a
GNU_MBIND segment for each GNU_MBIND section and its segment type is
PT_GNU_MBIND_LO plus the sh_info value. Each GNU_MBIND segment is
aligned at page boundary.
The assembler syntax:
.section .mbind.foo,"adx",%progbits
^ 0: Special memory type.
|
'd' for SHF_GNU_MBIND.
.section .mbind.foo,"adx",%progbits,0x1
^ 1: Special memory type.
|
'd' for SHF_GNU_MBIND.
.section .mbind.bar,"adG",%progbits,.foo_group,comdat,0x2
^ 2: Special memory type.
|
'd' for SHF_GNU_MBIND.
bfd/
* elf.c (get_program_header_size): Add a GNU_MBIND segment for
each GNU_MBIND section and align GNU_MBIND section to page size.
(_bfd_elf_map_sections_to_segments): Create a GNU_MBIND
segment for each GNU_MBIND section.
(_bfd_elf_init_private_section_data): Copy sh_info from input
for GNU_MBIND section.
binutils/
* NEWS: Mention support for ELF SHF_GNU_MBIND and
PT_GNU_MBIND_XXX.
* readelf.c (get_segment_type): Handle PT_GNU_MBIND_XXX.
(get_elf_section_flags): Handle SHF_GNU_MBIND.
(process_section_headers): Likewise.
* testsuite/binutils-all/mbind1.s: New file.
* testsuite/binutils-all/objcopy.exp: Run readelf test on
mbind1.s.
gas/
* NEWS: Mention support for ELF SHF_GNU_MBIND.
* config/obj-elf.c (section_match): New.
(get_section): Match both sh_info and group name.
(obj_elf_change_section): Add argument for sh_info. Pass both
sh_info and group name to get_section. Issue an error for
SHF_GNU_MBIND section without SHF_ALLOC. Set sh_info.
(obj_elf_parse_section_letters): Set SHF_GNU_MBIND for 'd'.
(obj_elf_section): Support SHF_GNU_MBIND section info.
* config/obj-elf.h (obj_elf_change_section): Add argument for
sh_info.
* config/tc-arm.c (start_unwind_section): Pass 0 as sh_info to
obj_elf_change_section.
* config/tc-ia64.c (obj_elf_vms_common): Likewise.
* config/tc-microblaze.c (microblaze_s_data): Likewise.
(microblaze_s_sdata): Likewise.
(microblaze_s_rdata): Likewise.
(microblaze_s_bss): Likewise.
* config/tc-mips.c (s_change_section): Likewise.
* config/tc-msp430.c (msp430_profiler): Likewise.
* config/tc-rx.c (parse_rx_section): Likewise.
* config/tc-tic6x.c (tic6x_start_unwind_section): Likewise.
* doc/as.texinfo: Document 'd' for SHF_GNU_MBIND.
* testsuite/gas/elf/elf.exp: Run section12a, section12b and
section13.
* testsuite/gas/elf/section10.d: Updated.
* testsuite/gas/elf/section10.s: Likewise.
* testsuite/gas/elf/section12.s: New file.
* testsuite/gas/elf/section12a.d: Likewise.
* testsuite/gas/elf/section12b.d: Likewise.
* testsuite/gas/elf/section13.l: Likewise.
* testsuite/gas/elf/section13.d: Likewise.
* testsuite/gas/elf/section13.s: Likewise.
include/
* elf/common.h (PT_GNU_MBIND_NUM): New.
(PT_GNU_MBIND_LO): Likewise.
(PT_GNU_MBIND_HI): Likewise.
(SHF_GNU_MBIND): Likewise.
ld/
* NEWS: Mention support for ELF SHF_GNU_MBIND and
PT_GNU_MBIND_XXX.
* emultempl/elf32.em (gld${EMULATION_NAME}_place_orphan): Place
input GNU_MBIND sections with the same type, attributes and
sh_info field into a single output GNU_MBIND section.
* testsuite/ld-elf/elf.exp: Run mbind2a and mbind2b.
* testsuite/ld-elf/mbind1.s: New file.
* testsuite/ld-elf/mbind1a.d: Likewise.
* testsuite/ld-elf/mbind1b.d: Likewise.
* testsuite/ld-elf/mbind1c.d: Likewise.
* testsuite/ld-elf/mbind2a.s: Likewise.
* testsuite/ld-elf/mbind2b.c: Likewise.
|
||
Pip Cet
|
f96bd6c2d7 |
Add support for the WebAssembly file format and the wasm32 ELF conversion to gas and the binutils.
binutils * readelf.c: Add support for wasm32 ELF format WebAssembly files. (guess_is_rela): Likewise. (dump_relocations): Likewise. (is_32bit_abs_reloc): Likewise. (is_none_reloc_): Likewise. * NEWS: Mention the new support. * testsuite/lib/binutils-common.exp (is_elf_format): Mark wasm32 as ELF target. (supports_gnu_unique): Mark wasm32 as supporting STB_GNU_UNIQUE. * testsuite/binutils-all/nm.exp: Mark wasm32 as requiring .size annotations. * testsuite/binutils-all/wasm32: New directory. * testsuite/binutils-all/wasm32/create-wasm.d: New file. * testsuite/binutils-all/wasm32/create-wasm.s: Likewise. * testsuite/binutils-all/wasm32/custom-section.d: Likewise. * testsuite/binutils-all/wasm32/custom-section.s: Likewise. * testsuite/binutils-all/wasm32/invalid-wasm-1.d: Likewise. * testsuite/binutils-all/wasm32/invalid-wasm-1.s: Likewise. * testsuite/binutils-all/wasm32/long-sections.d: Likewise. * testsuite/binutils-all/wasm32/long-sections.s: Likewise. * testsuite/binutils-all/wasm32/parse-wasm.d: Likewise. * testsuite/binutils-all/wasm32/parse-wasm.s: Likewise. * testsuite/binutils-all/wasm32/parse-wasm-2.d: Likewise. * testsuite/binutils-all/wasm32/parse-wasm-2.s: Likewise. * testsuite/binutils-all/wasm32/prepared-section.d: Likewise. * testsuite/binutils-all/wasm32/prepared-section.s: Likewise. * testsuite/binutils-all/wasm32/wasm32.exp: New file, run tests. gas * config/tc-wasm32.h: New file: Add WebAssembly assembler target. * config/tc-wasm32.c: New file: Add WebAssembly assembler target. * Makefile.am: Add WebAssembly assembler target. * configure.tgt: Add WebAssembly assembler target. * doc/c-wasm32.texi: New file: Start documenting WebAssembly assembler. * doc/all.texi: Define WASM32. * doc/as.texinfo: Add WebAssembly entries. * NEWS: Mention the new support. * Makefile.in: Regenerate. * po/gas.pot: Regenerate. * po/POTFILES.in: Regenerate. * testsuite/gas/wasm32: New directory. * testsuite/gas/wasm32/allinsn.d: New file. * testsuite/gas/wasm32/allinsn.s: New file. * testsuite/gas/wasm32/illegal.l: New file. * testsuite/gas/wasm32/illegal.s: New file. * testsuite/gas/wasm32/illegal-2.l: New file. * testsuite/gas/wasm32/illegal-2.s: New file. * testsuite/gas/wasm32/illegal-3.l: New file. * testsuite/gas/wasm32/illegal-3.s: New file. * testsuite/gas/wasm32/illegal-4.l: New file. * testsuite/gas/wasm32/illegal-4.s: New file. * testsuite/gas/wasm32/illegal-5.l: New file. * testsuite/gas/wasm32/illegal-5.s: New file. * testsuite/gas/wasm32/illegal-6.l: New file. * testsuite/gas/wasm32/illegal-6.s: New file. * testsuite/gas/wasm32/illegal-7.l: New file. * testsuite/gas/wasm32/illegal-7.s: New file. * testsuite/gas/wasm32/illegal-8.l: New file. * testsuite/gas/wasm32/illegal-8.s: New file. * testsuite/gas/wasm32/illegal-9.l: New file. * testsuite/gas/wasm32/illegal-9.s: New file. * testsuite/gas/wasm32/illegal-10.l: New file. * testsuite/gas/wasm32/illegal-10.s: New file. * testsuite/gas/wasm32/illegal-11.l: New file. * testsuite/gas/wasm32/illegal-11.s: New file. * testsuite/gas/wasm32/illegal-12.l: New file. * testsuite/gas/wasm32/illegal-12.s: New file. * testsuite/gas/wasm32/illegal-13.l: New file. * testsuite/gas/wasm32/illegal-13.s: New file. * testsuite/gas/wasm32/illegal-14.l: New file. * testsuite/gas/wasm32/illegal-14.s: New file. * testsuite/gas/wasm32/illegal-15.l: New file. * testsuite/gas/wasm32/illegal-15.s: New file. * testsuite/gas/wasm32/illegal-16.l: New file. * testsuite/gas/wasm32/illegal-16.s: New file. * testsuite/gas/wasm32/illegal-17.l: New file. * testsuite/gas/wasm32/illegal-17.s: New file. * testsuite/gas/wasm32/illegal-18.l: New file. * testsuite/gas/wasm32/illegal-18.s: New file. * testsuite/gas/wasm32/illegal-19.l: New file. * testsuite/gas/wasm32/illegal-19.s: New file. * testsuite/gas/wasm32/illegal-20.l: New file. * testsuite/gas/wasm32/illegal-20.s: New file. * testsuite/gas/wasm32/illegal-21.l: New file. * testsuite/gas/wasm32/illegal-21.s: New file. * testsuite/gas/wasm32/illegal-22.l: New file. * testsuite/gas/wasm32/illegal-22.s: New file. * testsuite/gas/wasm32/illegal-24.l: New file. * testsuite/gas/wasm32/illegal-24.s: New file. * testsuite/gas/wasm32/illegal-25.l: New file. * testsuite/gas/wasm32/illegal-25.s: New file. * testsuite/gas/wasm32/reloc.d: New file. * testsuite/gas/wasm32/reloc.s: New file. * testsuite/gas/wasm32/wasm32.exp: New tests for WebAssembly architecture. opcodes * configure.ac: Add (empty) bfd_wasm32_arch target. * configure: Regenerate * po/opcodes.pot: Regenerate. include * opcode/wasm.h: New file to support wasm32 architecture. * elf/wasm32.h: Add R_WASM32_32 relocation. bfd * elf32-wasm32.c: Add relocation code, two relocs. * reloc.c: Add wasm32 relocations. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate. * bfd/po/bfd.pot: Regenerate. |
||
Palmer Dabbelt
|
19683c0408 |
Sanitize RISC-V GAS help text, documentation
It looks like I missed the GAS help text when going through all the documentation last time, so it printed some of the old-format (never upstream) arguments. I fixed this, and when I went to check doc/ I noticed it was missing the '-fpic'/'-fno-pic' options. |
||
|
Nick Clifton
|
e406e428df |
Update descriptions of the .2byte, .4byte and .8byte directives.
* doc/as.texinfo (2byte): Note that if no expressions are present the directive does nothing. Emphasize that the output is unaligned, and that this can have an effect on the relocations generated. (4byte): Simplify description. Refer back to the 2byte description. (8byte): Likewise. |
||
Richard Earnshaw
|
d5e0ba9cdb |
[arm] Document missing -mfpu entries.
Nick pointed out that I hadn't documented the new -mfpu option neon-vfpv3 and mentioned that some others were missing. Having looked through the list only one (neon-fp16) really should be documented; the other two entries in the real table should not be documented as they are aliases kept for legacy compatibility reasons. This patch adds the missing entries and notes in the main table that the other two entries should not be documented. I've also fixed a small spelling error in the accompanying text. * config/tc-arm.c (arm_fpus): Note entires that should not be documented. * doc/c-arm.texi (-mfpu): Add missing FPU entries for neon-vfpv3 and neon-fp16. Fix spelling error. |
||
|
Nick Clifton
|
8b1e5da10a |
Document that the .2byte and .4byte directives warn about overlarge values.
* doc/as.texinfo (2byte): Tidy up wording. Add note that overlarge values will produce a warning message and be trunacted. (4byte): Likewise. |
||
|
H.J. Lu
|
86fa6981e7 |
X86: Add pseudo prefixes to control encoding
Many x86 instructions have more than one encodings. Assembler picks
the default one, usually the shortest one. Although the ".s", ".d8"
and ".d32" suffixes can be used to swap register operands or specify
displacement size, they aren't very flexible. This patch adds pseudo
prefixes, {xxx}, to control instruction encoding. The available
pseudo prefixes are {disp8}, {disp32}, {load}, {store}, {vex2}, {vex3}
and {evex}. Pseudo prefixes are preferred over the ".s", ".d8" and
".d32" suffixes, which are deprecated.
gas/
* config/tc-i386.c (_i386_insn): Add dir_encoding and
vec_encoding. Remove swap_operand and need_vrex.
(extra_symbol_chars): Add '}'.
(md_begin): Mark '}' with LEX_BEGIN_NAME. Allow '}' in
mnemonic.
(build_vex_prefix): Don't use 2-byte VEX encoding with
{vex3}. Check dir_encoding and load.
(parse_insn): Check pseudo prefixes. Set dir_encoding.
(VEX_check_operands): Likewise.
(match_template): Check dir_encoding and load.
(parse_real_register): Set vec_encoding instead of need_vrex.
(parse_register): Likewise.
* doc/c-i386.texi: Document {disp8}, {disp32}, {load}, {store},
{vex2}, {vex3} and {evex}. Remove ".s", ".d8" and ".d32"
* testsuite/gas/i386/i386.exp: Run pseudos and x86-64-pseudos.
* testsuite/gas/i386/pseudos.d: New file.
* testsuite/gas/i386/pseudos.s: Likewise.
* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
* testsuite/gas/i386/x86-64-pseudos.s: Likewise.
opcodes/
* i386-gen.c (opcode_modifiers): Replace S with Load.
* i386-opc.h (S): Removed.
(Load): New.
(i386_opcode_modifier): Replace s with load.
* i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
and {evex}. Replace S with Load.
* i386-tbl.h: Regenerated.
|
||
|
Alan Modra
|
ea86f53442 |
Correct @section placement for makeinfo 4.13
* doc/as.texinfo (2byte, 4byte, 8byte): Correct @section placement. |
||
|
Alan Modra
|
2b841ec206 |
Document .Nbyte assembler directives
* doc/as.texinfo (2byte, 4byte, 8byte): Document. * doc/c-arm.texi (2byte, 4byte, 8byte): Omit if ELF. |
||
|
H.J. Lu
|
603555e563 |
Add support for Intel CET instructions
Support Intel Control-flow Enforcement Technology (CET) instructions: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf gas/ * config/tc-i386.c (cpu_arch): Add .cet. * doc/c-i386.texi: Document cet. * testsuite/gas/i386/cet-intel.d: New file. * testsuite/gas/i386/cet.d: Likewise. * testsuite/gas/i386/cet.s: Likewise. * testsuite/gas/i386/x86-64-cet-intel.d: Likewise. * testsuite/gas/i386/x86-64-cet.d: Likewise. * testsuite/gas/i386/x86-64-cet.s: Likewise. * testsuite/gas/i386/i386.exp: Run Intel CET tests. opcodes/ * i386-dis.c (REG_0F1E_MOD_3): New enum. (MOD_0F1E_PREFIX_1): Likewise. (MOD_0F38F5_PREFIX_2): Likewise. (MOD_0F38F6_PREFIX_0): Likewise. (RM_0F1E_MOD_3_REG_7): Likewise. (PREFIX_MOD_0_0F01_REG_5): Likewise. (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise. (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise. (PREFIX_0F1E): Likewise. (PREFIX_MOD_0_0FAE_REG_5): Likewise. (PREFIX_0F38F5): Likewise. (dis386_twobyte): Use PREFIX_0F1E. (reg_table): Add REG_0F1E_MOD_3. (prefix_table): Add PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2, PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update PREFIX_0FAE_REG_6 and PREFIX_0F38F6. (three_byte_table): Use PREFIX_0F38F5. (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5. Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0. (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0, RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and PREFIX_MOD_3_0F01_REG_5_RM_2. * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS. (cpu_flags): Add CpuCET. * i386-opc.h (CpuCET): New enum. (CpuUnused): Commented out. (i386_cpu_flags): Add cpucet. * i386-opc.tbl: Add Intel CET instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. |
||
Szabolcs Nagy
|
01cca2f95e |
[AArch64] Document +rcpc weak release consistency extension
gas/ * doc/c-aarch64.texi (AArch64 Extensions): Document rcpc. |
||
Richard Sandiford
|
582e12bf76 |
[AArch64] Additional SVE instructions
This patch supports some additions to the SVE architecture prior to
its public release.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16)
(AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2)
(AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX)
(AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
(OP_SVE_V_HSD): New macros.
(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
(aarch64_opcode_table): Add new SVE instructions.
(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
for rotation operands. Add new SVE operands.
* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
(ins_sve_quad_index): Likewise.
(ins_imm_rotate): Split into...
(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
functions.
(aarch64_ins_sve_addr_ri_s4): New function.
(aarch64_ins_sve_quad_index): Likewise.
(do_misc_encoding): Handle "MOV Zn.Q, Qm".
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
(ext_sve_quad_index): Likewise.
(ext_imm_rotate): Split into...
(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
functions.
(aarch64_ext_sve_addr_ri_s4): New function.
(aarch64_ext_sve_quad_index): Likewise.
(aarch64_ext_sve_index): Allow quad indices.
(do_misc_decoding): Likewise.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
aarch64_field_kinds.
(OPD_F_OD_MASK): Widen by one bit.
(OPD_F_NO_ZR): Bump accordingly.
(get_operand_field_width): New function.
* aarch64-opc.c (fields): Add new SVE fields.
(operand_general_constraint_met_p): Handle new SVE operands.
(aarch64_print_operand): Likewise.
* aarch64-opc-2.c: Regenerate.
gas/
* doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum.
* config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q
to be used with SVE registers.
(parse_operands): Handle new SVE operands.
(aarch64_features): Make "sve" require F16 rather than FP. Also
require COMPNUM.
* testsuite/gas/aarch64/sve.s: Add tests for new instructions.
Include compnum tests.
* testsuite/gas/aarch64/sve.d: Update accordingly.
* testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions.
* testsuite/gas/aarch64/sve-invalid.l: Update accordingly. Also
update expected output for new FMOV and MOV alternatives.
|
||
|
Richard Sandiford
|
f482d30447 |
[AArch64] Add a "compnum" feature
This patch adds a named "compnum" feature for the ARMv8.3-A FCADD and FCMLA extensions. include/ * opcode/aarch64.h (AARCH64_FEATURE_COMPNUM): New macro. (AARCH64_ARCH_V8_3): Include AARCH64_FEATURE_COMPNUM. opcodes/ * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with... (aarch64_feature_compnum): ...this. (SIMD_V8_3): Replace with... (COMPNUM): ...this. (CNUM_INSN): New macro. (aarch64_opcode_table): Use it for the complex number instructions. gas/ * doc/c-aarch64.texi: Add a "compnum" entry. * config/tc-aarch64.c (aarch64_features): Likewise, * testsuite/gas/aarch64/advsimd-compnum.s: New test. * testsuite/gas/aarch64/advsimd-compnum.d: Likewise. |
||
|
Andreas Krebbel
|
64025b4ec9 |
S/390: Add support for new cpu architecture - arch12.
This adds support of new instructions to the S/390 specific parts. The important feature of the new instruction set is the support of single and extended precision floating point vector operations. Note: arch12 is NOT the official name of the new CPU. It just continues the series of archXX options supported as alternate names. The archXX terminology refers to the edition number of the Principle of Operations manual. The official CPU name will be added later while keeping support of the arch12 for backwards compatibility. No testsuite regressions. Committed to mainline. Bye, -Andreas- opcodes/ChangeLog: 2017-02-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * s390-mkopc.c (main): Accept arch12 as cpu string and vx2 as facility. * s390-opc.c: Add new operand description macros, new instruction types, instruction masks, and new .insn instruction types. * s390-opc.txt: Add new arch12 instructions. include/ChangeLog: 2017-02-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * opcode/s390.h (enum s390_opcode_cpu_val): New value S390_OPCODE_ARCH12. (S390_INSTR_FLAG_VX2): New macro definition. gas/ChangeLog: 2017-02-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config/tc-s390.c (s390_parse_cpu): New entry for arch12. * doc/as.texinfo: Document arch12 as cpu type. * doc/c-s390.texi: Likewise. * testsuite/gas/s390/s390.exp: Run arch12 specific tests. * testsuite/gas/s390/zarch-arch12.d: New test. * testsuite/gas/s390/zarch-arch12.s: New test. * testsuite/gas/s390/zarch-z13.d: Rename some mnemonics in the output patterns. |