Since (%bp)/(%ebp)/(%rbp) are encoded as 0(%bp)/0(%ebp)/0(%rbp), use
disp32/disp16 on 0(%bp)/0(%ebp)/0(%rbp) for {disp32}.
Note: Since there is no disp32 on 0(%bp), use disp16 instead.
PR gas/26305
* config/tc-i386.c (build_modrm_byte): Use disp32/disp16 on
(%bp)/(%ebp)/(%rbp) for {disp32}.
* doc/c-i386.texi: Update {disp32} documentation.
* testsuite/gas/i386/pseudos.s: Add (%bp)/(%ebp) tests.
* testsuite/gas/i386/x86-64-pseudos.s: Add (%ebp)/(%rbp) tests.
* testsuite/gas/i386/pseudos.d: Updated.
* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
The 64-bit version of binutils got support for the PE COFF BIG OBJ format a
couple of years ago. The BIG OBJ format is a slightly different COFF format
which extends the size of the number of section field in the header from a
uint16_t to a uint32_t and so greatly increases the number of sections allowed.
However the 32-bit version of bfd never got support for this. The GHC Haskell
compiler generates a great deal of symbols due to it's use of
-ffunction-sections and -fdata-sections.
This meant that we could not build the 32-bit version of the GHC Compiler for
many releases now as binutils didn't have this support.
This patch adds the support to the 32-bit port of binutils as well and also does
come cleanup in the code.
bfd/ChangeLog:
* coff-i386.c (COFF_WITH_PE_BIGOBJ): New.
* coff-x86_64.c (COFF_WITH_PE_BIGOBJ): New.
* config.bfd (targ_selvecs): Rename x86_64_pe_be_vec
to x86_64_pe_big_vec as it not a big-endian format.
(vec i386_pe_big_vec): New.
* configure.ac: Likewise.
* targets.c: Likewise.
* configure: Regenerate.
* pe-i386.c (TARGET_SYM_BIG, TARGET_NAME_BIG,
COFF_WITH_PE_BIGOBJ): New.
* pe-x86_64.c (TARGET_SYM_BIG, TARGET_NAME_BIG):
New.
(x86_64_pe_be_vec): Moved.
gas/ChangeLog:
* NEWS: Add news entry for big-obj.
* config/tc-i386.c (i386_target_format): Support new format.
* doc/c-i386.texi: Add i386 support.
* testsuite/gas/pe/big-obj.d: Rename test to not be x64 specific.
* testsuite/gas/pe/pe.exp (big-obj): Make test run on i386 as well.
ld/ChangeLog:
* pe-dll.c (pe_detail_list): Add pe-bigobj-i386.
Add 3 command-line options to generate lfence for load, indirect near
branch and ret to help mitigate:
https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00334.htmlhttp://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2020-0551
1. -mlfence-after-load=[no|yes]:
-mlfence-after-load=yes generates lfence after load instructions.
2. -mlfence-before-indirect-branch=[none|all|memory|register]:
a. -mlfence-before-indirect-branch=all generates lfence before indirect
near branches via register and a warning before indirect near branches
via memory.
b. -mlfence-before-indirect-branch=memory issue a warning before
indirect near branches via memory.
c. -mlfence-before-indirect-branch=register generates lfence before
indirect near branches via register.
Note that lfence won't be generated before indirect near branches via
register with -mlfence-after-load=yes since lfence will be generated
after loading branch target register.
3. -mlfence-before-ret=[none|or|not]
a. -mlfence-before-ret=or generates or with lfence before ret.
b. -mlfence-before-ret=not generates not with lfence before ret.
A warning will be issued and lfence won't be generated before indirect
near branch and ret if the previous item is a prefix or a constant
directive, which may be used to hardcode an instruction, since there
is no clear instruction boundary.
* config/tc-i386.c (lfence_after_load): New.
(lfence_before_indirect_branch_kind): New.
(lfence_before_indirect_branch): New.
(lfence_before_ret_kind): New.
(lfence_before_ret): New.
(last_insn): New.
(load_insn_p): New.
(insert_lfence_after): New.
(insert_lfence_before): New.
(md_assemble): Call insert_lfence_before and insert_lfence_after.
Set last_insn.
(OPTION_MLFENCE_AFTER_LOAD): New.
(OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH): New.
(OPTION_MLFENCE_BEFORE_RET): New.
(md_longopts): Add -mlfence-after-load=,
-mlfence-before-indirect-branch= and -mlfence-before-ret=.
(md_parse_option): Handle -mlfence-after-load=,
-mlfence-before-indirect-branch= and -mlfence-before-ret=.
(md_show_usage): Display -mlfence-after-load=,
-mlfence-before-indirect-branch= and -mlfence-before-ret=.
(i386_cons_align): New.
* config/tc-i386.h (i386_cons_align): New.
(md_cons_align): New.
* doc/c-i386.texi: Document -mlfence-after-load=,
-mlfence-before-indirect-branch= and -mlfence-before-ret=.
AMD ABM has 2 instructions: popcnt and lzcnt. ABM CPUID feature bit has
been reused for lzcnt and a POPCNT CPUID feature bit is added for popcnt
which used to be the part of SSE4.2. This patch removes CpuABM and adds
CpuPOPCNT. It changes ABM to enable both lzcnt and popcnt, changes SSE4.2
to also enable popcnt.
gas/
* config/tc-i386.c (cpu_arch): Add .popcnt.
* doc/c-i386.texi: Remove abm and .abm. Add popcnt and .popcnt.
Add a tab before @samp{.sse4a}.
opcodes/
* i386-gen.c (cpu_flag_init): Replace CpuABM with
CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
CPU_POPCNT_FLAGS.
(cpu_flags): Remove CpuABM. Add CpuPOPCNT.
* i386-opc.h (CpuABM): Removed.
(CpuPOPCNT): New.
(i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
* i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
popcnt. Remove CpuABM from lzcnt.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
commit 7deea9aad8 changed nosse4 to include CpuSSE4a. But AMD SSE4a is
a superset of SSE3 and Intel SSE4 is a superset of SSSE3. Disable Intel
SSE4 shouldn't disable AMD SSE4a. This patch restores nosse4. It also
adds .sse4a and nosse4a.
gas/
* config/tc-i386.c (cpu_arch): Add .sse4a and nosse4a. Restore
nosse4.
* doc/c-i386.texi: Document sse4a and nosse4a.
opcodes/
* i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
CPU_ANY_SSE4_FLAGS.
Document different mnemonics of movsx, movsxd and movzx in AT&T syntax.
PR gas/25438
* doc/c-i386.texi: Document movsx, movsxd and movzx for AT&T
syntax.
AMD and Intel differ in their handling of far indirect branches as well
as LFS/LGS/LSS: AMD CPUs ignore REX.W while Intel ones honors it. (Note
how the latter three were hybrids so far, while far branches were fully
AMD-like.)
Commit d835a58baa disabled sysenter/sysenter in 64-bit mode by
default. By default, assembler should accept common, Intel64 only
and AMD64 ISAs since there are no conflicts.
gas/
PR gas/25516
* config/tc-i386.c (intel64): Renamed to ...
(isa64): This.
(match_template): Accept Intel64 only instruction by default.
(i386_displacement): Updated.
(md_parse_option): Updated.
* c-i386.texi: Update -mamd64/-mintel64 documentation.
* testsuite/gas/i386/i386.exp: Run x86-64-sysenter. Pass
-mamd64 to x86-64-sysenter-amd.
* testsuite/gas/i386/x86-64-sysenter.d: New file.
opcodes/
PR gas/25516
* i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
with ISA64.
* i386-opc.h (AMD64): Removed.
(Intel64): Likewose.
(AMD64): New.
(INTEL64): Likewise.
(INTEL64ONLY): Likewise.
(i386_opcode_modifier): Replace amd64 and intel64 with isa64.
* i386-opc.tbl (Amd64): New.
(Intel64): Likewise.
(Intel64Only): Likewise.
Replace AMD64 with Amd64. Update sysenter/sysenter with
Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
* i386-tbl.h: Regenerated.
movsxd is a 64-bit only instruction. It supports both 16-bit and 32-bit
destination registers. Its AT&T mnemonic is movslq which only supports
64-bit destination register. There is also a discrepancy between AMD64
and Intel64 on movsxd with 16-bit destination register. AMD64 supports
32-bit source operand and Intel64 supports 16-bit source operand.
This patch updates movsxd encoding and decoding to alow 16-bit and 32-bit
destination registers. It also handles movsxd with 16-bit destination
register for AMD64 and Intel 64.
gas/
PR binutils/25445
* config/tc-i386.c (check_long_reg): Also convert to QWORD for
movsxd.
* doc/c-i386.texi: Add a node for AMD64 vs. Intel64 ISA
differences. Document movslq and movsxd.
* testsuite/gas/i386/i386.exp: Run PR binutils/25445 tests.
* testsuite/gas/i386/x86-64-movsxd-intel.d: New file.
* testsuite/gas/i386/x86-64-movsxd-intel64-intel.d: Likewise.
* testsuite/gas/i386/x86-64-movsxd-intel64-inval.l: Likewise.
* testsuite/gas/i386/x86-64-movsxd-intel64-inval.s: Likewise.
* testsuite/gas/i386/x86-64-movsxd-intel64.d: Likewise.
* testsuite/gas/i386/x86-64-movsxd-intel64.s: Likewise.
* testsuite/gas/i386/x86-64-movsxd-inval.l: Likewise.
* testsuite/gas/i386/x86-64-movsxd-inval.s: Likewise.
* testsuite/gas/i386/x86-64-movsxd.d: Likewise.
* testsuite/gas/i386/x86-64-movsxd.s: Likewise.
opcodes/
PR binutils/25445
* i386-dis.c (MOVSXD_Fixup): New function.
(movsxd_mode): New enum.
(x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
(intel_operand_size): Handle movsxd_mode.
(OP_E_register): Likewise.
(OP_G): Likewise.
* i386-opc.tbl: Remove Rex64 and allow 32-bit destination
register on movsxd. Add movsxd with 16-bit destination register
for AMD64 and Intel64 ISAs.
* i386-tbl.h: Regenerated.
Commit b76bc5d54e ("x86: don't default variable shift count insns to
8-bit operand size") pointed out a very bad case, but the underlying
problem is, as mentioned on various occasions, much larger: Silently
selecting a (nowhere documented afaict) certain default operand size
when there's no "sizing" suffix and no suitable register operand(s) is
simply dangerous (for the programmer to make mistakes).
While in Intel syntax mode such mistakes already lead to an error (which
is going to remain that way), AT&T syntax mode now gains warnings in
such cases by default, which can be suppressed or promoted to an error
if so desired by the programmer. Furthermore at least general purpose
insns now consistently have a default applied (alongside the warning
emission), rather than accepting some and refusing others.
No warnings are (as before) to be generated for "DefaultSize" insns as
well as ones acting on selector and other fixed-width values. For
SYSRET, however, the DefaultSize needs to be dropped - it had been
wrongly put there in the first place, as it's unrelated to .code16gcc
(no stack accesses involved).
As set forth as a prereq when I first mentioned this intended change a
few years back, Linux as well as gcc have meanwhile been patched to
avoid (emission of) ambiguous operands (and hence triggering of the new
warning).
Note that I think that in 64-bit mode IRET and far RET would better get
a diagnostic too, as it's reasonably likely that a suffix-less instance
really is meant to be a 64-bit one. But I guess I better make this a
separate follow-on patch.
Note further that floating point operations with integer operands are an
exception for now: They continue to use short (16-bit) operands by
default even in 32- and 64-bit modes.
Finally note that while {,V}PCMPESTR{I,M} would, strictly speaking, also
need to be diagnosed, with their 64-bit forms not being very useful I
think it is better to continue to avoid warning about them (by way of
them carrying IgnoreSize attributes).
Add 3 command-line options to align branches within a fixed boundary
with segment prefixes or NOPs:
1. -malign-branch-boundary=NUM aligns branches within NUM byte boundary.
2. -malign-branch=TYPE[+TYPE...] specifies types of branches to align.
The supported branches are:
a. Conditional jump.
b. Fused conditional jump.
c. Unconditional jump.
d. Call.
e. Ret.
f. Indirect jump and call.
3. -malign-branch-prefix-size=NUM aligns branches with NUM segment
prefixes per instruction.
3 new rs_machine_dependent frag types are added:
1. BRANCH_PADDING. The variable size frag to insert NOP before branch.
2. BRANCH_PREFIX. The variable size frag to insert segment prefixes to
an instruction. The choices of prefixes are:
a. Use the existing segment prefix if there is one.
b. Use CS segment prefix in 64-bit mode.
c. In 32-bit mode, use SS segment prefix with ESP/EBP base register
and use DS segment prefix without ESP/EBP base register.
3. FUSED_JCC_PADDING. The variable size frag to insert NOP before fused
conditional jump.
The new rs_machine_dependent frags aren't inserted if the previous item
is a prefix or a constant directive, which may be used to hardcode an
instruction, since there is no clear instruction boundary. Segment
prefixes and NOP padding are disabled before relaxable TLS relocations
and tls_get_addr calls to keep TLS instruction sequence unchanged.
md_estimate_size_before_relax() and i386_generic_table_relax_frag() are
used to handled BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags.
i386_generic_table_relax_frag() grows or shrinks sizes of segment prefix
and NOP to align the next branch frag:
1. First try to add segment prefixes to instructions before a branch.
2. If there is no sufficient room to add segment prefixes, NOP will be
inserted before a branch.
* config/tc-i386.c (_i386_insn): Add has_gotpc_tls_reloc.
(tls_get_addr): New.
(last_insn): New.
(align_branch_power): New.
(align_branch_kind): New.
(align_branch_bit): New.
(align_branch): New.
(MAX_FUSED_JCC_PADDING_SIZE): New.
(align_branch_prefix_size): New.
(BRANCH_PADDING): New.
(BRANCH_PREFIX): New.
(FUSED_JCC_PADDING): New.
(i386_generate_nops): Support BRANCH_PADDING and FUSED_JCC_PADDING.
(md_begin): Abort if align_branch_prefix_size <
MAX_FUSED_JCC_PADDING_SIZE.
(md_assemble): Set last_insn.
(maybe_fused_with_jcc_p): New.
(add_fused_jcc_padding_frag_p): New.
(add_branch_prefix_frag_p): New.
(add_branch_padding_frag_p): New.
(output_insn): Generate a BRANCH_PADDING, FUSED_JCC_PADDING or
BRANCH_PREFIX frag and terminate each frag to align branches.
(output_disp): Set i.has_gotpc_tls_reloc to TRUE for GOTPC and
relaxable TLS relocations.
(output_imm): Likewise.
(i386_next_non_empty_frag): New.
(i386_next_jcc_frag): New.
(i386_classify_machine_dependent_frag): New.
(i386_branch_padding_size): New.
(i386_generic_table_relax_frag): New.
(md_estimate_size_before_relax): Handle COND_JUMP_PADDING,
FUSED_JCC_PADDING and COND_JUMP_PREFIX frags.
(md_convert_frag): Handle BRANCH_PADDING, BRANCH_PREFIX and
FUSED_JCC_PADDING frags.
(OPTION_MALIGN_BRANCH_BOUNDARY): New.
(OPTION_MALIGN_BRANCH_PREFIX_SIZE): New.
(OPTION_MALIGN_BRANCH): New.
(md_longopts): Add -malign-branch-boundary=,
-malign-branch-prefix-size= and -malign-branch=.
(md_parse_option): Handle -malign-branch-boundary=,
-malign-branch-prefix-size= and -malign-branch=.
(md_show_usage): Display -malign-branch-boundary=,
-malign-branch-prefix-size= and -malign-branch=.
(i386_target_format): Set tls_get_addr.
(i386_cons_align): New.
* config/tc-i386.h (i386_cons_align): New.
(md_cons_align): New.
(i386_generic_table_relax_frag): New.
(md_generic_table_relax_frag): New.
(i386_tc_frag_data): Add u, padding_address, length,
max_prefix_length, prefix_length, default_prefix, cmp_size,
classified and branch_type.
(TC_FRAG_INIT): Initialize u, padding_address, length,
max_prefix_length, prefix_length, default_prefix, cmp_size,
classified and branch_type.
* doc/c-i386.texi: Document -malign-branch-boundary=,
-malign-branch= and -malign-branch-prefix-size=.
It seems to be not uncommon for people to use AND or OR in this form for
just setting the status flags. TEST, which doesn't write to any
register other than EFLAGS, ought to be preferred. Make the change only
for -O2 and above though, at least for now.
When they're in the 0F opcode space, swapping their source operands may
allow switching from 3-byte to 2-byte VEX prefix encoding. Note that NaN
behavior precludes us doing so for many packed and scalar floating point
insns; such an optimization would need to be done by the compiler
instead in this case, when it knows that NaN-s have undefined behavior
anyway.
While for explicitly specified AVX/AVX2 insns the optimization (for now
at least) gets done only for -O2 and -Os, it is utilized by default in
SSE2AVX mode, as there we're re-writing the programmer's specified insns
anyway.
Rather than introducing a new attribute flag, the change re-uses one
which so far was meaningful only for EVEX-encoded insns.
As long as there's no write mask as well as no broadcast, and as long
as the scaled Disp8 wouldn't result in a shorter EVEX encoding, encode
VPAND{D,Q}, VPANDN{D,Q}, VPOR{D,Q}, and VPXOR{D,Q} acting on only the
lower 16 XMM/YMM registers using their VEX equivalents with -O1.
Also take the opportunity and avoid looping twice over all operands
when dealing with memory-with-displacement ones.
Since all AVX512 processors support AVX, we can encode 256-bit/512-bit
VEX/EVEX vector register clearing instructions with 128-bit VEX vector
register clearing instructions at -O1.
* config/tc-i386.c (optimize_encoding): Encode 256-bit/512-bit
VEX/EVEX vector register clearing instructions with 128-bit VEX
vector register clearing instructions at -O1.
* doc/c-i386.texi: Update -O1 and -O2 documentation.
* testsuite/gas/i386/i386.exp: Run optimize-1a and
x86-64-optimize-2a.
* testsuite/gas/i386/optimize-1a.d: New file.
* testsuite/gas/i386/x86-64-optimize-2a.d: Likewise.
Add -mvexwig=[0|1] option to x86 assembler to control how the assembler
should encode the VEX.W bit in WIG VEX instructions.
* gas/NEWS: Mention -mvexwig=[0|1] option.
* config/tc-i386.c (vexwig): New.
(build_vex_prefix): Set the VEX.W bit for -mvexwig=1 for WIG
VEX instructions.
(OPTION_MVEXWIG): New.
(md_longopts): Add -mvexwig=.
(md_parse_option): Handle OPTION_MVEXWIG.
(md_show_usage): Show -mvexwig=[0|1].
* doc/c-i386.texi: Document -mvexwig=[0|1].
* testsuite/gas/i386/avx-wig.d: New file.
* testsuite/gas/i386/avx-wig.s: Likewise.
* testsuite/gas/i386/avx2-wig.d: Likewise.
* testsuite/gas/i386/avx2-wig.s: Likewise.
* testsuite/gas/i386/x86-64-avx-wig.d: Likewise.
* testsuite/gas/i386/x86-64-avx-wig.s: Likewise.
* testsuite/gas/i386/x86-64-avx2-wig.d: Likewise.
* testsuite/gas/i386/x86-64-avx2-wig.s: Likewise.
* testsuite/gas/i386/i386.exp: Run avx-wig, avx2-wig,
x86-64-avx-wig and x86-64-avx2-wig.
Add -mx86-used-note=[yes|no] option to generate (or not) GNU property
notes with GNU_PROPERTY_X86_FEATURE_2_USED and GNU_PROPERTY_X86_ISA_1_USED
properties. If the assembly input contains no instructions, set the
GNU_PROPERTY_X86_UINT32_VALID bit in GNU_PROPERTY_X86_FEATURE_2_USED
property. Add a --enable-x86-used-note configure time option to set the
default behavior. Set the default if the configure option is not used
to "no".
* NEWS: Mention -mx86-used-note=[no|yes].
* configure.ac: Add --enable-x86-used-note. Define
DEFAULT_X86_USED_NOTE.
* config.in: Regenerated.
* configure: Likewise.
* config/tc-i386.c (x86_isa_1_used): New.
(x86_feature_2_used): Likewise.
(x86_used_note): Likewise.
(_i386_insn): Add has_regmmx, has_regxmm, has_regymm and
has_regzmm.
(build_modrm_byte): Set i.has_regmmx, i.has_regzmm.
i.has_regymm and i.has_regxmm.
(x86_cleanup): New function.
(output_insn): Update x86_isa_1_used and x86_feature_2_used.
(OPTION_X86_USED_NOTE): New.
(md_longopts): Add -mx86-used-note=.
(md_parse_option): Handle OPTION_X86_USED_NOTE.
(md_show_usage): Display -mx86-used-note=.
* config/tc-i386.h (x86_cleanup): New prototype.
(md_cleanup): New.
* doc/c-i386.texi: Document -mx86-used-note=.
There are separate CPUID feature bits for fxsave/fxrstor and cmovCC
instructions. This patch adds CpuCMOV and CpuFXSR to replace Cpu686
on corresponding instructions.
gas/
* config/tc-i386.c (cpu_arch): Add .cmov and .fxsr.
(cpu_noarch): Add nocmov and nofxsr.
* doc/c-i386.texi: Document cmov and fxsr.
opcodes/
* i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
(cpu_flags): Add CpuCMOV and CpuFXSR.
* i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
Binutils documentation uses a mix of spelling for the compound word
"command-line X". According to [1]:
"Sometimes compound words are written separately (nail polish),
sometimes with a hyphen (short-sighted) and sometimes as one word
(eyelashes). Often new compounds are written as two separate words and,
as they become more familiar, they are either connected with a hyphen
(-) or made into one word."
I think command-line X is common enough in our industry that the two
workds command and line should be connected. Since command-line is more
common than commandline, I propose to update binutils documentation to
consistently use "command-line" when this is used as an adjective to a
noun (eg. command-line argument, command-line switch, command-line
option and command-line flag). I've left occurences of "the command
line" as is. I've also left gdb, sim and readline alone and have only
touched public documentation (texi and NEWS files).
[1]
http://dictionary.cambridge.org/grammar/british-grammar/word-formation/compounds
2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
* doc/bfdint.texi: Use command-line consistently when used in a
compount word.
* doc/bfdsumm.texi: Likewise.
binutils/
* NEWS: Use command-line consistently when used in a compount word.
* doc/binutils.texi: Likewise and fix trailing whitespace on same
line.
gas/
* NEWS: Use command-line consistently when used in a compount word.
* doc/as.texi: Likewise.
* doc/c-aarch64.texi: Likewise.
* doc/c-alpha.texi: Likewise.
* doc/c-arc.texi: Likewise.
* doc/c-arm.texi: Likewise.
* doc/c-avr.texi: Likewise.
* doc/c-bfin.texi: Likewise.
* doc/c-cris.texi: Likewise.
* doc/c-epiphany.texi: Likewise.
* doc/c-i386.texi: Likewise.
* doc/c-ia64.texi: Likewise.
* doc/c-lm32.texi: Likewise.
* doc/c-m32r.texi: Likewise.
* doc/c-m68k.texi: Likewise.
* doc/c-mips.texi: Likewise.
* doc/c-mmix.texi: Likewise.
* doc/c-msp430.texi: Likewise.
* doc/c-mt.texi: Likewise.
* doc/c-nios2.texi: Likewise.
* doc/c-ppc.texi: Likewise.
* doc/c-pru.texi: Likewise.
* doc/c-rl78.texi: Likewise.
* doc/c-rx.texi: Likewise.
* doc/c-tic6x.texi: Likewise.
* doc/c-v850.texi: Likewise.
* doc/c-vax.texi: Likewise.
* doc/c-visium.texi: Likewise.
* doc/c-xstormy16.texi: Likewise.
* doc/c-xtensa.texi: Likewise.
* doc/c-z80.texi: Likewise.
* doc/c-z8k.texi: Likewise.
* doc/internals.texi: Likewise.
gprof/
* gprof.texi: Use command-line consistently when used in a compount
word.
ld/
* NEWS: Use command-line consistently when used in a compount word.
* ld.texinfo: Likewise.
* ldint.texinfo: Likewise.
