SHF_INFO_LINK bit set, which shows up in readelf section dumps. This
has broken a couple of IA64 testcases in the gas testsuite, which are
fixed by this patch.
PR binutils/16317
* gas/ia64/group-2.d: Expect I attribute with RELA sections.
* gas/ia64/xdata.d: Likewise.
For each object, if it has a nonempty .data or .bss section,
emit a symbol that could cause the startup code to selectively
link in the code to initialize those sections.
* config/tc-msp430.c (msp430_section): Always flag data sections,
regardless of -md.
(msp430_frob_section): New. Make sure all sections are noticed if
they have content.
(msp430_lcomm): New. Flag bss if .lcomm is seen.
(msp430_comm): New. Likewise.
(md_pseudo_table): Add them.
* config/tc-msp430.h (msp430_frob_section): Declare.
(tc_frob_section): Define.
New MSP430 MCU parts are being created by TI all the time and the
list is basically always out of date. Instead any name will be
accepted by the -mmcu= command line option. ISA selection is now
based upon the -mcpu= command line option, just as is done for GCC.
gas/ChangeLog
* config/tc-msp430.c (show_mcu_list): Delete.
(md_parse_option): Accept any MCU name. Accept several more
variants for the -mcpu option.
(md_show_usage): Do not call show_mcu_list.
* config/tc-msp430.c (msp430_refsym): New: ".refsym <symbol>"
* doc/c-msp430.texi (MSP430 Directives): Document it.
The purpose of this patch is to provide a way for one object file
to require the inclusion of another object, without having to
allocate space for a .word address reference.
Since regzmm can't be used in AVX2 gather instructions, there is no need
to check regzmm in AVX2 gather assert.
2014-01-22 Michael Zolotukhin <michael.v.zolotukhin@gmail.com>
* config/tc-i386.c (check_VecOperands): Remove regzmm from AVX2
gather assert.
This is to avoid expressions like: %hi(foo) + 1, which will
not do what you expect. The complex relocations can handle it,
but the internal fixups can't.
The direct rounding floating-point VCVT instructions introduced in
ARMv8 encode the s32.f64 variant incorrectly. The op bit should be
set to 1 for all signed conversions.
gas/ChangeLog:
2014-01-17 Will Newton <will.newton@linaro.org>
* config/tc-arm.c (do_vfp_nsyn_cvt_fpv8): Set OP to 1
for the s32.f64 flavours of VCVT.
gas/testsuite/ChangeLog:
2014-01-17 Will Newton <will.newton@linaro.org>
* gas/arm/armv8-a+fp.d: Correct encoding of vcvta.s32.f64.
binutils/
* version.c (print_version): Update copyright year to 2014.
gas/
* as.c (parse_args): Update copyright year to 2014.
gold/
* version.cc (print_version): Update copyright year to 2014.
ld/
* ldver.c (ldversion): Update copyright year to 2014.
opcodes/
* i386-gen.c (process_copyright): Update copyright year to 2014.
This removes the last uses of the obsolete VA_* macros from binutils.
All the binutils and bfd changes were tested by rebuilding.
I didn't rebuild the gas change but I think it is obviously correct.
2014-01-07 Tom Tromey <tromey@redhat.com>
* elf32-xtensa.c (vsprint_msg): Don't use old VA_* compatibility
wrappers.
2014-01-07 Tom Tromey <tromey@redhat.com>
* bucomm.c (fatal, non_fatal): Replace obsolete VA_* macros with
stdarg macros.
* dlltool.c (inform): Replace obsolete VA_* macros with stdarg
macros.
* dllwrap.c (inform, warn): Replace obsolete VA_* macros with
stdarg macros.
2014-01-07 Tom Tromey <tromey@redhat.com>
* config/tc-tic30.c (debug): Avoid old VA_* compatibility
wrappers.
This removes the last uses of PARAMS from binutils.
The two changes in binutils were tested by rebuilding.
I didn't rebuild the gas change but I think it is obviously correct.
2014-01-07 Tom Tromey <tromey@redhat.com>
* coffgrok.h (coff_ofile): Don't use PARAMS.
* nlmheader.y (strerror): Don't use PARAMS.
2014-01-07 Tom Tromey <tromey@redhat.com>
* config/tc-microblaze.h (parse_cons_expression_microblaze): Don't
use PARAMS.
This removes the last use of ANSI_PROTOTYPES in the tree.
It appears in gas.
I didn't even rebuild this but I think it is obviously correct.
2014-01-07 Tom Tromey <tromey@redhat.com>
* config/tc-xc16x.h: Don't use ANSI_PROTOTYPES.
Add two more as test files for user special and system register.
Fix typo.
2013-12-17 Kuan-Lin Chen <kuanlinchentw@gmail.com>
* gas/nds32/nds32.exp: Add system and user special register tests.
* gas/nds32/sys-reg.s: New test.
* gas/nds32/sys-reg.d: Likewise.
* gas/nds32/usr-spe-reg.s: Likewise.
* gas/nds32/usr-spe-reg.d: Likewise.
* gas/nds32/alu-2.d: Delete the new blank line at EOF.
* gas/nds32/br-1.d: Likewise.
* gas/nds32/br-2.d: Likewise.
* gas/nds32/ji-jr.d: Likewise.
* gas/nds32/lsi.d: Likewise.
* nds32-dis.c (sr_map): Add system register table for disassembling.
(usr_map): Fix typo.
* nds32-asm.c (keyword_sr): Add embedded debug registers.
2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
gas/testsuite/gas/mips/
* mips.exp: Add CP1 register name tests.
* cp1-names-mips32.d: New test.
* cp1-names-mips32r2.d: New test.
* cp1-names-mips64.d: New test.
* cp1-names-mips64r2.d: New test.
* cp1-names-numeric.d: New test.
* cp1-names-r3000.d: New test.
* cp1-names-r4000.d: New test.
* cp1-names-sb1.d: New test.
* cp1-names.s: New test.
* micromips-insn32.d: Add the correct symbolic names for the CP1
registers.
* micromips-noinsn32.d: Likewise.
* micromips-trap.d: Likewise.
* micromips.d: Likewise.
opcodes/
* mips-dis.c: Add mips_cp1_names pointer.
(mips_cp1_names_numeric): New array.
(mips_cp1_names_mips3264): New array.
(mips_arch_choice): Add cp1_names.
(mips_arch_choices): Add relevant cp1 register name array to each of
the elements.
(set_default_mips_dis_options): Add support for setting up the
mips_cp1_names pointer.
(parse_mips_dis_option): Add support for the cp1-names command line
variable. Also setup the mips_cp1_names pointer.
(print_reg): Print out name of the cp1 register.
The element index range for the following MIPS MSA instructions: sldi, splati,
copy_s, copy_u, insert and insve is 1 bit too large. This patch fixes this issue.
ChangeLog:
gas/testsuite/gas/mips/
* msa.s: Reduced maximum element index range for sldi, splati,
copy_s, copy_u, insert and insve instructions.
* msa64.s: Likewise.
* micromips@msa.d: Likewise.
* micromips@msa64.d: Likewise.
* msa.d: Likewise.
* msa64.d: Likewise.
include/opcode/
* mips.h: Updated description of +o, +u, +v and +w for MIPS and
microMIPS.
opcodes/
* micromips-opc.c (decode_micromips_operand): Reduced range of +o, +u,
+v and +w.
(micromips_opcodes): Reduced element index range for sldi, splati,
copy_s, copy_u, insert and insve instructions.
* opcodes/mips-opc.c (decode_mips_operand): Reduced range of +o, +u,
+v and +w.
(mips_builtin_opcodes): Reduced element index range for sldi, splati,
copy_s, copy_u, insert and insve instructions.
(OPTION_INTR_NOPS): Define.
(gen_interrupt_nops): Default to FALSE.
(md_parse_opton): Add support for OPTION_INTR_NOPS.
(md_longopts): Add -mn.
(md_show_usage): Add -mn.
(msp430_operands): Generate NOPs for all MCUs not just 430Xv2.
* doc/c-msp430.c: Document -mn.
These files are source files and have no business being +x. We couldn't
easily fix it in CVS (you need login+write access to the raw rcs files),
but we can fix this w/git.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2013-11-27 Matthew Fortune <matthew.fortune@imgtec.com>
* binutils-all/objcopy.exp: Consider mips-mti-elf the same as
mips-sde-elf
* binutils-all/readelf.exp: Likewise
gas/testsuite/
2013-11-27 Matthew Fortune <matthew.fortune@imgtec.com>
* gas/mips/mips.exp: Consider mips-mti-elf the same as mips-sde-elf
ld/testsuite/
2013-11-27 Matthew Fortune <matthew.fortune@imgtec.com>
* ld-mips-elf/mips-elf.exp: Consider mips-mti-elf the same as
mips-sde-elf
gas/
* config/tc-arm.c (arm_archs): New armv7ve architecture option.
(arm_cpus): Replace ARM_ARCH_V7A_IDIV_MP_SEC_VIRT with
ARM_ARCH_V7VE for cortex-a7, cortex-a12 and cortex-a15.
(cpu_arch_ver): Likewise.
* doc/c-arm.texi: Document armv7ve.
gas/testsuite/
* gas/arm/attr-march-armv7ve.d: New test case for armv7ve.
include/opcode/
* arm.h (ARM_AEXT_V7VE): New define.
(ARM_ARCH_V7VE): New define.
(ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
* config/tc-aarch64.c (set_other_error): New function.
(parse_sys_reg): Add new parameter 'sys_reg' and if non-NULL set
the variable to which it points with 'o'.
(parse_operands): Update; check for write to read-only system
registers or read from write-only ones.
gas/testsuite/
* gas/aarch64/diagnostic.s: Add tests.
* gas/aarch64/diagnostic.l: Update.
* gas/aarch64/tracereg-illegal.d: New file.
* gas/aarch64/tracereg-illegal.l: Ditto.
* gas/aarch64/tracereg-illegal.s: Ditto.
* gas/aarch64/tracereg.d: Ditto.
* gas/aarch64/tracereg.s: Ditto.
include/opcode
* aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
(aarch64_sys_reg_writeonly_p): Ditto.
opcodes/
* aarch64-opc.c (CPENT): New define.
(F_READONLY, F_WRITEONLY): Likewise.
(aarch64_sys_regs): Add trace unit registers.
(aarch64_sys_reg_readonly_p): New function.
(aarch64_sys_reg_writeonly_p): Ditto.
* config/tc-aarch64.c (parse_sys_reg): Update to use aarch64_sys_reg;
call aarch64_sys_reg_deprecated_p and warn about the deprecated
system registers.
gas/testsuite/
* gas/aarch64/deprecated.d: New file.
* gas/aarch64/deprecated.l: New file.
* gas/aarch64/deprecated.s: New file.
* gas/aarch64/sysreg-1.s: Add tests.
* gas/aarch64/sysreg-1.d: Add tests.
include/opcode/
* aarch64.h (aarch64_sys_reg): New typedef.
(aarch64_sys_regs): Change to define with the new type.
(aarch64_sys_reg_deprecated_p): Declare.
opcodes/
* aarch64-opc.c (F_DEPRECATED): New macro.
(aarch64_sys_regs): Update; flag "spsr_svc" and "spsr_hyp" with
F_DEPRECATED.
(aarch64_print_operand): Call aarch64_sys_reg_deprecated_p on
AARCH64_OPND_SYSREG.
Parsing a vector mov instruction currently leads to a phantom undefined
symbol being added to the symbol table. e.g.:
.text
mov x0, v0.D[0]
Produces an undefined symbol called "v0.D".
gas/ChangeLog:
2013-11-05 Will Newton <will.newton@linaro.org>
PR gas/16103
* config/tc-aarch64.c (parse_operands): Avoid trying to
parse a vector register as an immediate.
gas/testsuite/ChangeLog:
2013-11-05 Will Newton <will.newton@linaro.org>
* gas/aarch64/advsimd-mov-bad.d: New file.
* gas/aarch64/advsimd-mov-bad.s: Likewise.
Without this, constructs like "orw %rax, (%rax)" aren't being rejected
(other than any other wrong suffix/register combination).
gas/
2013-11-04 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (check_long_reg): Correct comment indentation.
(check_qword_reg): Correct comment and its indentation.
(check_word_reg): Extend comment and correct its indentation. Also
check for 64-bit register.
gas/testsuite/
2013-11-04 Jan Beulich <jbeulich@suse.com>
* gas/i386/x86-64-suffix-bad.[sl]: New.
* gas/i386/i386.exp: Run new test.
I think HJ has already fixed the binutils and ld tests with his
2013-09-27 readelf change, but this allows them to pass with wider
address output as per Nick's 2013-09-12 readelf change.
binutils/testsuite/
* binutils-all/x86-64/compressed-1a.d: Allow wide display of addresses.
gas/testsuite/
* gas/cfi/cfi-x86_64.d: Match when lacking end of section padding.
ld/testsuite/
* ld-pe/cfi.d: Allow wide display of addresses.
This defines the ELF symbol st_other field used to encode the number
of instructions between a function "global entry" and its "local entry",
and adds support related to the local entry offset.
include/elf/
* ppc64.h (STO_PPC64_LOCAL_BIT, STO_PPC64_LOCAL_MASK): Define.
(ppc64_decode_local_entry, ppc64_encode_local_entry): New functions.
(PPC64_LOCAL_ENTRY_OFFSET, PPC64_SET_LOCAL_ENTRY_OFFSET): Define.
bfd/
* elf64-ppc.c (struct ppc_stub_hash_entry): Add "other".
(stub_hash_newfunc): Init new ppc_stub_hash_entry field, and one
we forgot, "plt_ent".
(ppc64_elf_add_symbol_hook): Check ELFv1 objects don't have
st_other bits only valid in ELFv2.
(ppc64_elf_merge_symbol_attribute): New function.
(ppc_type_of_stub): Add local_off param to test branch range.
(ppc_build_one_stub): Adjust destinations for ELFv2 locals.
(ppc_size_one_stub, toc_adjusting_stub_needed): Similarly.
(ppc64_elf_size_stubs): Pass local_off to ppc_type_of_stub.
Set "other" field.
(ppc64_elf_relocate_section): Adjust destination for ELFv2 local
calls.
gas/
* config/tc-ppc.c (md_pseudo_table): Add .localentry.
(ppc_elf_localentry): New function.
(ppc_force_relocation): Force relocs on all branches to localenty
symbols.
(ppc_fix_adjustable): Don't reduce such symbols to section+offset.
binutils/
* readelf.c (get_ppc64_symbol_other): New function.
(get_symbol_other): Use it for EM_PPC64.
Defines bits in ELF e_flags to differentiate ELFv2 objects from ELFv2,
adds .abiversion directive to explicitly choose the ABI, and code to
check and automatically select ABI.
include/elf/
* ppc64.h (EF_PPC64_ABI): Define.
bfd/
* elf64-ppc.c (abiversion, set_abiversion): New functions.
(ppc64_elf_get_synthetic_symtab): Handle ELFv2 objects without .opd.
(struct ppc_link_hash_table): Add opd_abi.
(ppc64_elf_check_relocs): Check no .opd with ELFv2.
(ppc64_elf_merge_private_bfd_data): New function.
(ppc64_elf_print_private_bfd_data): New function.
(ppc64_elf_tls_setup): Set htab->opd_abi.
(ppc64_elf_size_dynamic_sections): Don't emit OPD related dynamic
tags for ELFv2.
(ppc_build_one_stub): Use R_PPC64_IRELATIVE for ELFv2 ifunc.
(ppc64_elf_finish_dynamic_symbol): Likewise
binutils/
* readelf.c (get_machine_flags): Display ABI version for EM_PPC64.
gas/
* config/tc-ppc.c: Include elf/ppc64.h.
(ppc_abiversion): New variable.
(md_pseudo_table): Add .abiversion.
(ppc_elf_abiversion, ppc_elf_end): New functions.
* config/tc-ppc.h (md_end): Define.
This changes the behaviour of @h and @ha on PowerPC64 to report errors
on 32-bit overflow. The motivation for this change is that on
PowerPC64, most uses of @h and @ha modifiers and their corresponding
relocations are to build up 32-bit offsets. We'd like to know when
such offsets overflow. Only rarely do people use @h or @ha with the
high 32-bit modifiers to build a 64-bit constant. Those uses will now
need to use two new modifiers, @high and @higha, if the constant isn't
known at assembly time. For now, we won't report overflow at assembly
time..
This also fixes an error when applying some of the HIGHER and HIGHEST
relocations.
include/elf/
* ppc64.h (R_PPC64_ADDR16_HIGH, R_PPC64_ADDR16_HIGHA,
R_PPC64_TPREL16_HIGH, R_PPC64_TPREL16_HIGHA,
R_PPC64_DTPREL16_HIGH, R_PPC64_DTPREL16_HIGHA): New.
(IS_PPC64_TLS_RELOC): Match new tls relocs.
bfd/
* reloc.c (BFD_RELOC_PPC64_ADDR16_HIGH, BFD_RELOC_PPC64_ADDR16_HIGHA,
BFD_RELOC_PPC64_TPREL16_HIGH, BFD_RELOC_PPC64_TPREL16_HIGHA,
BFD_RELOC_PPC64_DTPREL16_HIGH, BFD_RELOC_PPC64_DTPREL16_HIGHA): New.
* elf64-ppc.c (ppc64_elf_howto_raw): Add entries for new relocs.
Make all _HA and _HI relocs report signed overflow.
(ppc64_elf_reloc_type_lookup): Handle new relocs.
(must_be_dyn_reloc, ppc64_elf_check_relocs): Likewise.
(dec_dynrel_count, ppc64_elf_relocate_section): Likewise.
(ppc64_elf_relocate_section): Don't apply 0x8000 adjust to
R_PPC64_TPREL16_HIGHER, R_PPC64_TPREL16_HIGHEST,
R_PPC64_DTPREL16_HIGHER, and R_PPC64_DTPREL16_HIGHEST.
* libbfd.h: Regenerate.
* bfd-in2.h: Regenerate.
gas/
* config/tc-ppc.c (SEX16): Don't mask.
(REPORT_OVERFLOW_HI): Define as zero.
(ppc_elf_suffix): Support @high, @higha, @dtprel@high, @dtprel@higha,
@tprel@high, and @tprel@higha modifiers.
(md_assemble): Ignore X_unsigned when applying 16-bit insn fields.
Add (disabled) code to check @h and @ha reloc overflow for powerpc64.
Handle new relocs.
(md_apply_fix): Similarly.
elfcpp/
* powerpc.h (R_PPC64_ADDR16_HIGH, R_PPC64_ADDR16_HIGHA,
R_PPC64_TPREL16_HIGH, R_PPC64_TPREL16_HIGHA,
R_PPC64_DTPREL16_HIGH, R_PPC64_DTPREL16_HIGHA): Define.
gold/
* powerpc.cc (Target_powerpc::Scan::check_non_pic): Handle new relocs.
(Target_powerpc::Scan::global, local): Likewise.
(Target_powerpc::Relocate::relocate): Likewise. Check for overflow
on all ppc64 @h and @ha relocs.
There's no real need to emit these always: They're needed only if we
indeed want to emit a localized symbol. Hence defer emission until we
at least did the basic early checks that would lead to no such symbol
getting emitted. This in particular avoids emitting such a symbol in
the majority of (if not all) "ld -r" cases.
I hope my set of cross build tests caught all the test cases needing
adjustment - please forgive if I missed a few.
bfd/
2013-10-29 Jan Beulich <jbeulich@suse.com>
* elflink.c (struct elf_outext_info): Add field file_sym_done.
(bfd_elf_final_link): Initialize new field. Move fake STT_FILE
symbol emission from here ...
(elf_link_output_extsym): ... to here.
gas/testsuite/
2013-10-29 Jan Beulich <jbeulich@suse.com>
* gas/microblaze/relax_size.elf: Drop expectation of no longer
present STT_FILE symbol.
* gas/microblaze/relax_size2.elf: Likewise.
ld/testsuite/
2013-10-29 Jan Beulich <jbeulich@suse.com>
* ld-cris/tls-e-tpoffcomm1.d: Drop expectation of no longer
present STT_FILE symbol.
* ld-mmix/bpo-18.d: Likewise.
* ld-mmix/bpo-22.d: Likewise.
* ld-mmix/greg-6.d: Likewise.
* ld-mmix/greg-7.d: Likewise.
* ld-mmix/loc4.d: Likewise.
* ld-mmix/local1.d: Likewise.
* ld-mmix/local3.d: Likewise.
* ld-mmix/local5.d: Likewise.
* ld-mmix/local7.d: Likewise.
* ld-mmix/loct-1.d: Likewise.
* ld-sh/sh64/abi32.xd: Likewise.
* ld-sh/sh64/abi64.xd: Likewise.
* ld-sh/sh64/cmpct1.xd: Likewise.
* ld-sh/sh64/crange1.rd: Likewise.
* ld-sh/sh64/crange2.rd: Likewise.
* ld-sh/sh64/crange3-cmpct.rd: Likewise.
* ld-sh/sh64/crange3-media.rd: Likewise.
* ld-sh/sh64/crange3.rd: Likewise.
* ld-sh/sh64/crangerel1.rd: Likewise.
* ld-sh/sh64/crangerel2.rd: Likewise.
* ld-sh/sh64/mix1.xd: Likewise.
* ld-sh/sh64/mix2.xd: Likewise.
* ld-sh/sh64/shdl32.xd: Likewise.
* ld-sh/sh64/shdl64.xd: Likewise.
* config/tc-mips.c (fpr_read_mask): Test MSA registers.
(fpr_write_mask): Test MSA registers.
(can_swap_branch_p): Check fpr write followed by fpr read.
opcodes/
* nios2-opc.c (nios2_builtin_reg): Use "sstatus" rather than "ba"
as the primary name of r30.
gas/
* config/tc-nios2.c (nios2_consume_arg): Make the "ba" warning
also test/refer to "sstatus". Reformat the warning message.
gas/testsuite/
* gas/nios2/warn_nobreak.l: Update text of warning messages.
* gas/nios2/registers.s: Use "sstatus" rather than "ba"
as the primary name of r30.
* gas/nios2/registers.d: Likewise.
2013-10-10 Jan Beulich <jbeulich@suse.com>
* tc-i386-intel.c (i386_intel_simplify_register): Suppress base/index
swapping for bndmk, bndldx, and bndstx.
for "<foo>a". Issue error messages for unrecognised or corrrupt
size extensions.
* gas/msp430/bad.s: New test: Checks erroneous size extensions.
* gas/msp430/bad.d: New test command file.
* gas/msp430/bad.l: New file: Expected error messages.
* gas/msp430/msp430.exp: Run the new test.
* gas/msp430/msp430x.s: Add "<foo>.a" aliases of "<foo>a"
instructions.
* gas/msp430/msp430x.d: Update expected disassembly.
(move_data): New variable.
(md_parse_option): Parse -md.
(msp430_section): New function. Catch references to the .bss or
.data sections and generate a special symbol for use by the libcrt
library.
(md_pseudo_table): Intercept .section directives.
(md_longopt): Add -md
(md_show_usage): Likewise.
(msp430_operands): Generate a warning message if a NOP is inserted
into the instruction stream.
* doc/c-msp430.texi (node MSP430 Options): Document -md option.
The existing code would accept VLD2.64 and similar undefined
instructions.
gas/ChangeLog:
2013-09-16 Will Newton <will.newton@linaro.org>
* config/tc-arm.c (do_neon_ld_st_interleave): Add constraint
disallowing element size 64 with interleave other than 1.
gas/testsuite/ChangeLog:
2013-09-16 Will Newton <will.newton@linaro.org>
* gas/arm/neon-ldst-es.d: Add VLD1.64 instructions.
* gas/arm/neon-ldst-es.s: Likewise.
* testsuite/gas/arm/neon-ldst-es-bad.d: New file.
* testsuite/gas/arm/neon-ldst-es-bad.l: Likewise.
* testsuite/gas/arm/neon-ldst-es-bad.s: Likewise.
* config/tc-ppc.c (md_apply_fix): Handle defined after use toc
symbols.
gas/testsuite/
* gas/ppc/aix.exp: Run xcoff-toc-1 test.
* gas/ppc/xcoff-toc-1.s, gas/ppc/xcoff-toc-1.d: New test.
* config/tc-arm.c (T16_32_TAB): Add _udf.
(do_t_udf): New function.
(insns): Add "udf".
* gas/arm/udf-bad.s: New file.
* gas/arm/udf-bad.d: New file.
* gas/arm/udf-bad.l: New file.
* gas/arm/udf.s: New file.
* gas/arm/udf.d: New file.
* gas/arm/udf.l: New file.
* arm-dis.c (arm_opcodes): Add udf.
(thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
(thumb32_opcodes): Add udf.w.
(print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
immediate is not suitable for the 32-bit ABI.
* gas/aarch64/illegal.s: Add illegal constant for logical
operation.
* gas/aarch64/illegal.l: Add expected error message.
NEON vector load and store instructions do not accept immediates
or pre-indexed base plus offset addressing modes, so make sure that
the assembler enforces this.
gas/ChangeLog:
2013-08-23 Will Newton <will.newton@linaro.org>
* config/tc-arm.c (do_neon_ldx_stx): Add extra constraints
for pre-indexed addressing modes.
* testsuite/gas/arm/neon-addressing-bad.l: Add test for
VLDn and VSTn instructions.
* testsuite/gas/arm/neon-addressing-bad.s: Likewise.
gas/testsuite/ChangeLog:
2013-08-23 Will Newton <will.newton@linaro.org>
* testsuite/gas/arm/neon-addressing-bad.l: Add test for
VLDn and VSTn instructions.
* testsuite/gas/arm/neon-addressing-bad.s: Likewise.
* mips.h (M_DEXT, M_DINS): Delete.
opcodes/
* micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
Use +H rather than +C for the real "dext".
* mips-opc.c (mips_builtin_opcodes): Likewise.
gas/
* config/tc-mips.c (report_bad_range, report_bad_field): Delete.
(macro): Remove M_DEXT and M_DINS handling.
gas/testsuite/
* gas/mips/ext-ill.l, gas/mips/mips64r2-ill.l: Expect DEXT and DINS
error messages to have the same form as the EXT and INS ones.
* gas/mips/micromips-insn32.d, gas/mips/micromips-noinsn32.d,
gas/mips/micromips-trap.d, gas/mips/micromips.d,
gas/mips/micromips@mips64r2.d, gas/mips/mips64r2.d: Expect
"dext" and "dins" instead of "dextm", "dextu", "dinsm" and "dinsu".
* config/tc-mips.c (mips_arg_info): Replace allow_nonconst and
lax_max with lax_match.
(match_int_operand): Update accordingly. Don't report an error
for !lax_match-only cases.
(match_insn): Replace more_alts with lax_match and use it to
initialize the mips_arg_info field. Add a complete_p parameter.
Handle implicit VU0 suffixes here.
(match_invalid_for_isa, match_insns, match_mips16_insns): New
functions.
(mips_ip, mips16_ip): Use them.
* config/tc-mips.c (mips_arg_info): Remove soft_match.
(match_out_of_range, match_not_constant): New functions.
(match_const_int): Remove fallback parameter and check for soft_match.
Use match_not_constant.
(match_mapped_int_operand, match_addiusp_operand)
(match_perf_reg_operand, match_save_restore_list_operand)
(match_mdmx_imm_reg_operand): Update accordingly. Use
match_out_of_range and set_insn_error* instead of as_bad.
(match_int_operand): Likewise. Use match_not_constant in the
!allows_nonconst case.
(match_float_constant): Report invalid float constants.
(match_insn, match_mips16_insn): Remove soft_match code. Rely on
match_float_constant to check for invalid constants. Fail the
match if match_const_int or match_float_constant return false.
(mips_ip): Update accordingly.
(mips16_ip): Likewise. Undo null termination of instruction name
once lookup is complete.
gas/testsuite/
* gas/mips/ext-ill.l, gas/mips/lui-1.l, gas/mips/mips16e-64.l,
gas/mips/mips32r2-ill-fp64.l, gas/mips/mips32r2-ill-nofp.l,
gas/mips/mips32r2-ill.l, gas/mips/mips64r2-ill.l,
gas/mips/octeon-ill.l, gas/mips/r5900-error-vu0.l,
gas/mips/vr5400-ill.l: Adjust expected errors.
* gas/mips/micromips-size-0.l,
gas/mips/micromips-size-0.s: Likewise. Add new tests.
* gas/mips/mips16e-save-err.s, gas/mips/mips16e-save-err.l: New test.
* gas/mips/mips.exp: Run it.
* config/tc-mips.c (mips_insn_error_format): New enum.
(mips_insn_error): New struct.
(insn_error): Change to a mips_insn_error.
(clear_insn_error, set_insn_error_format, set_insn_error)
(set_insn_error_i, set_insn_error_ss, report_insn_error): New
functions.
(mips_parse_argument_token, md_assemble, match_insn)
(match_mips16_insn): Use them instead of manipulating insn_error
directly.
(mips_ip, mips16_ip): Likewise. Simplify control flow.
gas/testsuite/
* gas/mips/micromips-ill.l: Expect "floating-point expression required"
* config/tc-mips.c (normalize_constant_expr): Move further up file.
(normalize_address_expr): Likewise.
(match_insn, match_mips16_insn): New functions, split out from...
(mips_ip, mips16_ip): ...here.
2013-08-06 Jürgen Urban <JuergenUrban@gmx.de>
* mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
VCLIPW.
gas/
2013-08-06 Jürgen Urban <JuergenUrban@gmx.de>
* config/tc-mips.c (match_vu0_suffix_operand): Allow single-channel
suffixes to be elided too.
(mips_lookup_insn): Don't reject INSN2_VU0_CHANNEL_SUFFIX here.
(mips_ip): Assume .xyzw if no VU0 suffix is specified. Allow +N
to be omitted too.
gas/testsuite/
2013-08-06 Jürgen Urban <JuergenUrban@gmx.de>
* gas/mips/r5900-error-vu0.s, gas/mips/r5900-error-vu0.l,
gas/mips/r5900-full-vu0.s, gas/mips/r5900-full-vu0.d: Allow
single-channel suffixes to be elided.
2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
Richard Sandiford <rdsandiford@googlemail.com>
* mips.h: Document new VU0 operand characters.
(OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
(OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
(OP_REG_R5900_ACC): New mips_reg_operand_types.
(INSN2_VU0_CHANNEL_SUFFIX): New macro.
(mips_vu0_channel_mask): Declare.
opcodes/
2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
Richard Sandiford <rdsandiford@googlemail.com>
* mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
(print_vu0_channel): New function.
(print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
(print_insn_args): Handle '#'.
(print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
* mips-opc.c (mips_vu0_channel_mask): New constant.
(decode_mips_operand): Handle new VU0 operand types.
(VU0, VU0CH): New macros.
(mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E"
for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2.
Use "+6" rather than "G" for QMFC2 and QMTC2.
gas/
2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
Richard Sandiford <rdsandiford@googlemail.com>
* config/tc-mips.c (MAX_OPERANDS): Bump to 6.
(RWARN): Bump to 0x8000000.
(RTYPE_VI, RTYPE_VF, RTYPE_R5900_I, RTYPE_R5900_Q, RTYPE_R5900_R)
(RTYPE_R5900_ACC): New register types.
(RTYPE_MASK): Include them.
(R5900_I_NAMES, R5900_Q_NAMES, R5900_R_NAMES, R5900_ACC_NAMES): New
macros.
(reg_names): Include them.
(mips_parse_register_1): New function, split out from...
(mips_parse_register): ...here. Add a channels_ptr parameter.
Look for VU0 channel suffixes when nonnull.
(reg_lookup): Update the call to mips_parse_register.
(mips_parse_vu0_channels): New function.
(OT_CHANNELS, OT_DOUBLE_CHAR): New mips_operand_token_types.
(mips_operand_token): Add a "channels" field to the union.
Extend the comment above "ch" to OT_DOUBLE_CHAR.
(mips_parse_base_start): Match -- and ++. Handle channel suffixes.
(mips_parse_argument_token): Handle channel suffixes here too.
(validate_mips_insn): Handle INSN2_VU0_CHANNEL_SUFFIX.
Ignore OP_VU0_MATCH_SUFFIX when calculating the used bits.
Handle '#' formats.
(md_begin): Register $vfN and $vfI registers.
(operand_reg_mask): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
(convert_reg_type): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
(match_vu0_suffix_operand): New function.
(match_operand): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
(macro): Use "+7" rather than "E" for LDQ2 and STQ2.
(mips_lookup_insn): New function.
(mips_ip): Use it. Allow "+K" operands to be elided at the end
of an instruction. Handle '#' sequences.
gas/testsuite/
2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
* gas/mips/r5900-vu0.d: Expect $vfN and $viN instead of numeric
coprocessor registers.
* gas/mips/r5900-all-vu0.s, gas/mips/r5900-all-vu0.d,
gas/mips/r5900-full-vu0.s, gas/mips/r5900-full-vu0.d,
gas/mips/r5900-error-vu0.s, gas/mips/r5900-error-vu0.l: New tests.
* gas/mips/mips.exp: Run them.
* mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
(mips_int_operand_min, mips_int_operand_max): New functions.
(mips_decode_pcrel_operand): Use mips_decode_int_operand.
opcodes/
* mips-formats.h (PCREL): Reorder parameters and update the definition
to match new mips_pcrel_operand layout.
(JUMP, JALX, BRANCH): Update accordingly.
* mips16-opc.c (decode_mips16_operand): Likewise.
gas/
* config/tc-mips.c (match_int_operand): Use mips_int_operand_min
and mips_int_operand_max.
(mips16_immed_operand, mips16_immed_operands, MIPS16_NUM_IMMED):
Delete.
(mips16_immed_operand, mips16_immed_in_range_p): New functions.
(mips16_immed, mips16_extended_frag): Use them. Use mips_int_operand
instead of mips16_immed_operand.
* config/tc-mips.c (mips16_macro): Don't use move_register.
(mips16_ip): Allow macros to use 'p'.
gas/testsuite/
* gas/mips/mips16-macro.s, gas/mips/mips16-macro.d: New test.
* gas/mips/mips.exp: Run it.
* mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
(MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
(MIPS16_INSN_COND_BRANCH): Delete.
opcodes/
* mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
(WR_SP): Replace with...
(MOD_SP): ...this.
(mips16_opcodes): Update accordingly.
* mips-dis.c (print_insn_mips16): Likewise.
gas/
* config/tc-mips.c (compact_branch_p, uncond_branch_p): Use the same
flags for MIPS16 and non-MIPS16 instructions.
(gpr_mod_mask): Move the INSN2_MOD_SP case outside the micromips block.
(gpr_read_mask): Use INSN2_READ_GPR_31 for MIPS16 instructions too.
(gpr_write_mask): Remove MIPS16_INSN_WRITE_SP handling.
(can_swap_branch_p, get_append_method): Use the same flags for MIPS16
and non-MIPS16 instructions. Fix formatting.
gas/
* config/tc-aarch64.c (enum aarch64_abi_type): New enumeration tag.
(AARCH64_ABI_LP64, AARCH64_ABI_ILP32): New enumerators.
(aarch64_abi): New variable.
(ilp32_p): Change to be a macro.
(aarch64_opts): Remove the support for option -milp32 and -mlp64.
(struct aarch64_option_abi_value_table): New struct.
(aarch64_abis): New table.
(aarch64_parse_abi): New function.
(aarch64_long_opts): Add entry for -mabi=.
* doc/as.texinfo (Target AArch64 options): Document -mabi.
* doc/c-aarch64.texi: Likewise.
gas/testsuite/
* gas/aarch64/ilp32-basic.d (#as): Update to use -mabi=ilp32
RX610.
* config/rx-parse.y: (rx_check_float_support): Add function to
check floating point operation support for target RX100 and
RX200.
* config/tc-rx.c: Add CPU options RX100, RX200, RX600, and RX610.
* doc/c-rx.texi: Add -mcpu option to recognize macros for RX100,
RX200, RX600, and RX610
* config/tc-mips.c (mips_prefer_vec_regno, mips_parse_register):
New functions, split out from...
(reg_lookup): ...here. Remove itbl support.
(reglist_lookup): Delete.
(mips_operand_token_type): New enum.
(mips_operand_token): New structure.
(mips_operand_tokens): New variable.
(mips_add_token, mips_parse_base_start, mips_parse_argument_token)
(mips_parse_arguments): New functions.
(md_begin): Initialize mips_operand_tokens.
(mips_arg_info): Add a token field. Remove optional_reg field.
(match_char, match_expression): New functions.
(match_const_int): Use match_expression. Remove "s" argument
and return a boolean result. Remove O_register handling.
(match_regno, match_reg, match_reg_range): New functions.
(match_int_operand, match_mapped_int_operand, match_msb_operand)
(match_reg_operand, match_reg_pair_operand, match_perf_reg_operand)
(match_addiusp_operand, match_clo_clz_dest_operand)
(match_lwm_swm_list_operand, match_entry_exit_operand)
(match_save_restore_list_operand, match_mdmx_imm_reg_operand)
(match_tied_reg_operand): Remove "s" argument and return a boolean
result. Match tokens rather than text. Update calls to
match_const_int. Rely on match_regno to call check_regno.
(match_pcrel_operand, match_pc_operand): Replace "s" argument with
"arg" argument. Return a boolean result.
(parse_float_constant): Replace with...
(match_float_constant): ...this new function.
(match_operand): Remove "s" argument and return a boolean result.
Update calls to subfunctions.
(mips_ip, mips16_ip): Call mips_parse_arguments. Use match routines
rather than string-parsing routines. Update handling of optional
registers for token scheme.
gas/testsuite/
* gas/mips/vr5400-ill.s, gas/mips/vr5400-ill.l: Add some more cases.
* gas/mips/micromips-ill.s, gas/mips/micromips-ill.l: New test.
* gas/mips/mips.exp: Run it.
* config/tc-mips.c (mips32_to_16_reg_map): Delete.
(match_entry_exit_operand): New function.
(match_save_restore_list_operand): Likewise.
(match_operand): Use them.
(check_absolute_expr): Delete.
(mips16_ip): Rewrite main parsing loop to use mips_operands.
