Commit Graph

3311 Commits

Author SHA1 Message Date
Claudiu Zissulescu
0f3f71676a [ARC] Update disassembler opcode selection
New instruction are added, and some of them are overlapping. Update
disassembler to correctly recognize them. Introduce nps400 option.

opcodes/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
	and MPY class instructions.
	(parse_option): Add nps400 option.
	(print_arc_disassembler_options): Add nps400 info.

gas/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* testsuite/gas/arc/nps400-6.d: Update test.
2019-07-24 16:52:23 +03:00
Claudiu Zissulescu
7e126ba31a [ARC] Update ARC opcode table
Update ARC opcode table by cleaning up invalid instructions, and fixing wrong encodings.

opcodes/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-ext-tbl.h (bspeek): Remove it, added to main table.
	(bspop): Likewise.
	(modapp): Likewise.
	* arc-opc.c (RAD_CHK): Add.
	* arc-tbl.h: Regenerate.

include/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* include/opcode/arc.h (FASTMATH): Add.
	(SWITCH): Likewise.
2019-07-24 16:46:01 +03:00
Kyrylo Tkachov
a028026d2f [AArch64] Add support for GMID_EL1 register for +memtag
We're missing support for the GMID_EL1 system register from the Memory Tagging Extension in binutils.
This is specified at:
https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/gmid_el1

This simple patch adds the support for this read-only register.
Tested make check on gas.
2019-07-23 15:54:54 +01:00
Nick Clifton
ac79ff9ed2 Add Changelog entry missing from previous delta.
2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>

	* arm-dis.c (is_mve_unpredictable): Stop marking some MVE
	instructions as UNPREDICTABLE.
2019-07-23 09:47:06 +01:00
Barnaby Wilks
236ab0c60c This patch addresses the change in the June Armv8.1-M Mainline specification, that marks certain MVE instructions as no longer UNPREDICTABLE when a source operand is the same as a destination operand for a 32-bit element size.
The instructions that this change apply to are:

  VQDMLADH, VQRDMLADH, VQDMLSDH, VQRDMLSDH

The updated documentation is here: https://static.docs.arm.com/ddi0553/bh/DDI0553B_h_armv8m_arm.pdf

Fixed this by removing the check for this warning from GAS as well as opcodes.

Added testcases to test that the warning is not generated for the instructions that have a 32-bit element size
and the same source and destination operand. Also fixed tests that would previously check for this warning.

gas	* config/tc-arm.c (do_mve_vqdmladh): Remove check for UNPREDICTABLE.
	* testsuite/gas/arm/mve-vqdmladh-bad.l: Remove tests.
	* testsuite/gas/arm/mve-vqdmladh-bad.s: Remove tests.
	* testsuite/gas/arm/mve-vqdmladh.d: New tests.
	* testsuite/gas/arm/mve-vqdmladh.s: New tests.
	* testsuite/gas/arm/mve-vqdmlsdh-bad.l: Remove tests.
	* testsuite/gas/arm/mve-vqdmlsdh-bad.s: Remove tests.
	* testsuite/gas/arm/mve-vqdmlsdh.d: New tests.
	* testsuite/gas/arm/mve-vqdmlsdh.s: New tests.

opcodes	* arm-dis.c (is_mve_unpredictable): Stop marking some MVE
	instructions as UNPREDICTABLE.
2019-07-22 13:18:27 +01:00
Jose E. Marchesi
231097b03a cpu,opcodes,gas: use %r0 and %r6 instead of %a and %ctf in eBPF disassembler
This patch changes the eBPF CPU description to prefer the register
names %r0 and %r6 instead of %a and %ctx when disassembling.  This
matches better with the current practice, vs. cBPF.

It also updates the GAS tests in order to reflect this change.
Tested in a x86_64 host.

cpu/ChangeLog:

2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf.cpu (h-gpr): when disassembling, use %r0 and %r6 instead of
	%a and %ctx.

opcodes/ChangeLog:

2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf-desc.c: Regenerated.

gas/ChangeLog:

2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* testsuite/gas/bpf/alu.d: Use %r6 instead of %ctx.
	* testsuite/gas/bpf/lddw-be.d: Likewise.
	* testsuite/gas/bpf/lddw.d: Likewise.
	* testsuite/gas/bpf/alu-be.d: Likewise.
	* testsuite/gas/bpf/alu32.d: Likewise.
2019-07-19 15:35:43 +02:00
Jan Beulich
1d942ae908 x86: drop stale Mem enumerator
This was supposed to also be removed by c48dadc9a8 ('x86: drop "mem"
operand type attribute').  It's odd enough that this hasn't caused
build issues, considering the careful use of OTunused (apparently to
avoid "missing initializer" warnings).

To avoid such happening again introduce compile time consistency
checks.
2019-07-17 09:15:49 +02:00
Jan Beulich
dfd6917457 x86: make RegMem an opcode modifier
... instead of an operand type bit: It's an insn property, not an
operand one.  There's just one actual change to be made to the
templates: Most are now required to have the (unswapped) destination go
into ModR/M.rm, so VMOVD template needs its opcode adjusted accordingly
and its operands swapped.  {,V}MOVS{S,D}, otoh, are left alone in this
regard, as otherwise generated code would differ from what we've been
producing so far (which I don't think is wanted).

Take the opportunity and add a missing IgnoreSize to pextrb (leading to
an error in 16-bit mode), and take the liberty to once again drop stray
IgnoreSize attributes from lines changed and neighboring related ones.
2019-07-16 09:31:36 +02:00
Jan Beulich
21df382b91 x86: fold SReg{2,3}
They're the only exception to there generally being no mix of register
kinds possible in an insn operand template, and there being two bits per
operand for their representation is also quite wasteful, considering the
low number of uses.  Fold both bits and deal with the little bit of
fallout.

Also take the liberty and drop dead code trying to set REX_B: No segment
register has RegRex set on it.

Additionally I was quite surprised that PUSH/POP with the permitted
segment registers is not covered by the test cases.  Add the missing
pieces.
2019-07-16 09:30:29 +02:00
Jose E. Marchesi
3719fd55b6 cpu,opcodes,gas: fix explicit arguments to eBPF ldabs instructions
This patch fixes the eBPF CPU description in order to reflect the
right explicit arguments passed to the ldabs{b,h,w,dw} instructions,
updates the corresponding GAS tests, and updates the BPF section of
the GAS manual.

cpu/ChangeLog:

2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf.cpu (dlabs): New pmacro.
	(dlind): Likewise.

opcodes/ChangeLog:

2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf-desc.c: Regenerate.
	* bpf-opc.c: Likewise.
	* bpf-opc.h: Likewise.

gas/ChangeLog:

2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* testsuite/gas/bpf/mem.s: ldabs instructions do not take a `src'
	register as an argument.
	* testsuite/gas/bpf/mem.d: Updated accordingly.
	* testsuite/gas/bpf/mem-be.d: Likewise.
	* doc/c-bpf.texi (BPF Opcodes): Update to reflect the correct
	explicit arguments to ldabs and ldind instructions.
2019-07-15 16:00:28 +02:00
Jose E. Marchesi
92434a14b9 cpu,opcodes,gas: fix arguments to ldabs and ldind eBPF instructions
The eBPF non-generic load instructions ldind{b,h,w,dw} and
ldabs{b,h,w,dw} do not take an explicit destination register as an
argument.  Instead, they put the loaded value in %r0, implicitly.

This patch fixes the CPU BPF description to not expect a 'dst'
argument in these arguments, regenerates the corresponding files in
opcodes, and updates the impacted GAS tests.

Tested in a x86-64 host.

cpu/ChangeLog:

2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf.cpu (dlsi): ldabs and ldind instructions do not take an
	explicit 'dst' argument.

opcodes/ChangeLog:

2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf-desc.c: Regenerate.
	* bpf-opc.c: Likewise.

gas/ChangeLog:

2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* testsuite/gas/bpf/mem.s: Do not use explicit arguments for
	ldabs and ldind instructions.
	* testsuite/gas/bpf/mem.d: Updated accordingly.
	* testsuite/gas/bpf/mem-be.d: Likewise.
2019-07-14 14:45:31 +02:00
Hans-Peter Nilsson
43dd762689 arm-dis.c (print_insn_coprocessor): Rename index to index_operand.
Older gcc warns, arguably incorrectly, about name collisions between
global functions and function-local variable names.  Consesus has been
to rename local variables whenever this is spotted, hence committed as
obvious.  Note the pre-existing variable named idx; "index_operand"
seemed logical given the context.

	* arm-dis.c (print_insn_coprocessor): Rename index to
	index_operand.
2019-07-10 18:42:06 +02:00
Jim Wilson
98602811d8 Kito's 5-part patch set to improve .insn support.
From Kito Cheng <kito.cheng@sifive.com>
	gas/ChangeLog
	* doc/c-riscv.texi (Instruction Formats): Add r4 type.
	* testsuite/gas/riscv/insn.d: Add testcase for r4 type.
	* testsuite/gas/riscv/insn.s: Ditto.
	* doc/c-riscv.texi (Instruction Formats): Add b and j type.
	* testsuite/gas/riscv/insn.d: Add test case for b and j type.
	* testsuite/gas/riscv/insn.s: Ditto.
	* testsuite/gas/riscv/insn.s: Correct instruction type for load
	and store.
	* testsuite/gas/riscv/insn.d: Using regular expression to match
	address.
	* doc/c-riscv.texi (Instruction Formats): Fix encoding table for SB
	type and fix typo.
	opcode/ChangeLog
	* riscv-opc.c (riscv_insn_types): Add r4 type.
	* riscv-opc.c (riscv_insn_types): Add b and j type.
	* opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
	format for sb type and correct s type.
2019-07-05 15:19:11 +08:00
Richard Sandiford
01c1ee4a70 [AArch64] Allow MOVPRFX to be used with FMOV
The entry for the FMOV alias of FCPY was missing C_SCAN_MOVPRFX.
(The entry for FCPY itself was OK.)

This was the only /m-predicated instruction I could see that was
missing the flag.

2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>

opcodes/
	* aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
	SVE FMOV alias of FCPY.

gas/
	* testsuite/gas/aarch64/sve-movprfx_27.s,
	* testsuite/gas/aarch64/sve-movprfx_27.d: New test.
2019-07-02 10:52:16 +01:00
Richard Sandiford
83adff695c [AArch64] Add missing C_MAX_ELEM flags for SVE conversions
SVE FCVTZS, FCVTZU, SCVTF and UCVTF need the same treatment as FCVT:
the register size used in a predicated MOVPRFX must be the wider of
the destination and source sizes.

Since I was adding a (supposedly) complete set of tests for converts,
it seemed more consistent to add a complete set of tests for shifts
as well, even though there's no bug to fix there.

2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>

opcodes/
	* aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
	to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.

gas/
	* testsuite/gas/aarch64/sve-movprfx_26.s: Also test FCVTZS, FCVTZU,
	SCVTF, UCVTF, LSR and ASR.
	* testsuite/gas/aarch64/sve-movprfx_26.d: Update accordingly.
	* testsuite/gas/aarch64/sve-movprfx_26.l: Likewise.
2019-07-02 10:51:09 +01:00
Richard Sandiford
8941884429 [AArch64] Fix bogus MOVPRFX warning for GPR form of CPY
One of the MOVPRFX tests has:

  output register of preceding `movprfx' used as input at operand 3 -- `cpy z1.d,p1/m,x1'

But X1 and Z1 are not the same register, so the instruction is
actually OK.

2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>

opcodes/
	* aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
	registers in an instruction prefixed by MOVPRFX.

gas/
	* testsuite/gas/aarch64/sve-movprfx_25.s: Allow CPY Z1.D.P1/M,X1
	to be prefixed by MOVPRFX.
	* testsuite/gas/aarch64/sve-movprfx_25.d: Update accordingly.
	* testsuite/gas/aarch64/sve-movprfx_25.l: Likewise.
2019-07-02 10:51:05 +01:00
Matthew Malcomson
41be57caf3 [gas][aarch64][SVE2] Fix pmull{t,b} requirement on SVE2-AES
I had mistakenly given all variants of the new SVE2 instructions
pmull{t,b} a dependency on the feature +sve2-aes.

Only the variant specifying .Q -> .D  sizes should have that
restriction.

This patch fixes that mistake and updates the testsuite to have extra
tests (matching the given set of tests per line in aarch64-tbl.h that
the rest of the SVE2 tests follow).

We also add a line in the documentation of the command line to clarify
how to enable `pmull{t,b}` of this larger size.  This is needed because
all other instructions gated under the `sve2-aes` architecture extension
are marked in the instruction documentation by an `HaveSVE2AES` check
while pmull{t,b} is gated under the `HaveSVE2PMULL128` check.

Regtested targeting aarch64-linux.

gas/ChangeLog:

2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>

	* testsuite/gas/aarch64/illegal-sve2-aes.d: Update tests.
	* testsuite/gas/aarch64/illegal-sve2.l: Update tests.
	* doc/c-aarch64.texi: Add special note of pmull{t,b}
	instructions under the sve2-aes architecture extension.
	* testsuite/gas/aarch64/illegal-sve2.s: Add small size
	pmull{t,b} instructions.
	* testsuite/gas/aarch64/sve2.d: Add small size pmull{t,b}
	disassembly.
	* testsuite/gas/aarch64/sve2.s: Add small size pmull{t,b}
	instructions.

include/ChangeLog:

2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (enum aarch64_insn_class): sve_size_013
	renamed to sve_size_13.

opcodes/ChangeLog:

2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
	sve_size_13 icode to account for variant behaviour of
	pmull{t,b}.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
	sve_size_13 icode to account for variant behaviour of
	pmull{t,b}.
	* aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
	(OP_SVE_VVV_Q_D): Add new qualifier.
	(OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
	(struct aarch64_opcode): Split pmull{t,b} into those requiring
	AES and those not.
2019-07-01 15:17:22 +01:00
Jan Beulich
9d3bf266fd x86: drop Vec_Imm4
It is pretty wasteful to have a per-operand flag which is used in
exactly 4 cases. It can be relatively easily replaced, and by doing so
I've actually found some dead code to remove at the same time (there's
no case of ImmExt set at the same time as Vec_Imm4).
2019-07-01 08:38:50 +02:00
Jan Beulich
c3949f432f x86: limit ImmExt abuse
In quite a few cases ImmExt gets used when there's not really any
immediate, but rather a degenerate ModR/M byte. ENCL{S,U} show how this
case is supposed to be dealt with. Eliminate most abuses, leaving in
place (for now) only ones where process_immext() is involved.
2019-07-01 08:37:40 +02:00
Jan Beulich
5641ec015a x86: optimize AND/OR with twice the same register
It seems to be not uncommon for people to use AND or OR in this form for
just setting the status flags. TEST, which doesn't write to any
register other than EFLAGS, ought to be preferred. Make the change only
for -O2 and above though, at least for now.
2019-07-01 08:35:08 +02:00
Jan Beulich
79dec6b7ba x86-64: optimize certain commutative VEX-encoded insns
When they're in the 0F opcode space, swapping their source operands may
allow switching from 3-byte to 2-byte VEX prefix encoding. Note that NaN
behavior precludes us doing so for many packed and scalar floating point
insns; such an optimization would need to be done by the compiler
instead in this case, when it knows that NaN-s have undefined behavior
anyway.

While for explicitly specified AVX/AVX2 insns the optimization (for now
at least) gets done only for -O2 and -Os, it is utilized by default in
SSE2AVX mode, as there we're re-writing the programmer's specified insns
anyway.

Rather than introducing a new attribute flag, the change re-uses one
which so far was meaningful only for EVEX-encoded insns.
2019-07-01 08:33:56 +02:00
Jan Beulich
a0a1771e89 x86: optimize EVEX packed integer logical instructions
As long as there's no write mask as well as no broadcast, and as long
as the scaled Disp8 wouldn't result in a shorter EVEX encoding, encode
VPAND{D,Q}, VPANDN{D,Q}, VPOR{D,Q}, and VPXOR{D,Q} acting on only the
lower 16 XMM/YMM registers using their VEX equivalents with -O1.

Also take the opportunity and avoid looping twice over all operands
when dealing with memory-with-displacement ones.
2019-07-01 08:31:14 +02:00
Jan Beulich
cd546e7bd2 x86: add missing pseudo ops for VPCLMULQDQ ISA extension
While the ISA extensions doc suggests them to be made available just
like the SDM does for the PCLMULQDQ ISA extension, these weren't added
when supposrt for the new extension was introduced.

Also make sure the 64-bit non-AVX512 test actually tests VEX encodings,
not EVEX ones.
2019-07-01 08:28:58 +02:00
Jan Beulich
e3bba3fc75 x86: drop bogus Disp8MemShift attributes
In commit dc821c5f9a ("x86: replace Reg8, Reg16, Reg32, and Reg64") I
apparently blindly copied the original register/memory templates into
separate ones, in particular without removing the Disp8MemShift which
are applicable to templates with memory operands only.
2019-07-01 08:27:38 +02:00
Jan Beulich
36cc073ef4 x86: remove ModRM.mod decoding layer from AVX512F VMOVS{S,D}
Just like their AVX counterparts they can utilize XMVexScalar /
EXdVexScalarS / EXqVexScalarS taking care of dropping the middle operand
for their memory forms.
2019-07-01 08:23:41 +02:00
Jan Beulich
219920a7c4 x86: drop a few dead macros 2019-07-01 08:22:37 +02:00
H.J. Lu
e395f487b3 i386: Check vector length for scatter/gather prefetch instructions
Since not all vector lengths are supported by scatter/gather prefetch
instructions, decode them only with supported vector lengths.

gas/

	PR binutils/24719
	* testsuite/gas/i386/disassem.s: Add test for vgatherpf0dps
	with invalid vector length.
	* testsuite/gas/i386/x86-64-disassem.s: Likewise.
	* testsuite/gas/i386/disassem.d: Updated.
	* testsuite/gas/i386/x86-64-disassem.d: Likewise.

opcodes/

	PR binutils/24719
	* i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
	EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
	EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
	EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
	EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
	EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
	EVEX_LEN_0F38C7_R_6_P_2_W_1.
	* i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
	PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
	PREFIX_EVEX_0F38C6_REG_6 entries.
	* i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
	EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
	EVEX_W_0F38C7_R_6_P_2 entries.
	* i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
	EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
	EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
	EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
	EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
	EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
	EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
2019-06-27 13:39:32 -07:00
Jan Beulich
2b7bcc8740 x86: fold AVX scalar to/from int conversion insns
There's no point doing a separate decode of the VEX.L bit - both decoded
forms are identical.
2019-06-27 08:50:28 +02:00
Jan Beulich
c1dc7af521 x86: allow VEX et al encodings in 16-bit (protected) mode
These encodings aren't valid in real and VM86 modes, but they are very
well usable in 16-bit protected mode.

A few adjustments in the disassembler tables are needed where Ev or Gv
were wrongly used. Additionally an adjustment is needed to avoid
printing "addr32" when that's already recognizable by the use of %eiz.

Furthermore the Iq operand template was wrong for XOP:0Ah encoding
insns: They're having a uniform 32-bit immediate. Drop Iq and introduce
Id instead.

Clone a few existing test cases to exercise assembler and disassembler.
2019-06-27 08:49:40 +02:00
Jim Wilson
d7560e2df5 RISC-V: Make objdump disassembly work right for binary files.
Without the ELF header to set info->endian, it ends up as BFD_UNKNOWN_ENDIAN
which gets printed as big-endian.  But RISC-V instructions are always little
endian, so we can set endian_code correctly, and then set display_endian from
that.  This is similar to how the aarch64 support works, but without the
support for constant pools, as we don't have that on RISC-V.

	opcodes/
	PR binutils/24739
	* riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
	Set info->display_endian to info->endian_code.
2019-06-26 17:17:09 -07:00
Jan Beulich
2c70385689 x86: correct / adjust debug printing
For quite some time we've been using combinations of bits for
specifying various registers in operands and templates. I think it was
Alan who had indicated that likely the debug printing would need
adjustment as a result. Here we go.

Accumulator handling for GPRs gets changed to match that for FPU regs.
For this to work, OPERAND_TYPE_ACC{32,64} get repurposed, with their
original uses replaced by direct checks of the two bits of interest,
which is cheaper than operand_type_equal() invocations.

For SIMD registers nothing similar appears to be needed, as respective
operands get stripped from the (copy of the) template before pt() is
reached.

The type change on pi() is to silence a compiler diagnostic. Arguably
its other parameter could also be const-qualified.
2019-06-25 09:41:33 +02:00
Jan Beulich
54fbadc0c3 x86: drop dqa_mode
I assume this mode was needed when EVEX.W handling wasn't really correct
yet for other than 64-bit mode. It's clearly not needed anymore. Its
elimination also allows dropping the EVEX.W split of VCVT{,U}SI2SS. (For
the record, the dropped mode would have been wrong if used in any table
entry not already guaranteeing EVEX.W=1.)
2019-06-25 09:35:17 +02:00
Jan Beulich
a280ab8e81 x86: simplify OP_I64()
The only meaningful difference from OP_I() is the handling of the
VEX.W=1 case in 64-bit mode for bytemode being v_mode. Funnel
everything else into OP_I(), and drop no longer needed local
variables.
2019-06-25 09:35:17 +02:00
Jan Beulich
e1a1babdad x86: fix (dis)assembly of certain SSE2 insns in 16-bit mode
MOVNTI was wrongly assembled with a 66h prefix. Add IgnoreSize to
address this. It and the scalar to/from integer conversion insns also
were also wrongly using Ev / Gv, leading to 16-bit register names being
printed when 32-bit ones were meant.

Clone the 32-bit SSE2 test to cover both assembler and disassembler.
2019-06-25 09:35:17 +02:00
Jan Beulich
b8364fa775 x86-64: also optimize ANDQ with immediate fitting in 7 bits
The same reasoning applies here as did/does for immediates fitting in
31 bits.
2019-06-25 09:35:17 +02:00
H.J. Lu
ad692897c1 i386: Break i386-dis-evex.h into small files
Break i386-dis-evex.h into small files such that each file is included
just once.

	* i386-dis-evex.h: Break into ...
	* i386-dis-evex-len.h: New file.
	* i386-dis-evex-mod.h: Likewise.
	* i386-dis-evex-prefix.h: Likewise.
	* i386-dis-evex-reg.h: Likewise.
	* i386-dis-evex-w.h: Likewise.
	* i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
	i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
	i386-dis-evex-mod.h.
2019-06-21 13:18:41 -07:00
H.J. Lu
f0a6222e30 i386: Check vector length for EVEX broadcast instructions
Since not all vector lengths are supported by EVEX broadcast instructions,
decode them only with supported vector lengths.

gas/

	PR binutils/24700
	* testsuite/gas/i386/disassem.s: Add test for vbroadcasti32x8
	with invalid vector length.
	* testsuite/gas/i386/x86-64-disassem.s: Likewise.
	* testsuite/gas/i386/disassem.d: Updated.
	* testsuite/gas/i386/x86-64-disassem.d: Likewise.

opcodes/

	PR binutils/24700
	* i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
	EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
	EVEX_W_0F385B_P_2.
	(evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
	EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
	EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
	EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
	EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
	EVEX_LEN_0F385B_P_2_W_1.
	* i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
	(EVEX_LEN_0F3819_P_2_W_1): Likewise.
	(EVEX_LEN_0F381A_P_2_W_0): Likewise.
	(EVEX_LEN_0F381A_P_2_W_1): Likewise.
	(EVEX_LEN_0F381B_P_2_W_0): Likewise.
	(EVEX_LEN_0F381B_P_2_W_1): Likewise.
	(EVEX_LEN_0F385A_P_2_W_0): Likewise.
	(EVEX_LEN_0F385A_P_2_W_1): Likewise.
	(EVEX_LEN_0F385B_P_2_W_0): Likewise.
	(EVEX_LEN_0F385B_P_2_W_1): Likewise.
2019-06-19 10:01:42 -07:00
H.J. Lu
6e1c90b7f5 i386: Check vector length for vshufXXX/vinsertXXX/vextractXXX
Since not all vector lengths are supported by vshufXXX, vinsertXXX and
vextractXXX, decode them only with supported vector lengths.

gas/

	PR binutils/24691
	* testsuite/gas/i386/disassem.s: Add test for vshuff32x4 with
	invalid vector length.
	* testsuite/gas/i386/x86-64-disassem.s: Likewise.
	* testsuite/gas/i386/disassem.d: Updated.
	* testsuite/gas/i386/x86-64-disassem.d: Likewise.

opcodes/

	PR binutils/24691
	* i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
	EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
	EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
	(evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
	EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
	EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
	EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
	EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
	EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
	EVEX_LEN_0F3A43_P_2_W_1.
	* i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
	(EVEX_LEN_0F3A23_P_2_W_1): Likewise.
	(EVEX_LEN_0F3A38_P_2_W_0): Likewise.
	(EVEX_LEN_0F3A38_P_2_W_1): Likewise.
	(EVEX_LEN_0F3A39_P_2_W_0): Likewise.
	(EVEX_LEN_0F3A39_P_2_W_1): Likewise.
	(EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
	(EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
	(EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
	(EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
	(EVEX_LEN_0F3A43_P_2_W_0): Likewise.
	(EVEX_LEN_0F3A43_P_2_W_1): Likewise.
2019-06-17 10:21:36 -07:00
Nick Clifton
bcc5a6eb66 Updated French translation for the opcodes subdirectory.
* po/fr.po; Updated French translation.
2019-06-14 11:43:53 +01:00
Stafford Horne
e4c4ac46e8 opcodes/or1k: Regenerate opcodes
This picks up changes for:
  - new orfpx64a32 spec additions
  - new unordered instructions
  - symbol and documentation updates

opcodes/ChangeLog:

	* or1k-asm.c: Regenerated.
	* or1k-desc.c: Regenerated.
	* or1k-desc.h: Regenerated.
	* or1k-dis.c: Regenerated.
	* or1k-ibld.c: Regenerated.
	* or1k-opc.c: Regenerated.
	* or1k-opc.h: Regenerated.
	* or1k-opinst.c: Regenerated.
2019-06-13 06:16:19 +09:00
Peter Bergner
a0e44ef56c Add missing ChangeLog entries 2019-06-12 15:51:01 -05:00
Peter Bergner
6fbc939cfd Remove the ldmx mnemonic that never made it into POWER9.
opcodes/
	* ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.

gas/
	* testsuite/gas/ppc/power9.d: Delete ldmx tests.
	* testsuite/gas/ppc/power9.s: Likewise.
2019-06-12 15:48:53 -05:00
H.J. Lu
12efd68d15 i386: Check vector length for EVEX vextractfXX and vinsertfXX
Since not all vector lengths are supported by EVEX vextractfXX and
vinsertfXX, decode them only with supported vector lengths.

gas/

	PR binutils/24633
	* testsuite/gas/i386/disassem.s: Add tests for invalid vector
	lengths for EVEX vextractfXX and vinsertfXX.
	* testsuite/gas/i386/x86-64-disassem.s: Likewise.
	* testsuite/gas/i386/disassem.d: Updated.
	* testsuite/gas/i386/x86-64-disassem.d: Likewise.

opcodes/

	PR binutils/24633
	* i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
	EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
	(evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
	EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
	EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
	EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
	EVEX_LEN_0F3A1B_P_2_W_1.
	* i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
	(EVEX_LEN_0F3A18_P_2_W_1): Likewise.
	(EVEX_LEN_0F3A19_P_2_W_0): Likewise.
	(EVEX_LEN_0F3A19_P_2_W_1): Likewise.
	(EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
	(EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
	(EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
	(EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
2019-06-05 10:27:28 -07:00
H.J. Lu
63c6fc6cac i386: Check for reserved VEX.vvvv and EVEX.vvvv
If VEX.vvvv and EVEX.vvvv are reserved, they must be all 1s, which are
all 0s in inverted form.  Add check for unused VEX.vvvv and EVEX.vvvv
when disassembling VEX and EVEX instructions.

gas/

	PR binutils/24626
	* testsuite/gas/i386/disassem.s: Add tests for reserved VEX.vvvv
	and EVEX.vvvv.
	* testsuite/gas/i386/x86-64-disassem.s: Likewise.
	* testsuite/gas/i386/disassem.d: Updated.
	* testsuite/gas/i386/x86-64-disassem.d: Likewise.

opcodes/

	PR binutils/24626
	* i386-dis.c (print_insn): Check for unused VEX.vvvv and
	EVEX.vvvv when disassembling VEX and EVEX instructions.
	(OP_VEX): Set vex.register_specifier to 0 after readding
	vex.register_specifier.
	(OP_Vex_2src_1): Likewise.
	(OP_Vex_2src_2): Likewise.
	(OP_LWP_E): Likewise.
	(OP_EX_Vex): Don't check vex.register_specifier.
	(OP_XMM_Vex): Likewise.
2019-06-04 12:45:33 -07:00
H.J. Lu
9186c494a3 Enable Intel AVX512_VP2INTERSECT insn
This patch enables support for VP2INTERSECT in binutils.  Please refer to

https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

for VP2INTERSECT details.

Make check-gas is ok.

gas/

2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
	    Lili Cui  <lili.cui@intel.com>

	* config/tc-i386.c (cpu_arch): Add .avx512_vp2intersect.
	(cpu_noarch): Likewise.
	* doc/c-i386.texi: Document avx512_vp2intersect.
	* testsuite/gas/i386/i386.exp: Run vp2intersect tests.
	* testsuite/gas/i386/vp2intersect-intel.d: New test.
	* testsuite/gas/i386/vp2intersect.d: Likewise.
	* testsuite/gas/i386/vp2intersect.s: Likewise.
	* testsuite/gas/i386/vp2intersect-inval-bcast.l: Likewise.
	* testsuite/gas/i386/vp2intersect-inval-bcast.s: Likewise.
	* testsuite/gas/i386/x86-64-vp2intersect-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-vp2intersect.d: Likewise.
	* testsuite/gas/i386/x86-64-vp2intersect.s: Likewise.
	* testsuite/gas/i386/x86-64-vp2intersect-inval-bcast.l: Likewise.
	* testsuite/gas/i386/x86-64-vp2intersect-inval-bcast.s: Likewise.

opcodes/

2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
	    Lili Cui  <lili.cui@intel.com>

	* i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
	* i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
	instructions.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
	CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
	(cpu_flags): Add CpuAVX512_VP2INTERSECT.
	* i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
	(i386_cpu_flags): Add cpuavx512_vp2intersect.
	* i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
2019-06-04 08:58:31 -07:00
H.J. Lu
5d79adc4b2 Add support for Intel ENQCMD[S] instructions
This patch enables support for ENQCMD[S] in binutils.  Please refer to

https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

for ENQCMD[S] details.

Make check-gas is ok.

gas/ChangeLog:

2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
	    Lili Cui  <lili.cui@intel.com>

	* doc/c-i386.texi: Document enqcmd.
	* testsuite/gas/i386/enqcmd-intel.d: New file.
	* testsuite/gas/i386/enqcmd-inval.l: Likewise.
	* testsuite/gas/i386/enqcmd-inval.s: Likewise.
	* testsuite/gas/i386/enqcmd.d: Likewise.
	* testsuite/gas/i386/enqcmd.s: Likewise.
	* testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
	* testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
	* testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
	* testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
	* testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
	enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
	and x86-64-enqcmd.

opcodes/ChangeLog:

2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
	    Lili Cui  <lili.cui@intel.com>

	* i386-dis.c (enum): Add MOD_0F38F8_PREFIX_1 and
	MOD_0F38F8_PREFIX_3.
	(prefix_table): New instructions (see prefix above).
	(mod_table): New instructions (see prefix above).
	* i386-gen.c (cpu_flag_init): Add entries for enqcmd.
	(cpu_flags): Add a bitfield for enqmcd.
	* i386-init.h: Regenerated.
	* i386-opc.h (enum): Add CpuENQCMD.
	(i386_cpu_flags): Add a bitfield for cpuenqcmd.
	* i386-opc.tbl: Add enqcmd and enqcmds instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Regenerated.
2019-06-04 08:50:46 -07:00
Alan Hayward
a9d96ab97e Remove an unnecessary set of parentheses in the arm-dis.c source file.
* arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
2019-06-04 14:25:08 +01:00
Alan Modra
4f6d070adb Don't waste space in prefix_opcd_indices
* ppc-dis.c (prefix_opcd_indices): Correct size.
2019-06-03 11:50:51 +09:30
H.J. Lu
a2f4b66c9e x86: Add CheckRegSize to AVX512_BF16 instructions with Disp8ShiftVL
For AVX512 instructions with Disp8ShiftVL and Broadcast, we may need to
add CheckRegSize to check if broadcast matches the destination register
size.

gas/

	PR gas/24625
	* testsuite/gas/i386/inval-avx512f.s: Add tests for AVX512_BF16
	instructions with invalid broadcast.
	* testsuite/gas/i386/x86-64-inval-avx512f.s: Likewise.
	* testsuite/gas/i386/inval-avx512f.l: Updated.
	* testsuite/gas/i386/x86-64-inval-avx512f.l: Likewise.

opcodes/

	PR gas/24625
	* i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
	Disp8ShiftVL.
	* i386-tbl.h: Regenerated.
2019-05-28 10:05:44 -07:00
Alan Modra
405b5bd86f Regen POTFILES for bpf
bfd/
	* po/SRC-POTFILES.in: Regenerate.
gas/
	* po/POTFILES.in: Regenerate.
ld/
	* po/BLD-POTFILES.in: Regenerate.
opcodes/
	* po/POTFILES.in: Regenerate.
2019-05-24 23:15:07 +09:30