Commit Graph

833 Commits

Author SHA1 Message Date
Richard Sandiford
d50c751e00 [AArch64][SVE 22/32] Add qualifiers for merging and zeroing predication
This patch adds qualifiers to represent /z and /m suffixes on
predicate registers.

include/
	* opcode/aarch64.h (AARCH64_OPND_QLF_P_Z): New aarch64_opnd_qualifier.
	(AARCH64_OPND_QLF_P_M): Likewise.

opcodes/
	* aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
	AARCH64_OPND_QLF_P_[ZM].
	(aarch64_print_operand): Print /z and /m where appropriate.

gas/
	* config/tc-aarch64.c (vector_el_type): Add NT_zero and NT_merge.
	(parse_vector_type_for_operand): Assert that the skipped character
	is a '.'.
	(parse_predication_for_operand): New function.
	(parse_typed_reg): Parse /z and /m suffixes for predicate registers.
	(vectype_to_qualifier): Handle NT_zero and NT_merge.
2016-09-21 16:54:30 +01:00
Richard Sandiford
f11ad6bc0f [AArch64][SVE 21/32] Add Zn and Pn registers
This patch adds the Zn and Pn registers, and associated fields and
operands.

include/
	* opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New
	aarch64_operand_class.
	(AARCH64_OPND_CLASS_PRED_REG): Likewise.
	(AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5)
	(AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16)
	(AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt)
	(AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd)
	(AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn)
	(AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN)
	(AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds.

opcodes/
	* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
	* aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
	(FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
	(FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
	(FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
	* aarch64-opc.c (fields): Add corresponding entries here.
	(operand_general_constraint_met_p): Check that SVE register lists
	have the correct length.  Check the ranges of SVE index registers.
	Check for cases where p8-p15 are used in 3-bit predicate fields.
	(aarch64_print_operand): Handle the new SVE operands.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
	* aarch64-asm.c (aarch64_ins_sve_index): New function.
	(aarch64_ins_sve_reglist): Likewise.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
	* aarch64-dis.c (aarch64_ext_sve_index): New function.
	(aarch64_ext_sve_reglist): Likewise.
	* aarch64-dis-2.c: Regenerate.

gas/
	* config/tc-aarch64.c (NTA_HASVARWIDTH): New macro.
	(AARCH64_REG_TYPES): Add ZN and PN.
	(get_reg_expected_msg): Handle them.
	(parse_vector_type_for_operand): Add a reg_type parameter.
	Skip the width for Zn and Pn registers.
	(parse_typed_reg): Extend vector handling to Zn and Pn.  Update the
	call to parse_vector_type_for_operand.  Set HASVARTYPE for Zn and Pn,
	expecting the width to be 0.
	(parse_vector_reg_list): Restrict error about [BHSD]nn operands to
	REG_TYPE_VN.
	(vectype_to_qualifier): Use S_[BHSD] qualifiers for NTA_HASVARWIDTH.
	(parse_operands): Handle the new Zn and Pn operands.
	(REGSET16): New macro, split out from...
	(REGSET31): ...here.
	(reg_names): Add Zn and Pn entries.
2016-09-21 16:53:54 +01:00
Richard Sandiford
0c608d6b62 [AArch64][SVE 20/32] Add support for tied operands
SVE has some instructions in which the same register appears twice
in the assembly string, once as an input and once as an output.
This patch adds a general mechanism for that.

The patch needs to add new information to the instruction entries.
One option would have been to extend the flags field of the opcode
to 64 bits (since we already rely on 64-bit integers being available
on the host).  However, the *_INSN macros mean that it's easy to add
new information as top-level fields without affecting the existing
table entries too much.  Going for that option seemed to give slightly
neater code.

include/
	* opcode/aarch64.h (aarch64_opcode): Add a tied_operand field.
	(AARCH64_OPDE_UNTIED_OPERAND): New aarch64_operand_error_kind.

opcodes/
	* aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
	(_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
	(V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
	* aarch64-opc.c (aarch64_match_operands_constraint): Check for
	tied operands.

gas/
	* config/tc-aarch64.c (output_operand_error_record): Handle
	AARCH64_OPDE_UNTIED_OPERAND.
2016-09-21 16:52:30 +01:00
Richard Sandiford
4989adac84 [AArch64][SVE 13/32] Add an F_STRICT flag
SVE predicate operands can appear in three forms:

1. unsuffixed: "Pn"
2. with a predication type: "Pn/[ZM]"
3. with a size suffix: "Pn.[BHSD]"

No variation is allowed: unsuffixed operands cannot have a (redundant)
suffix, and the suffixes can never be dropped.  Unsuffixed Pn are used
in LDR and STR, but they are also used for Pg operands in cases where
the result is scalar and where there is therefore no choice to be made
between "merging" and "zeroing".  This means that some Pg operands have
suffixes and others don't.

It would be possible to use context-sensitive parsing to handle
this difference.  The tc-aarch64.c code would then raise an error
if the wrong kind of suffix is used for a particular instruction.

However, we get much more user-friendly error messages if we parse
all three forms for all SVE instructions and record the suffix as a
qualifier.  The normal qualifier matching code can then report cases
where the wrong kind of suffix is used.  This is a slight extension
of existing usage, which really only checks for the wrong choice of
suffix within a particular kind of suffix.

The only catch is a that a "NIL" entry in the qualifier list
specifically means "no suffix should be present" (case 1 above).
NIL isn't a wildcard here.  It also means that an instruction that
requires all-NIL qualifiers can fail to match (because a suffix was
supplied when it shouldn't have been); this requires a slight change
to find_best_match.

This patch adds an F_STRICT flag to select this behaviour.
The flag will be set for all SVE instructions.  The behaviour
for other instructions doesn't change.

include/
	* opcode/aarch64.h (F_STRICT): New flag.

opcodes/
	* aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.

gas/
	* config/tc-aarch64.c (find_best_match): Simplify, allowing an
	instruction with all-NIL qualifiers to fail to match.
2016-09-21 16:51:00 +01:00
Richard Earnshaw
27e5a27096 [arm] Automatically enable CRC instructions on supported ARMv8-A CPUs.
2016-09-07  Richard Earnshaw  <rearnsha@arm.com>

	* opcode/arm.h (ARM_ARCH_V8A_CRC): New architecture.

2016-09-07  Richard Earnshaw  <rearnsha@arm.com>

	* config/tc-arm.c ((arm_cpus): Use ARM_ARCH_V8A_CRC for all
	ARMv8-A CPUs except xgene1.
2016-09-07 17:14:54 +01:00
Cupertino Miranda
a87aa054a6 Fixes to legacy ARC relocations.
Added support for ARC_SDA_12 reloc.
Fixed ARC_N32_ME.
Added ME (middle-endian) to ARC_SDA_12 reloc.

bfd/ChangeLog:

Cupertino Miranda  <cmiranda@synopsys.com>
	* reloc.c: Fixed type in ARC_SECTOFF relocations. Added ARC_SDA_12
	relocation.
	* bfd-in2.h: Regenerated from the previous changes.
	* libbfd.h: Regenerated from the previous changes.

include/ChangeLog:

Cupertino Miranda  <cmiranda@synopsys.com>
	* elf/arc-reloc.def: Fixed relocation formula for N*, SDA, SDA_12,
	SDA_16_LD*, S13_PCREL, N32_ME, SECTOFF_* relocations.
	* opcode/arc-func.h (replace_disp12s): Added. Used for SDA_12 relocation.
2016-08-26 12:09:17 +02:00
Thomas Preud'homme
4ba2ef8fbe 2016-08-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
	* elf32-arm.c (CMSE_PREFIX): Define macro.
	(elf32_arm_stub_cmse_branch_thumb_only): Define stub sequence.
	(cmse_branch_thumb_only): Declare stub.
	(struct elf32_arm_link_hash_table): Define cmse_stub_sec field.
	(elf32_arm_get_plt_info): Add globals parameter.  Use it to return
	FALSE if there is no PLT.
	(arm_type_of_stub): Adapt to new elf32_arm_get_plt_info signature.
	(elf32_arm_final_link_relocate): Likewise.
	(elf32_arm_gc_sweep_hook): Likewise.
	(elf32_arm_gc_mark_extra_sections): Mark sections holding ARMv8-M
	secure entry functions.
	(arm_stub_is_thumb): Add case for arm_stub_cmse_branch_thumb_only.
	(arm_dedicated_stub_output_section_required): Change to a switch case
	and add a case for arm_stub_cmse_branch_thumb_only.
	(arm_dedicated_stub_output_section_required_alignment): Likewise.
	(arm_stub_dedicated_output_section_name): Likewise.
	(arm_stub_dedicated_input_section_ptr): Likewise and remove
	ATTRIBUTE_UNUSED for htab parameter.
	(arm_stub_required_alignment): Likewise.
	(arm_stub_sym_claimed): Likewise.
	(arm_dedicated_stub_section_padding): Likewise.
	(cmse_scan): New function.
	(elf32_arm_size_stubs): Call cmse_scan for ARM M profile targets.
	Set stub_changed to TRUE if such veneers were created.
	(elf32_arm_swap_symbol_in): Add detection code for CMSE special
	symbols.

include/
	* arm.h (ARM_GET_SYM_CMSE_SPCL): Define macro.
	(ARM_SET_SYM_CMSE_SPCL): Likewise.

ld/
	* ld.texinfo (Placement of SG veneers): New concept entry.
	* testsuite/ld-arm/arm-elf.exp
	(Secure gateway veneers: no .gnu.sgstubs section): New test.
	(Secure gateway veneers: wrong entry functions): Likewise.
	(Secure gateway veneers (ARMv8-M Baseline)): Likewise.
	(Secure gateway veneers (ARMv8-M Mainline)): Likewise.
	* testsuite/ld-arm/cmse-veneers.s: New file.
	* testsuite/ld-arm/cmse-veneers.d: Likewise.
	* testsuite/ld-arm/cmse-veneers.rd: Likewise.
	* testsuite/ld-arm/cmse-veneers.sd: Likewise.
	* testsuite/ld-arm/cmse-veneers-no-gnu_sgstubs.out: Likewise.
	* testsuite/ld-arm/cmse-veneers-wrong-entryfct.out: Likewise.
2016-08-04 15:36:52 +01:00
Nick Clifton
fa3fcee7b8 Synchronize libiberty sources with FSF GCC mainline version.
include	* libiberty.h (MAX_ALLOCA_SIZE): New macro.

libiberty * make-relative-prefix.c (make_relative_prefix_1): Fall back to
	malloc if alloca argument is greater than MAX_ALLOCA_SIZE.

	* cp-demangle.c (cplus_demangle_operators): Add f[lrLR].
	(d_expression_1): Handle them.
	(d_maybe_print_fold_expression): New.
	(d_print_comp_inner): Use it.
	(d_index_template_argument): Handle negative index.

	* cp-demangle.c (cplus_demangle_operators): Add sP and sZ.
	(d_print_comp_inner): Handle them.
	(d_template_args_1): Split out from d_template_args.
	(d_args_length): New.

	PR c++/70926
	* cplus-dem.c: Handle large values and overflow when demangling
	length variables.
	(demangle_template_value_parm): Read only until end of mangled string.
	(do_hpacc_template_literal): Likewise.
	(do_type): Handle overflow when demangling array indices.

	* cp-demangle.c (cplus_demangle_print_callback): Avoid zero-length
	  VLAs.

	PR c++/70498
	* cp-demangle.c (d_expression_1): Formatting fix.

	* cplus-dem.c (enum type_kind_t): Add tk_rvalue_reference
	constant.
	(demangle_template_value_parm): Handle tk_rvalue_reference
	type kind.
	(do_type): Support 'O' type id (rvalue references).

	* testsuite/demangle-expected: Add tests.

	PR c++/70498
	* cp-demangle.c: Parse numbers as integer instead of long to avoid
	overflow after sanity checks. Include <limits.h> if available.
	(INT_MAX): Define if necessary.
	(d_make_template_param): Takes integer argument instead of long.
	(d_make_function_param): Likewise.
	(d_append_num): Likewise.
	(d_identifier): Likewise.
	(d_number): Parse as and return integer.
	(d_compact_number): Handle overflow.
	(d_source_name): Change variable type to integer for parsed number.
	(d_java_resource): Likewise.
	(d_special_name): Likewise.
	(d_discriminator): Likewise.
	(d_unnamed_type): Likewise.
	* testsuite/demangle-expected: Add regression test cases.

	* configure: Remove SH5 support.

	PR c++/69687
	* cplus-dem.c: Include <limits.h> if available.
	(INT_MAX): Define if necessary.
	(remember_type, remember_Ktype, register_Btype, string_need):
	Abort if we detect cases where we the size of the allocation would
	overflow.

	PR c++/70492
	* cplus-dem.c (gnu_special): Handle case where consume_count returns
	-1.

	PR c++/67394
	PR c++/70481
	* cplus-dem.c (squangle_mop_up): Zero bsize/ksize after freeing
	btypevec/ktypevec.
	* testsuite/demangle-expected: Add coverage tests.
2016-08-02 13:26:28 +01:00
Andrew Jenner
dfdaec14b0 Fix some PowerPC VLE BFD issues and add some PowerPC VLE instructions.
bfd/
        * elf32-ppc.c (is_branch_reloc): Recognise VLE branch relocations.
        (ppc_elf_howto_raw): Fix dst_mask of R_PPC_VLE_REL15.
        (ppc_elf_vle_split16): Clear field before inserting.

        opcodes/
        * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
        'e_cmplwi' to 'e_cmpli' instead.
        (OPVUPRT, OPVUPRT_MASK): Define.
        (powerpc_opcodes): Add E200Z4 insns.
        (vle_opcodes): Add context save/restore insns.

        include/
        * opcode/ppc.h (PPC_OPCODE_E200Z4): New define.
2016-08-01 09:42:31 -07:00
Graham Markall
db18dbabad Begin implementing ARC NPS-400 Accelerator instructions
opcodes * arc-nps400-tbl.h: Change block comments to GNU format.
        * arc-dis.c: Add new globals addrtypenames,
        addrtypenames_max, and addtypeunknown.
        (get_addrtype): New function.
        (print_insn_arc): Print colons and address types when
        required.
        * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
        define insert and extract functions for all address types.
        (arc_operands): Add operands for colon and all address
        types.
        * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
        * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
        insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
        * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
        * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
        insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.

include * opcode/arc.h: Add ARC_OPERAND_ADDRTYPE,
        ARC_OPERAND_COLON. Add the arc_nps_address_type enum and
        ARC_NUM_ADDRTYPES.
        * opcode/arc.h: Add BMU to insn_class_t enum.
        * opcode/arc.h: Add PMU to insn_class_t enum.

gas     * config/tc-arc.c: Add new global arc_addrtype_hash.
        Define O_colon and O_addrtype.
        (debug_exp): Add O_colon and O_addrtype.
        (tokenize_arguments): Handle colon and address type
        tokens.
        (declare_addrtype): New function.
        (md_begin): Initialise arc_addrtype_hash.
        (arc_parse_name): Add lookup of address types.
	(assemble_insn): Handle colons and address types by
        ignoring them.
        * testsuite/gas/arc/nps400-8.s: New file.
        * testsuite/gas/arc/nps400-8.d: New file.
        * testsuite/gas/arc/nps400-8.s: Add PMU instruction tests.
        * testsuite/gas/arc/nps400-8.d: Add expected PMU
        instruction output.
2016-07-27 15:57:18 +01:00
Claudiu Zissulescu
37fd5ef3ec Add support to the ARC disassembler for selecting instruction classes.
gas	* testsuite/gas/arc/dsp.d: New file.
	* testsuite/gas/arc/dsp.s: Likewise.
	* testsuite/gas/arc/fpu.d: Likewise.
	* testsuite/gas/arc/fpu.s: Likewise.
	* testsuite/gas/arc/ext2op.d: Add specific disassembler option.
	* testsuite/gas/arc/ext3op.d: Likewise.
	* testsuite/gas/arc/tdpfp.d: Likewise.
	* testsuite/gas/arc/tfpuda.d: Likewise.

opcodes	* arc-dis.c (skipclass): New structure.
	(decodelist): New variable.
	(is_compatible_p): New function.
	(new_element): Likewise.
	(skip_class_p): Likewise.
	(find_format_from_table): Use skip_class_p function.
	(find_format): Decode first the extension instructions.
	(print_insn_arc): Select either ARCEM or ARCHS based on elf
	e_flags.
	(parse_option): New function.
	(parse_disassembler_options): Likewise.
	(print_arc_disassembler_options): Likewise.
	(print_insn_arc): Use parse_disassembler_options function.  Proper
	select ARCv2 cpu variant.
	* disassemble.c (disassembler_usage): Add ARC disassembler
	options.

binutils* doc/binutils.texi (objdump): Add ARC disassembler options.
	* testsuite/binutils-all/arc/dsp.s: New file.
	* testsuite/binutils-all/arc/objdump.exp: Likewise.

include	* dis-asm.h: Declare print_arc_disassembler_options.
2016-07-20 17:08:07 +01:00
Thomas Preud'homme
7635954182 Add support for creating ELF import libraries
2016-07-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>

bfd/
	* elf-bfd.h (elf_backend_filter_implib_symbols): Declare backend hook.
	(_bfd_elf_filter_global_symbols): Declare.
	* elf.c (_bfd_elf_filter_global_symbols): New function.
	* elflink.c (elf_filter_global_symbols): Likewise.
	(elf_output_implib): Likewise.
	(bfd_elf_final_link): Call above function, failing if it does.
	* elfxx-target.h (elf_backend_filter_implib_symbols): Define macro and
	default it to NULL.
	(elf_backend_copy_indirect_symbol): Fix spacing.
	(elf_backend_hide_symbol): Likewise.
	(elfNN_bed): Initialize elf_backend_filter_implib_symbols backend hook.

include/
	* bfdlink.h (struct bfd_link_info): Declare new ldscript_def and
	out_implib_bfd fields.

2016-07-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
	    Nick Clifton  <nickc@redhat.com>

ld/
	* emultempl/elf32.em (gld${EMULATION_NAME}_after_open): Open import
	library file for writing and initialize implib_bfd field of link_info
	structure.
	* emultempl/pe.em (pe_implib_filename): Remove variable declaration.
	(OPTION_IMPLIB_FILENAME): Remove macro definition.
	(gld${EMULATION_NAME}_add_options): Remove --out-implib option.
	(gld_${EMULATION_NAME}_list_options): Likewise.
	(gld${EMULATION_NAME}_handle_option): Likewise.
	(gld_${EMULATION_NAME}_finish): Use command_line.out_implib_filename
	instead of pe_implib_filename.
	* emultempl/pep.em (pep_implib_filename): Remove variable declaration.
	(OPTION_IMPLIB_FILENAME): Remove enumerator.
	(gld${EMULATION_NAME}_add_options): Remove --out-implib option.
	(gld_${EMULATION_NAME}_list_options): Likewise.
	(gld${EMULATION_NAME}_handle_option): Likewise.
	(gld_${EMULATION_NAME}_finish): Use command_line.out_implib_filename
	instead of pep_implib_filename.
	* ld.h (args_type): Declare new out_implib_filename field.
	* ld.texinfo (--out-implib): Move documentation to arch-independent
	part and rephrase to apply to ELF targets.
	* ldexp.c (exp_fold_tree_1): Set ldscript_def field to 1 for symbols
	defined in linker scripts.
	* ldlex.h (enum option_values): Declare new OPTION_OUT_IMPLIB
	enumerator.
	* lexsup.c (ld_options): Add entry for new --out-implib switch.
	(parse_args): Handle OPTION_OUT_IMPLIB case.
	* testsuite/ld-elf/elf.exp (Generate empty import library): New test.
	(Generate import library): Likewise.
	* testsuite/ld-elf/implib.s: Likewise.
	* testsuite/ld-elf/implib.rd: New file.
	* testsuite/ld-elf/empty-implib.out: Likewise
2016-07-15 17:50:48 +01:00
Claudiu Zissulescu
fa1c017017 [ARC] Fix/improve small data support.
The R_ARC_SDA32 is wrongly described as a ME relocation, fix it.  Offset the
__SDATA_BEGIN__ to take advantage of the signed 9-bit field of the
load/store instructions.

include/
2016-07-08  Claudiu Zissulescu  <claziss@synopsys.com>

	* elf/arc-reloc.def (ARC_SDA32): Don't use ME transformation.

ld/
2016-07-08  Claudiu Zissulescu  <claziss@synopsys.com>

	* emulparams/arcelf.sh (SDATA_START_SYMBOLS): Add offset.
	* testsuite/ld-arc/sda-relocs.dd: New file.
	* testsuite/ld-arc/sda-relocs.ld: Likewise.
	* testsuite/ld-arc/sda-relocs.rd: Likewise.
	* testsuite/ld-arc/sda-relocs.s: Likewise.
	* testsuite/ld-arc/arc.exp: Add SDA tests.
2016-07-14 10:08:57 +02:00
Andre Vieria
f0728ee368 [ARM] Change noread to purecode.
bfd/ChangeLog
2016-07-05  Andre Vieria  <andre.simoesdiasvieira@arm.com>

        * bfd-in2.h (SEC_ELF_NOREAD): Rename to ...
          (SEC_ELF_PURECODE): ... this.
        * elf32-arm.c (elf32_arm_post_process_headers): Rename SEC_ELF_NOREAD
          to SEC_ELF_NOREAD.
          (elf32_arm_fake_sections): Likewise.
          (elf_32_arm_section_flags): Likewise.
          (elf_32_arm_lookup_section_flags): Likewise.
        * section.c (SEC_ELF_NOREAD): Rename to ...
          (SEC_ELF_PURECODE): ... this.

binutils/ChangeLog
2016-07-05  Andre Vieria  <andre.simoesdiasvieira@arm.com>

        * objdump.c (dump_section_header): Rename SEC_ELF_NOREAD
          to SEC_ELF_NOREAD.
        * readelf.c (get_elf_section_flags): Rename ARM_NOREAD to
          ARM_PURECODE and SHF_ARM_NOREAD to SHF_ARM_PURECODE.
          (process_section_headers): Rename noread to purecode.

        * section.c (SEC_ELF_NOREAD): Rename to ...
          (SEC_ELF_PURECODE): ... this.

include/ChangeLog
2016-07-05  Andre Vieria  <andre.simoesdiasvieira@arm.com>

        * elf/arm.h (SHF_ARM_NOREAD): Rename to ...
          (SHF_ARM_PURECODE): ... this.

ld/ChangeLog
2016-07-05  Andre Vieria  <andre.simoesdiasvieira@arm.com>

        * testsuite/ld-arm/arm_noread.ld: Renamed to ...
          testsuite/ld-arm/arm_purecode.ld: ... this, and replaced
          all noread's by purecode.
2016-07-05 11:28:46 +01:00
Szabolcs Nagy
93d8990cba [AArch64] Fix +nofp16 handling
Feature flag handling was not perfect, +nofp16 disabled fp
instructions too.

New feature flag macros were added to check features with multiple
bits set (matters for FP_F16 and SIMD_F16 opcode feature tests).
The unused AARCH64_OPCODE_HAS_FEATURE was removed, all checks should
use one of the AARCH64_CPU_HAS_* macros.  AARCH64_CPU_HAS_FEATURE
now checks all feature bits.

The aarch64_features table now contains the dependencies as
a separate field (so when the feature is enabled all dependencies
are enabled and when it is disabled everything that depends on it
is disabled).

Note that armv8-a+foo+nofoo is not equivalent to armv8-a if
+foo turns on dependent features that nofoo does not turn off.

gas/
	* config/tc-aarch64.c (struct aarch64_option_cpu_value_table): Add
	require field.
	(aarch64_features): Initialize require fields.
	(aarch64_parse_features): Handle dependencies.
	(aarch64_feature_enable_set, aarch64_feature_disable_set): New.
	(md_assemble): Use AARCH64_CPU_HAS_ALL_FEATURES.
	* testsuite/gas/aarch64/illegal-nofp16.s: New.
	* testsuite/gas/aarch64/illegal-nofp16.l: New.
	* testsuite/gas/aarch64/illegal-nofp16.d: New.

include/
	* opcode/aarch64.h (AARCH64_CPU_HAS_ALL_FEATURES): New.
	(AARCH64_CPU_HAS_ANY_FEATURES): New.
	(AARCH64_CPU_HAS_FEATURE): Define as AARCH64_CPU_HAS_ALL_FEATURES.
	(AARCH64_OPCODE_HAS_FEATURE): Remove.
2016-07-01 16:50:59 +01:00
Matthew Wahab
534dbe460e [ARM][GAS] ARMv8.2 should enable ARMv8.1 NEON instructions.
GAS fails to recognize march=armv8.2-a as a superset of march=armv8.1-a
when assembling NEON instructions. The patch corrects this, making
-march=armv8.2-a -mfpu=neon-fp-armv8 enable the NEON intructions
introduced with ARMv8.1-A.

include/
2016-06-30  Matthew Wahab  <matthew.wahab@arm.com>

	* opcode/arm.h (ARM_ARCH_V8_2a): Add FPU_NEON_EXT_RDMA to the set
	of enabled FPU features.

gas/
2016-06-30  Matthew Wahab  <matthew.wahab@arm.com>

	* testsuite/gas/arm/armv8_2+rdma.d: New.
2016-06-30 10:46:51 +01:00
Trevor Saunders
042c94de56 sparc: make SPARC_OPCODE_ARCH_MAX part of its enum
include/ChangeLog:

2016-06-29  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* opcode/sparc.h (enum sparc_opcode_arch_val): Move
	SPARC_OPCODE_ARCH_MAX into the enum.
2016-06-29 07:24:18 -04:00
Richard Sandiford
dab26bf4e7 [AArch64] Make register indices be full 64-bit values
aarch64_opnd_info used bitfields to hold vector element indices,
but values were stored into those bitfields before their ranges had
been checked.  This meant large invalid indices could be silently
truncated to smaller valid indices.

The two obvious fixes were to do the range checking earlier or use
a full 64-bit field for the index.  I went for the latter for two
reasons:

      - Doing the range checking in operand_general_constraint_met_p
        seems structurally cleaner than doing it while parsing.

      - The bitfields didn't really buy us anything.  The imm field
        of the union is already 128 bits, so we can use a full int64_t
        index without growing the structure.

The patch also adds missing range checks for the elements in a register
list index.

include/
	* opcode/aarch64.h (aarch64_opnd_info): Change index fields to int64_t.

opcodes/
	* aarch64-opc.c (operand_general_constraint_met_p): Check the
	range of ldst_elemlist operands.
	(print_register_list): Use PRIi64 to print the index.
	(aarch64_print_operand): Likewise.

gas/
	* testsuite/gas/aarch64/diagnostic.s,
	testsuite/gas/aarch64/diagnostic.l: Add tests for out-of-range indices.
2016-06-28 09:21:04 +01:00
Maciej W. Rozycki
c9775dde32 MIPS16: Add R_MIPS16_PC16_S1 branch relocation support
For R_MIPS16_PC16_S1 the calculation is `(sign_extend(A) + S - P) >> 1'
and the usual MIPS16 bit shuffling applies to relocated field handling,
as per the encoding of the branch target in the extended form of the
MIPS16 B, BEQZ, BNEZ, BTEQZ and BTNEZ instructions.

	include/
	* elf/mips.h (R_MIPS16_PC16_S1): New relocation.

	bfd/
	* elf32-mips.c (elf_mips16_howto_table_rel): Add
	R_MIPS16_PC16_S1.
	(mips16_reloc_map): Likewise.
	* elf64-mips.c (mips16_elf64_howto_table_rel): Likewise.
	(mips16_elf64_howto_table_rela): Likewise.
	(mips16_reloc_map): Likewise.
	* elfn32-mips.c (elf_mips16_howto_table_rel): Likewise.
	(elf_mips16_howto_table_rela): Likewise.
	(mips16_reloc_map): Likewise.
	* elfxx-mips.c (mips16_branch_reloc_p): New function.
	(mips16_reloc_p): Handle R_MIPS16_PC16_S1.
	(b_reloc_p): Likewise.
	(mips_elf_calculate_relocation): Likewise.
	(_bfd_mips_elf_check_relocs): Likewise.
	* reloc.c (BFD_RELOC_MIPS16_16_PCREL_S1): New relocation.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.

	gas/
	* config/tc-mips.c (mips16_reloc_p): Handle
	BFD_RELOC_MIPS16_16_PCREL_S1.
	(b_reloc_p): Likewise.
	(limited_pcrel_reloc_p): Likewise.
	(md_pcrel_from): Likewise.
	(md_apply_fix): Likewise.
	(tc_gen_reloc): Likewise.
	(md_convert_frag): Likewise.
	(mips_fix_adjustable): Update comment.
	* testsuite/gas/mips/mips16-branch-reloc-2.d: Remove error
	output, add dump patterns.
	* testsuite/gas/mips/mips16-branch-reloc-3.d: Remove error
	output, add dump patterns.
	* testsuite/gas/mips/mips16-branch-addend-2.d: Remove error
	output, add dump patterns.
	* testsuite/gas/mips/mips16-branch-addend-3.d: Remove error
	output, add dump patterns.
	* testsuite/gas/mips/mips16-branch-absolute.d: Remove error
	output, add dump patterns.
	* testsuite/gas/mips/mips16-branch-reloc-2.l: Remove file.
	* testsuite/gas/mips/mips16-branch-reloc-3.l: Remove file.
	* testsuite/gas/mips/mips16-branch-addend-2.l: Remove file.
	* testsuite/gas/mips/mips16-branch-addend-3.l: Remove file.
	* testsuite/gas/mips/mips16-branch-absolute.l: Remove file.
	* testsuite/gas/mips/mips16-branch-addend-2.s: Add padding.
	* testsuite/gas/mips/branch-weak.s: Adjust alignment, avoid
	implicit instruction padding, avoid MIPS16 JR->JRC conversion.
	* testsuite/gas/mips/branch-weak-6.d: New test.
	* testsuite/gas/mips/branch-weak-7.d: New test.
	* testsuite/gas/mips/mips.exp: Run the new tests.

	ld/
	* testsuite/ld-mips-elf/mips16-branch-2.d: New test.
	* testsuite/ld-mips-elf/mips16-branch-3.d: New test.
	* testsuite/ld-mips-elf/mips16-branch-addend-2.d: New test.
	* testsuite/ld-mips-elf/mips16-branch-addend-3.d: New test.
	* testsuite/ld-mips-elf/mips16-branch.s: New test source.
	* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2016-06-28 01:29:56 +01:00
Trevor Saunders
7c2c4aa12f xtensa: prototype xtensa_make_property_section in elf/xtensa.h
There's no reason to have multiple prototypes for the same function.

include/ChangeLog:

2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* elf/xtensa.h (xtensa_make_property_section): New prototype.

gas/ChangeLog:

2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-xtensa.c (xtensa_make_property_section): Remove prototype.

bfd/ChangeLog:

2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* elf32-xtensa.c (xtensa_make_property_section): Remove prototype.
2016-06-25 11:50:33 -04:00
John Baldwin
b00f86d072 Add constants for FreeBSD-specific auxiliary vector entry types.
include/ChangeLog:

	* elf/common.h (AT_FREEBSD_EXECPATH, AT_FREEBSD_CANARY)
	(AT_FREEBSD_CANARYLEN, AT_FREEBSD_OSRELDATE, AT_FREEBSD_NCPUS)
	(AT_FREEBSD_PAGESIZES, AT_FREEBSD_PAGESIZESLEN)
	(AT_FREEBSD_TIMEKEEP, AT_FREEBSD_STACKPROT): Define.
2016-06-24 10:30:45 -07:00
Graham Markall
ce440d638d [ARC] Misc minor edits/fixes
The code supporting -mspfp, -mdpfp, and -mfpuda options are in
sections of code that are commented as being for backward
compatibility only, and having no effect. However, they do have an
effect, enabling the SPX, DPX, and DPA instruction subclasses
respectively. This commit moves the code supporting these options
away from the comments indicating that they are dummy options, and
also fixes a small issue where -mnps400 had the additional effect
of enabling SPX instructions.

A couple of other minor edits (that make no functional change) are
also included.

gas/ChangeLog:

        * config/tc-arc.c (options, md_longopts, md_parse_option):
        Move -mspfp, -mdpfp and -mfpuda out of the sections for
        dummy options. Correct erroneous enabling of SPFP
        instructions when using -mnps400.

include/ChangeLog:

        * opcode/arc.h: Make insn_class_t alphabetical again.

opcodes/ChangeLog:

        * arc-opc.c: Correct description of availability of NPS400
        features.
2016-06-23 09:57:42 +01:00
Trevor Saunders
6b4778968b addmore extern C
opcodes/ChangeLog:

2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* arc-ext.h: Wrap in extern C.

include/ChangeLog:

2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* elf/dlx.h: Wrap in extern C.
	* elf/xtensa.h: Likewise.
	* opcode/arc.h: Likewise.
2016-06-22 12:59:58 -04:00
Trevor Saunders
6edaf4d75b tilegx: move TILEGX_NUM_PIPELINE_ENCODINGS to tilegx_pipeline enum
Its closely related to what the encodings are, more than a set of random
constants, so it seems to make sense to put it here.

include/ChangeLog:

2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* opcode/tilegx.h: Move TILEGX_NUM_PIPELINE_ENCODINGS into
	tilegx_pipeline.
2016-06-22 05:14:08 -04:00
Graham Markall
bdd582dbf1 Arc assembler: Convert nps400 from a machine type to an extension.
gas	* config/tc-arc.c (check_cpu_feature, md_parse_option):
	Add nps400 option and feature. Add check for nps400
	feature. Refactor existing checks to check subclass before
	feature enablement.
	(md_show_usage): Document flags for NPS-400 and add some other
	undocumented flags.
	(cpu_type): Remove nps400 CPU type entry
	(check_zol): Remove bfd_mach_arc_nps400 case.
	(md_show_usage): Add help on -mcpu=nps400.
	(cpu_types): Add entry for nps400 as arc700 plus nps400 extension
	set.
	* doc/c-arc.texi: Document the -mnps400, -mspfp, -mdpfp, and
	-fpuda flags.  Document -mcpu=nps400.
	* testsuite/gas/arc/nps-400-0.d: Use -mcpu=arc700 -mnps400. Change
	expected flags to match ARC700 instead of NPS400.
	* testsuite/gas/arc/nps-400-1.d: Use -mcpu=arc700 -mnps400.
	* testsuite/gas/arc/nps-400-2.d: Likewise.
	* testsuite/gas/arc/nps-400-3.d: Likewise.
	* testsuite/gas/arc/nps-400-4.d: Likewise.
	* testsuite/gas/arc/nps-400-5.d: Likewise.
	* testsuite/gas/arc/nps-400-6.d: Likewise.
	* testsuite/gas/arc/nps-400-7.d: Likewise.
	* testsuite/gas/arc/textinsn2op01.s: Change opcode of myinsn to
	avoid clash with cbba instruction.
	* testsuite/gas/arc/textinsn2op01.d: Likewise.
	* testsuite/gas/arc/textinsn3op.d: Likewise.
	* testsuite/gas/arc/textinsn3op.s: Likewise.
	* testsuite/gas/arc/nps-400-0.d: Test using NPS-400 using
	-mcpu=nps400 as an alternative to -mcpu=arc700 -mnps400 flags.

binutils* readelf.c (decode_ARC_machine_flags): Remove E_ARC_MACH_NPS400
	case.

ld	* testsuite/ld-arc/nps-1a.d: Use -mcpu=arc700 -mnps400.
	* testsuite/ld-arc/nps-1b.d: Likewise.

include	* opcode/arc.h: Add nps400 extension and instruction
	subclass.
	Remove ARC_OPCODE_NPS400
	* elf/arc.h: Remove E_ARC_MACH_NPS400

opcodes	* arc-dis.c (arc_insn_length): Add comment on instruction length.
	Use same method for determining	instruction length on ARC700 and
	NPS-400.
	(arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
	* arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
	with the NPS400 subclass.
	* arc-opc.c: Likewise.

bfd	* archures.c: Remove bfd_mach_arc_nps400.
	* bfd-in2.h: Likewise.
	* cpu-arc.c (arch_info_struct): Likewise.
	* elf32-arc.c (arc_elf_object_p, arc_elf_final_write_processing):
	Likewise.
2016-06-21 14:03:08 +01:00
Jose E. Marchesi
4f26fb3a1b bfd,opcodes: sparc: new opcode v9{c,d,e,v,m} architectures and bfd machine numbers.
This patch adds support for the opcode architectures
SPARC_OPCODE_ARCH_V9{C,D,E,V,M} and its associated BFD machine numbers
bfd_mach_sparc_v9{c,d,e,v,m} and bfd_mach_sparc_v8plus{c,d,e,v,m}.

Note that for arches up to v9b (UltraSPARC III), the detection of the
BFD machine type was based on the bits in the e_machine field of the ELF
header.  However, there are no more available bits in that field, so
this patch takes the approach of using the hardware capabilities stored
in the object attributes HWCAPS/HWCAPS2 in order to characterize the
machine the object was built for.

bfd/ChangeLog:

2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* archures.c (bfd_mach_sparc_v8plusc): Define.
	(bfd_mach_sparc_v9c): Likewise.
	(bfd_mach_sparc_v8plusd): Likewise.
	(bfd_mach_sparc_v9d): Likewise.
	(bfd_mach_sparc_v8pluse): Likewise.
	(bfd_mach_sparc_v9e): Likewise.
	(bfd_mach_sparc_v8plusv): Likewise
	(bfd_mach_sparc_v9v): Likewise.
	(bfd_mach_sparc_v8plusm): Likewise.
	(bfd_mach_sparc_v9m): Likewise.
	(bfd_mach_sparc_v9_p): Adapt to v8plusm and v9m.
	(bfd_mach_sparc_64bit_p): Likewise.
	* bfd-in2.h: Regenerate.
	* cpu-sparc.c (arch_info_struct): Add entries for
	bfd_mach_sparc_v8plus{c,d,e,v,m} and bfd_mach_sparc_v9{c,d,e,v,m}.
	* aoutx.h (machine_type): Handle bfd_mach_sparc_v8plus{c,d,e,v,m}
	and bfd_mach_sparc_v9{c,d,e,v,m}.
	* elf32-sparc.c (elf32_sparc_final_write_processing): Likewise.
	* elfxx-sparc.c (_bfd_sparc_elf_object_p): Likewise.

include/ChangeLog:

2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* opcode/sparc.h (enum sparc_opcode_arch_val): Add
	SPARC_OPCODE_ARCH_V9C, SPARC_OPCODE_ARCH_V9D,
	SPARC_OPCODE_ARCH_V9E, SPARC_OPCODE_ARCH_V9V and
	SPARC_OPCODE_ARCH_V9M.

opcodes/ChangeLog:

2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
	(compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
	bfd_mach_sparc_v9{c,d,e,v,m}.
	* sparc-opc.c (MASK_V9C): Define.
	(MASK_V9D): Likewise.
	(MASK_V9E): Likewise.
	(MASK_V9V): Likewise.
	(MASK_V9M): Likewise.
	(v6): Add MASK_V9{C,D,E,V,M}.
	(v6notlet): Likewise.
	(v7): Likewise.
	(v8): Likewise.
	(v9): Likewise.
	(v9andleon): Likewise.
	(v9a): Likewise.
	(v9b): Likewise.
	(v9c): Define.
	(v9d): Likewise.
	(v9e): Likewise.
	(v9v): Likewise.
	(v9m): Likewise.
	(sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
2016-06-17 02:12:48 -07:00
John Baldwin
99a54ef6f7 Change the size field of MSP430_Opcode_Decoded to a plain integer.
The size field was defined as an instance of an enum, but existing code
treats the size field as a plain integer containing a bit count.

include/ChangeLog:

	* opcode/msp430-decode.h (MSP430_Size): Remove.
	(Msp430_Opcode_Decoded): Change type of size to int.
2016-06-14 11:41:34 -07:00
Alan Modra
0eaf2e1b58 sparc-coff writing uninitialized memory
sparc-coff has a 20 byte symbol entry with an extra field, but neglects
to initialize the field.  Fix that.

	* coff/sparc.h (COFF_ADJUST_SYM_OUT_POST): Define.
2016-06-11 17:25:35 +09:30
Jose E. Marchesi
337c570c5f sparc: add missing comment about hyperprivileged register operands
include/ChangeLog:

2016-06-08  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* opcode/sparc.h: Add missing documentation for hyperprivileged
	registers in rd (%) and rs1 ($).
2016-06-09 04:37:07 -07:00
Alan Modra
14b57c7c6a PowerPC VLE
VLE is an encoding, not a particular processor architecture, so it
isn't really proper to select insns based on PPC_OPCODE_VLE.  For
example
{"evaddw",  VX (4, 512), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"vaddubs", VX (4, 512), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
shows two insns that have the same encoding, both available with VLE.
Enabling both with VLE means we can't disassemble the second variant
even if -Maltivec is given rather than -Mspe.  Also, we don't check
user assembly against the processor type as well as we could.

Another problem is that when using the VLE encoding, insns from the
main ppc opcode table are not available, except those using opcode 4
and 31.  Correcting this revealed two errors in the ld testsuite,
use of "nop" and "rfmci" when -mvle.

This patch fixes those problems in the opcode table, and removes
PPCNONE.  I find a plain 0 distracts less from other values.

In addition, I've implemented code to recognize some machine values
from the apuinfo note present in ppc32 objects.  It's not a complete
disambiguation since we're lacking info to detect newer chips, but
what we have should help with disassembly.

include/
	* elf/ppc.h (APUINFO_SECTION_NAME, APUINFO_LABEL, PPC_APUINFO_ISEL,
	PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK,
	PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK,
	PPC_APUINFO_VLE: Define.
opcodes/
	* ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
	cpu for "vle" to e500.
	* ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
	(NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
	(PPCNONE): Delete, substitute throughout.
	(powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
	except for major opcode 4 and 31.
	(vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
bfd/
	* cpu-powerpc.c (powerpc_compatible): Allow bfd_mach_ppc_vle entry
	to match other 32-bit archs.
	* elf32-ppc.c (_bfd_elf_ppc_set_arch): New function.
	(ppc_elf_object_p): Call it.
	(ppc_elf_special_sections): Use APUINFO_SECTION_NAME.  Fix
	overlong line.
	(APUINFO_SECTION_NAME, APUINFO_LABEL): Don't define here.
	* elf64-ppc.c (ppc64_elf_object_p): Call _bfd_elf_ppc_set_arch.
	* bfd-in.h (_bfd_elf_ppc_at_tls_transform,
	_bfd_elf_ppc_at_tprel_transform): Move to..
	* elf-bfd.h: ..here.
	(_bfd_elf_ppc_set_arch): Declare.
	* bfd-in2.h: Regenerate.
gas/
	* config/tc-ppc.c (PPC_APUINFO_ISEL, PPC_APUINFO_PMR,
	PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK, PPC_APUINFO_SPE,
	PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK, PPC_APUINFO_VLE): Don't define.
	(ppc_setup_opcodes): Check vle disables powerpc_opcodes overridden
	by vle_opcodes, and that vle flag doesn't enable opcodes.  Don't
	add vle_opcodes twice.
	(ppc_cleanup): Use APUINFO_SECTION_NAME and APUINFO_LABEL.
ld/
	* testsuite/ld-powerpc/apuinfo1.s: Delete nop.
	* testsuite/ld-powerpc/apuinfo-vle2.s: New.
	* testsuite/ld-powerpc/powerpc.exp: Use apuinfo-vle2.s.
2016-06-07 22:04:38 +09:30
Matthew Wahab
4d1464f294 [ARM] Add command line option for RAS extension.
This patch adds the architecture extension "+ras" to enable RAS
support. It is enabled by default for -march=armv8.2-a and available but
disabled by default for armv8-a and armv8.1-a.

gas/
	* config/tc-arm.c (arm_ext_v8_2): Rename to arm_ext_ras.
	(arm_ext_ras): Renamed from arm_ext_v8_2.
	(insns): Update for arm_ext_v8_2 renaming.
	(arm_extensions): Add "ras".
	* doc/c-arm.texi (ARM Options): Add an entry for "ras".
	* testsuite/gas/arm/armv8-a+ras.d: New.
	* testsuite/gas/arm/armv8_2-a.d: Add explicit command line
	options.

include/
	* opcode/arm.h (ARM_EXT2_RAS): New.  Also align preceding
	entries.
	(ARM_AEXT_V8_2A): Add ARM_EXT2_RAS.

opcodes/
	* arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
	ARM_EXT_RAS in relevant entries.
2016-06-07 09:56:42 +01:00
Andrew Burgess
4eb6f89250 Add support for 48 and 64 bit ARC instructions.
gas	* config/tc-arc.c (parse_opcode_flags): New function.
	(find_opcode_match): Move flag parsing code out to new function.
	Ignore operands marked IGNORE.
	(build_fake_opcode_hash_entry): New function.
	(find_special_case_long_opcode): New function.
	(find_special_case): Lookup long opcodes.
	* testsuite/gas/arc/nps400-7.d: New file.
	* testsuite/gas/arc/nps400-7.s: New file.

include	* opcode/arc.h (MAX_INSN_ARGS): Increase to 16.
	(struct arc_long_opcode): New structure.
	(arc_long_opcodes): Declare.
	(arc_num_long_opcodes): Declare.

opcodes	* arc-dis.c (struct arc_operand_iterator): New structure.
	(find_format_from_table): All the old content from find_format,
	with some minor adjustments, and parameter renaming.
	(find_format_long_instructions): New function.
	(find_format): Rewritten.
	(arc_insn_length): Add LSB parameter.
	(extract_operand_value): New function.
	(operand_iterator_next): New function.
	(print_insn_arc): Use new functions to find opcode, and iterator
	over operands.
	* arc-opc.c (insert_nps_3bit_dst_short): New function.
	(extract_nps_3bit_dst_short): New function.
	(insert_nps_3bit_src2_short): New function.
	(extract_nps_3bit_src2_short): New function.
	(insert_nps_bitop1_size): New function.
	(extract_nps_bitop1_size): New function.
	(insert_nps_bitop2_size): New function.
	(extract_nps_bitop2_size): New function.
	(insert_nps_bitop_mod4_msb): New function.
	(extract_nps_bitop_mod4_msb): New function.
	(insert_nps_bitop_mod4_lsb): New function.
	(extract_nps_bitop_mod4_lsb): New function.
	(insert_nps_bitop_dst_pos3_pos4): New function.
	(extract_nps_bitop_dst_pos3_pos4): New function.
	(insert_nps_bitop_ins_ext): New function.
	(extract_nps_bitop_ins_ext): New function.
	(arc_operands): Add new operands.
	(arc_long_opcodes): New global array.
	(arc_num_long_opcodes): New global.
	* arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
2016-06-02 14:03:23 +01:00
Trevor Saunders
1fe0971e41 add more extern C
opcodes/ChangeLog:

2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* nds32-asm.h: Add extern "C".
	* sh-opc.h: Likewise.

bfd/ChangeLog:

2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* elf32-hppa.h: Add extern "C".
	* elf32-nds32.h: Likewise.
	* elf32-tic6x.h: Likewise.

include/ChangeLog:

2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* elf/mips.h: Likewise.
	* elf/sh.h: Likewise.
	* opcode/d10v.h: Likewise.
	* opcode/d30v.h: Likewise.
	* opcode/ia64.h: Likewise.
	* opcode/mips.h: Likewise.
	* opcode/ppc.h: Likewise.
	* opcode/sparc.h: Likewise.
	* opcode/tic6x.h: Likewise.
	* opcode/v850.h: Likewise.
2016-06-01 21:26:32 -04:00
Alan Modra
1a72702bb3 Return void from linker callbacks
The ldmain.c implementation of these linker callback functions always
return true, so any code handling a false return is dead.  What's
more, some of the bfd backends abort if ever a false return is seen,
and there seems to be some confusion in gdb's compile-object-load.c.
The return value was never meant to be "oh yes, a multiple_definition
error occurred", but rather "out of memory or other catastrophic
failure".

This patch removes the status return on the callbacks that always
return true.  I kept the return status for "notice" because that one
does happen to need to return "out of memory".

include/
	* bfdlink.h (struct bfd_link_callbacks): Update comments.
	Return void from multiple_definition, multiple_common,
	add_to_set, constructor, warning, undefined_symbol,
	reloc_overflow, reloc_dangerous and unattached_reloc.
bfd/
	* aoutx.h: Adjust linker callback calls throughout file,
	removing dead code.
	* bout.c: Likewise.
	* coff-alpha.c: Likewise.
	* coff-arm.c: Likewise.
	* coff-h8300.c: Likewise.
	* coff-h8500.c: Likewise.
	* coff-i960.c: Likewise.
	* coff-mcore.c: Likewise.
	* coff-mips.c: Likewise.
	* coff-ppc.c: Likewise.
	* coff-rs6000.c: Likewise.
	* coff-sh.c: Likewise.
	* coff-tic80.c: Likewise.
	* coff-w65.c: Likewise.
	* coff-z80.c: Likewise.
	* coff-z8k.c: Likewise.
	* coff64-rs6000.c: Likewise.
	* cofflink.c: Likewise.
	* ecoff.c: Likewise.
	* elf-bfd.h: Likewise.
	* elf-m10200.c: Likewise.
	* elf-m10300.c: Likewise.
	* elf32-arc.c: Likewise.
	* elf32-arm.c: Likewise.
	* elf32-avr.c: Likewise.
	* elf32-bfin.c: Likewise.
	* elf32-cr16.c: Likewise.
	* elf32-cr16c.c: Likewise.
	* elf32-cris.c: Likewise.
	* elf32-crx.c: Likewise.
	* elf32-d10v.c: Likewise.
	* elf32-epiphany.c: Likewise.
	* elf32-fr30.c: Likewise.
	* elf32-frv.c: Likewise.
	* elf32-ft32.c: Likewise.
	* elf32-h8300.c: Likewise.
	* elf32-hppa.c: Likewise.
	* elf32-i370.c: Likewise.
	* elf32-i386.c: Likewise.
	* elf32-i860.c: Likewise.
	* elf32-ip2k.c: Likewise.
	* elf32-iq2000.c: Likewise.
	* elf32-lm32.c: Likewise.
	* elf32-m32c.c: Likewise.
	* elf32-m32r.c: Likewise.
	* elf32-m68hc1x.c: Likewise.
	* elf32-m68k.c: Likewise.
	* elf32-mep.c: Likewise.
	* elf32-metag.c: Likewise.
	* elf32-microblaze.c: Likewise.
	* elf32-moxie.c: Likewise.
	* elf32-msp430.c: Likewise.
	* elf32-mt.c: Likewise.
	* elf32-nds32.c: Likewise.
	* elf32-nios2.c: Likewise.
	* elf32-or1k.c: Likewise.
	* elf32-ppc.c: Likewise.
	* elf32-s390.c: Likewise.
	* elf32-score.c: Likewise.
	* elf32-score7.c: Likewise.
	* elf32-sh.c: Likewise.
	* elf32-sh64.c: Likewise.
	* elf32-spu.c: Likewise.
	* elf32-tic6x.c: Likewise.
	* elf32-tilepro.c: Likewise.
	* elf32-v850.c: Likewise.
	* elf32-vax.c: Likewise.
	* elf32-visium.c: Likewise.
	* elf32-xstormy16.c: Likewise.
	* elf32-xtensa.c: Likewise.
	* elf64-alpha.c: Likewise.
	* elf64-hppa.c: Likewise.
	* elf64-ia64-vms.c: Likewise.
	* elf64-mmix.c: Likewise.
	* elf64-ppc.c: Likewise.
	* elf64-s390.c: Likewise.
	* elf64-sh64.c: Likewise.
	* elf64-x86-64.c: Likewise.
	* elflink.c: Likewise.
	* elfnn-aarch64.c: Likewise.
	* elfnn-ia64.c: Likewise.
	* elfxx-mips.c: Likewise.
	* elfxx-sparc.c: Likewise.
	* elfxx-tilegx.c: Likewise.
	* linker.c: Likewise.
	* pdp11.c: Likewise.
	* pe-mips.c: Likewise.
	* reloc.c: Likewise.
	* reloc16.c: Likewise.
	* simple.c: Likewise.
	* vms-alpha.c: Likewise.
	* xcofflink.c: Likewise.
	* elf32-rl78.c (get_symbol_value, get_romstart, get_ramstart): Delete
	status param.  Adjust calls to these and linker callbacks throughout.
	* elf32-rx.c: (get_symbol_value, get_gp, get_romstart,
	get_ramstart): Delete status param.  Adjust calls to these and
	linker callbacks throughout.
ld/
	* ldmain.c (multiple_definition, multiple_common, add_to_set,
	constructor_callback, warning_callback, undefined_symbol,
	reloc_overflow, reloc_dangerous, unattached_reloc): Return void.
	* emultempl/elf32.em: Adjust callback calls.
gdb/
	* compile/compile-object-load.c (link_callbacks_multiple_definition,
	link_callbacks_warning, link_callbacks_undefined_symbol,
	link_callbacks_undefined_symbol, link_callbacks_reloc_overflow,
	link_callbacks_reloc_dangerous,
	link_callbacks_unattached_reloc): Return void.
2016-05-28 11:17:20 +09:30
Trevor Saunders
94740f9c4b metag: add extern C to header
include/ChangeLog:

2016-05-26  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* opcode/metag.h: wrap declarations in extern "C".
2016-05-26 06:12:15 -04:00
Claudiu Zissulescu
d9eca1df01 [ARC] Update instruction type and delay slot info.
This patch corrects the instructioninformation passed into the
disassebler_info structure.

include/
2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>

	* opcode/arc.h (insn_subclass_t): Add COND.
	(flag_class_t): Add F_CLASS_EXTEND.

opcodes/
2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
	information.
	(print_insn_arc): Set insn_type information.
	* arc-opc.c (C_CC): Add F_CLASS_COND.
	* arc-tbl.h (bbit0, bbit1): Update subclass to COND.
	(beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
	(ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
	(breq, breq_s, brge, brhs, brlo, brlt): Likewise.
	(brne, brne_s, jeq_s, jne_s): Likewise.
2016-05-23 17:41:54 +02:00
Claudiu Zissulescu
c810e0b87a [ARC] Rename "class" named attributes.
gas/
2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>

	* config/tc-arc.c (attributes_t): Renamed attribute class to
	attr_class.
	(find_opcode_match, assemble_insn, tokenize_extinsn): Changed.

opcode/
2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>

	* arc-dis.c (find_format, find_format, get_auxreg)
	(print_insn_arc): Changed.
	* arc-ext.h (INSERT_XOP): Likewise.

include/
2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>

	* opcode/arc.h (struct arc_opcode): Renamed attribute class to
	insn_class.
	(struct arc_flag_class): Renamed attribute class to flag_class.
2016-05-23 17:25:46 +02:00
Trevor Saunders
3d207518c1 tic54x: rename typedef of struct symbol_
generic gas code has a struct symbol, and tic54x typedefs a struct to symbol.
This seems at least rather confusing, and it seems like target specific headers
shouldn't  put such generic names in the global namespace preventing other
generic code from using them.

opcodes/ChangeLog:

2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* tic54x-dis.c (sprint_mmr): Adjust.
	* tic54x-opc.c: Likewise.

gas/ChangeLog:

2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-tic54x.c (tic54x_mmregs): Adjust.
	(md_begin): Likewise.
	(encode_condition): Likewise.
	(encode_cc3): Likewise.
	(encode_cc2): Likewise.
	(encode_operand): Likewise.
	(tic54x_undefined_symbol): Likewise.

include/ChangeLog:

2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* opcode/tic54x.h (struct symbol_): typedef to tic54x_symbol instead of
	plain symbol.
2016-05-23 01:17:12 -04:00
Tom Tromey
5ff087ac18 Add DW_LANG_Rust
include/
	* dwarf2.h (enum dwarf_source_language) <DW_LANG_Rust,
	DW_LANG_Rust_old>: New constants.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@235643 138bc75d-0d04-0410-961f-82ee72b054a4
2016-05-17 11:11:20 -06:00
Matthew Fortune
8f4f9071ad Add MIPS32 DSPr3 support.
bfd/

	* elfxx-mips.c (print_mips_ases): Add DSPR3.

binutils/

	* readelf.c (print_mips_ases): Add DSPR3.

gas/

	* config/tc-mips.c (options): Add OPTION_DSPR3 and
	OPTION_NO_DSPR3.
	(md_longopts): Likewise.
	(md_show_usage): Add help for -mdspr3 and -mno-dspr3.
	(mips_ases): Define availability for DSPr3.
	(mips_ase_groups): Add ASE_DSPR3 to the DSP group.
	(mips_convert_ase_flags): Map ASE_DSPR3 to AFL_ASE_DSPR3.
	* doc/as.texinfo: Document -mdspr3, -mno-dspr3.  Fix -mdspr2
	formatting.
	* doc/c-mips.texi: Document -mdspr3, -mno-dspr3, .set dspr3 and
	.set nodspr3.  Fix -mdspr2 formatting.
	* testsuite/gas/mips/mips32-dspr3.d: New file.
	* testsuite/gas/mips/mips32-dspr3.s: Likewise.
	* testsuite/gas/mips/mips.exp: Run mips32-dspr3 test.

include/

	* elf/mips.h (AFL_ASE_DSPR3): New macro.
	(AFL_ASE_MASK): Update to include AFL_ASE_DSPR3.
	* opcode/mips.h (ASE_DSPR3): New macro.

opcodes/

	* mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
	mips64r6.
	* mips-opc.c (D34): New macro.
	(mips_builtin_opcodes): Define bposge32c for DSPr3.
2016-05-11 17:06:13 +01:00
Thomas Preud'homme
39d911fc3c Use getters/setters to access ARM branch type
2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>

bfd/
	* elf32-arm.c (elf32_arm_size_stubs): Use new macros
	ARM_GET_SYM_BRANCH_TYPE and ARM_SET_SYM_BRANCH_TYPE to respectively get
	and set branch type of a symbol.
	(bfd_elf32_arm_process_before_allocation): Likewise.
	(elf32_arm_relocate_section): Likewise and fix identation along the
	way.
	(allocate_dynrelocs_for_symbol): Likewise.
	(elf32_arm_finish_dynamic_symbol): Likewise.
	(elf32_arm_swap_symbol_in): Likewise.
	(elf32_arm_swap_symbol_out): Likewise.

gas/
	* config/tc-arm.c (arm_adjust_symtab): Use ARM_SET_SYM_BRANCH_TYPE to
	set branch type of a symbol.

gdb/
	* arm-tdep.c (arm_elf_make_msymbol_special): Use
	ARM_GET_SYM_BRANCH_TYPE to get branch type of a symbol.

include/
	* arm.h (enum arm_st_branch_type): Add new ST_BRANCH_ENUM_SIZE
	enumerator.
	(NUM_ENUM_ARM_ST_BRANCH_TYPE_BITS): New macro.
	(ENUM_ARM_ST_BRANCH_TYPE_BITMASK): Likewise.
	(ARM_SYM_BRANCH_TYPE): Replace by ...
	(ARM_GET_SYM_BRANCH_TYPE): This and ...
	(ARM_SET_SYM_BRANCH_TYPE): This in two versions depending on whether
	BFD_ASSERT is defined or not.

ld/
	* emultempl/armelf.em (gld${EMULATION_NAME}_finish): Use
	ARM_GET_SYM_BRANCH_TYPE to get branch type of a symbol.

opcodes/
	* arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
	branch type of a symbol.
	(print_insn): Likewise.
2016-05-10 16:17:04 +01:00
Thomas Preud'homme
15afaa63f3 Add support for ARMv8-M Mainline with DSP extension
2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>

bfd/
	(elf32_arm_merge_eabi_attributes): Add merging logic for
	Tag_DSP_extension.

binutils/
	* readelf.c (display_arm_attribute): Add output for Tag_DSP_extension.
	(arm_attr_public_tags): Define DSP_extension attribute.

gas/
	* NEWS: Document ARMv8-M and ARMv8-M Security and DSP Extensions.
	* config/tc-arm.c (arm_ext_dsp): New feature for Thumb DSP
	instructions.
	(arm_extensions): Add dsp extension for ARMv8-M Mainline.
	(aeabi_set_public_attributes): Memorize the feature bits of the
	architecture selected for Tag_CPU_arch.  Use it to set
	Tag_DSP_extension to 1 for ARMv8-M Mainline with DSP extension.
	(arm_convert_symbolic_attribute): Define Tag_DSP_extension.
	* testsuite/gas/arm/arch7em-bad.d: Rename to ...
	* testsuite/gas/arm/arch7em-bad-1.d: This.
	* testsuite/gas/arm/arch7em-bad-2.d: New file.
	* testsuite/gas/arm/arch7em-bad-3.d: Likewise.
	* testsuite/gas/arm/archv8m-main-dsp-1.d: Likewise.
	* testsuite/gas/arm/archv8m-main-dsp-2.d: Likewise.
	* testsuite/gas/arm/archv8m-main-dsp-3.d: Likewise.
	* testsuite/gas/arm/archv8m-main-dsp-4.d: Likewise.
	* testsuite/gas/arm/archv8m-main-dsp-5.d: Likewise.
	* testsuite/gas/arm/attr-march-armv8m.main.dsp.d: Likewise.

include/
	* elf/arm.h (Tag_DSP_extension): Define.

ld/
	* testsuite/ld-arm/arm-elf.exp (EABI attribute merging 10 (DSP)): New
	test.
	* testsuite/ld-arm/attr-merge-10b-dsp.s: New file.
	* testsuite/ld-arm/attr-merge-10-dsp.attr: Likewise.
2016-05-10 15:24:10 +01:00
Thomas Preud'homme
d942732e82 Allow extension availability to depend on several architecture bits
2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>

gas/
	* config/tc-arm.c (struct arm_option_extension_value_table): Make
	allowed_archs an array with 2 entries.
	(ARM_EXT_OPT): Adapt to only fill the first entry of allowed_archs.
	(ARM_EXT_OPT2): New macro filling the two entries of allowed_archs.
	(arm_extensions): Use separate entries in allowed_archs when several
	archs are allowed to use an extension and change ARCH_ANY in
	ARM_ARCH_NONE in allowed_archs.
	(arm_parse_extension): Check that, for each allowed_archs entry, all
	bits are set in the current architecture, ignoring ARM_ANY entries.
	(s_arm_arch_extension): Likewise.

include/
	* arm.h (ARM_FSET_CPU_SUBSET): Define macro.
2016-05-10 15:12:11 +01:00
Thomas Preud'homme
16a1fa25be Add support for ARMv8-M security extensions instructions
2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>

gas/
	* config/tc-arm.c (arm_ext_m): Add feature bit ARM_EXT2_V8M_MAIN.
	(arm_ext_v8m_main): New feature set for bit ARM_EXT2_V8M_MAIN.
	(arm_ext_v8m_m_only): New feature set for instructions in ARMv8-M not
	shared with a non M profile architecture.
	(do_rn): New function.
	(known_t32_only_insn): Check opcode against arm_ext_v8m_m_only rather
	than arm_ext_v8m.
	(v7m_psrs): Add ARMv8-M security extensions new special registers.
	(insns): Add ARMv8-M Security Extensions instructions.
	(aeabi_set_public_attributes): Use arm_ext_v8m_m_only instead of
	arm_ext_v8m_m to decide the profile and the Thumb ISA.
	* testsuite/gas/arm/archv8m-cmse.s: New file.
	* testsuite/gas/arm/archv8m-cmse-main.s: Likewise..
	* testsuite/gas/arm/archv8m-cmse-msr.s: Likewise.
	* testsuite/gas/arm/any-cmse.d: Likewise.
	* testsuite/gas/arm/any-cmse-main.d: Likewise.
	* testsuite/gas/arm/archv8m-cmse-base.d: Likewise.
	* testsuite/gas/arm/archv8m-cmse-msr-base.d: Likewise.
	* testsuite/gas/arm/archv8m-cmse-main-1.d: Likewise.
	* testsuite/gas/arm/archv8m-cmse-main-2.d: Likewise.
	* testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise.

include/
	* opcode/arm.h (ARM_EXT2_V8M_MAIN): new feature bit.
	(ARM_AEXT2_V8M_MAIN): New architecture extension feature set.
	(ARM_ARCH_V8M_MAIN): Use ARM_AEXT2_V8M_MAIN instead of ARM_AEXT2_V8M
	for the high core bits.

opcodes/
	* arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
	Mainline Security Extensions instructions.
	(thumb_opcodes): Add entries for narrow ARMv8-M Security
	Extensions instructions.
	(thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
	instructions.
	(psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
	special registers.
2016-05-10 15:03:38 +01:00
Claudiu Zissulescu
945e0f82da [ARC] Add SYNTAX_NOP and SYNTAX_1OP for extension instructions
gas/
2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/tc-arc.c (syntaxclass): Add SYNTAX_NOP and SYNTAX_1OP.
	(arc_extinsn): Handle new introduced syntax.
	* testsuite/gas/arc/textinsn1op.d: New file.
	* testsuite/gas/arc/textinsn1op.s: Likewise.
	* doc/c-arc.texi: Document SYNTAX_NOP and SYNTAX_1OP.

opcodes/
2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
	(arcExtMap_genOpcode): Likewise.
	* arc-opc.c (arg_32bit_rc): Define new variable.
	(arg_32bit_u6): Likewise.
	(arg_32bit_limm): Likewise.

include/
2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>

	* opcode/arc.h (ARC_SYNTAX_1OP): Declare
	(ARC_SYNTAX_NOP): Likewsie.
	(ARC_OP1_MUST_BE_IMM): Update defined value.
	(ARC_OP1_IMM_IMPLIED): Likewise.
	(arg_32bit_rc, arg_32bit_u6, arg_32bit_limm): Declare.
2016-05-04 16:18:32 +02:00
Nick Clifton
4bd13cde17 Add support to AArch64 disassembler for verifying instructions. Add verifier for LDPSW.
PR target/19722
opcodes	* aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
	* aarch64-opc.c (verify_ldpsw): New function.
	* aarch64-opc.h (verify_ldpsw): New prototype.
	* aarch64-tbl.h: Add initialiser for verifier field.
	(LDPSW): Set verifier to verify_ldpsw.

binutils* testsuite/binutils-all/aarch64/illegal.s: New test.
	* testsuite/binutils-all/aarch64/illegal.d: New test driver.

include	* opcode/aarch64.h (struct aarch64_opcode): Add verifier field.
2016-04-28 09:11:03 +01:00
Alan Modra
a6a4679fc0 Cache result of scan for __start_* and __stop_* sections
include/
	* bfdlink.h (struct bfd_link_hash_entry): Add "section" field to
	undef.  Formatting.
bfd/
	* elflink.c (_bfd_elf_is_start_stop): New function.
	(_bfd_elf_gc_mark_rsec): Use it.
	* elf-bfd.h (_bfd_elf_is_start_stop): Declare.
2016-04-27 17:05:26 +09:30
Nick Clifton
4f3b23b390 Add support for non-ELF targets to check their relocs.
bfd	* aout-adobe.c: Use _bfd_generic_link_check_relocs.
	* aout-target.h: Likewise.
	* aout-tic30.c: Likewise.
	* binary.c: Likewise.
	* bout.c: Likewise.
	* coff-alpha.c: Likewise.
	* coff-rs6000.c: Likewise.
	* coff64-rs6000.c: Likewise.
	* coffcode.h: Likewise.
	* i386msdos.c: Likewise.
	* i386os9k.c: Likewise.
	* ieee.c: Likewise.
	* ihex.c: Likewise.
	* libbfd-in.h: Likewise.
	* libecoff.h: Likewise.
	* mach-o-target.c: Likewise.
	* mmo.c: Likewise.
	* nlm-target.h: Likewise.
	* oasys.c: Likewise.
	* pef.c: Likewise.
	* plugin.c: Likewise.
	* ppcboot.c: Likewise.
	* som.c: Likewise.
	* srec.c: Likewise.
	* tekhex.c: Likewise.
	* versados.c: Likewise.
	* vms-alpha.c: Likewise.
	* xsym.c: Likewise.
	* elfxx-target.h: Use _bfd_elf_link_check_relocs.
	* linker.c (bfd_link_check_relocs): New function.
	(_bfd_generic_link_check_relocs): New function.
	* targets.c (BFD_JUMP_TABLE_LINK): Add initialization of
	_bfd_link_check_relocs field.
	(struct bfd_target)L Add _bfd_link_check_relocs field.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.

ld	* ldlang.c (lang_check_relocs): Use bfd_link_check_relocs in
	prefernce to _bfd_elf_link_check_relocs.  Drop test for ELF
	targets.  Do not stop the checks when problems are encountered.

include	* bfdlink.h: Add prototype for bfd_link_check_relocs.
2016-04-21 15:43:00 +01:00
H.J. Lu
d968975277 Check ELF relocs after opening all input files
Delaying checking ELF relocations until opening all input files so
that symbol information is final when relocations are checked.  This
is only enabled for x86 targets.

bfd/

	* elf-bfd.h (_bfd_elf_link_check_relocs): New.
	* elflink.c (_bfd_elf_link_check_relocs): New function.
	(elf_link_add_object_symbols): Call _bfd_elf_link_check_relocs
	if check_relocs_after_open_input is FALSE.

include/

	* bfdlink.h (bfd_link_info): Add check_relocs_after_open_input.

ld/

	* emulparams/elf32_x86_64.sh (CHECK_RELOCS_AFTER_OPEN_INPUT):
	New.
	* emulparams/elf_i386.sh (CHECK_RELOCS_AFTER_OPEN_INPUT):
	Likewise.
	* emulparams/elf_i386_be.sh (CHECK_RELOCS_AFTER_OPEN_INPUT):
	Likewise.
	* emulparams/elf_i386_chaos.sh (CHECK_RELOCS_AFTER_OPEN_INPUT):
	Likewise.
	* emulparams/elf_i386_ldso.sh (CHECK_RELOCS_AFTER_OPEN_INPUT):
	Likewise.
	* emulparams/elf_i386_vxworks.sh (CHECK_RELOCS_AFTER_OPEN_INPUT):
	Likewise.
	* emulparams/elf_x86_64.sh (CHECK_RELOCS_AFTER_OPEN_INPUT):
	Likewise.
	* emulparams/i386nto.sh (CHECK_RELOCS_AFTER_OPEN_INPUT):
	Likewise.
	* emultempl/elf32.em (gld${EMULATION_NAME}_before_parse):
	Set check_relocs_after_open_input to TRUE if
	CHECK_RELOCS_AFTER_OPEN_INPUT is yes.
	(gld${EMULATION_NAME}_after_open): Call
	_bfd_elf_link_check_relocs on all inputs if
	check_relocs_after_open_input is TRUE.
2016-04-20 05:26:51 -07:00
Andrew Burgess
52176c676d arc: Fix relocation formula for ARC_NPS_CMEM16 relocation
The ME modifier was missing from the relocation formula for the
ARC_NPS_CMEM16 relocation, and as such the relocation would not patch
correctly on little endian targets.

include/ChangeLog:

	* elf/arc-reloc.def (ARC_NPS_CMEM16): Add ME modifier to formula.
2016-04-20 11:45:24 +01:00
Andrew Burgess
537aefaf18 opcodes/arc: Add yet more nps instructions
Add some more arc/nps400 instructions and the associated operands.
There's also a test added into the assembler.

gas/ChangeLog:

	* testsuite/gas/arc/nps400-6.d: New file.
	* testsuite/gas/arc/nps400-6.s: New file.

include/ChangeLog:

	* opcode/arc.h (MAX_INSN_ARGS): Increase 6 to 8.

opcodes/ChangeLog:

	* arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
	fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, and qcmp
	instructions.
	* arc-opc.c (insert_nps_bitop_size): Delete.
	(extract_nps_bitop_size): Delete.
	(MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
	(extract_nps_qcmp_m3): Define.
	(extract_nps_qcmp_m2): Define.
	(extract_nps_qcmp_m1): Define.
	(arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
	(arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
	(arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
	NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
	NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
	NPS_QCMP_M3.
2016-04-19 22:51:27 +01:00
Andrew Burgess
c8f785f220 opcodes/arc: Add more nps instructions
Add dctcp, dcip, dcet, and dcacl instructions.

gas/ChangeLog:

	* testsuite/gas/arc/nps400-4.d: New file.
	* testsuite/gas/arc/nps400-4.s: New file.
	* testsuite/gas/arc/nps400-5.d: New file.
	* testsuite/gas/arc/nps400-5.s: New file.

include/ChangeLog:

	* opcode/arc.h (insn_class_t): Add NET and ACL class.

opcodes/ChangeLog:

	* arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
2016-04-19 22:50:33 +01:00
Andrew Burgess
4b0c052e45 arc/nps400 : New cmem instructions and associated relocation
Add support for arc/nps400 cmem instructions, these load and store
instructions are hard-wired to access "0x57f00000 + 16-bit-offset".

Supporting this relocation required some additions to the arc relocation
handling in the bfd library, as well as the standard changes required to
add a new relocation type.

There's a test of the new instructions in the assembler, and a test of
the relocation in the linker.

bfd/ChangeLog:

	* reloc.c: Add BFD_RELOC_ARC_NPS_CMEM16 entry.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.
	* elf32-arc.c: Add 'opcode/arc.h' include.
	(struct arc_relocation_data): Add symbol_name.
	(arc_special_overflow_checks): New function.
	(arc_do_relocation): Use arc_special_overflow_checks, reindent as
	required, add an extra comment.
	(elf_arc_relocate_section): Setup symbol_name in reloc_data.

gas/ChangeLog:

	* testsuite/gas/arc/nps400-3.d: New file.
	* testsuite/gas/arc/nps400-3.s: New file.

include/ChangeLog:

	* elf/arc-reloc.def: Add ARC_NPS_CMEM16 reloc.
	* opcode/arc.h (NPS_CMEM_HIGH_VALUE): Define.

ld/ChangeLog:

	* testsuite/ld-arc/arc.exp: New file.
	* testsuite/ld-arc/nps-1.s: New file.
	* testsuite/ld-arc/nps-1a.d: New file.
	* testsuite/ld-arc/nps-1b.d: New file.
	* testsuite/ld-arc/nps-1b.err: New file.

opcodes/ChangeLog:

	* arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
	instructions.
	* arc-opc.c (insert_nps_cmem_uimm16): New function.
	(extract_nps_cmem_uimm16): New function.
	(arc_operands): Add NPS_XLDST_UIMM16 operand.
2016-04-14 17:16:46 +01:00
Claudiu Zissulescu
f36e33dac1 Add support for .extCondCode, .extCoreRegister and .extAuxRegister.
gas/
2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>

	* testsuite/gas/arc/textauxregister.d: New file.
	* testsuite/gas/arc/textauxregister.s: Likewise.
	* testsuite/gas/arc/textcondcode.d: Likewise.
	* testsuite/gas/arc/textcondcode.s: Likewise.
	* testsuite/gas/arc/textcoreregister.d: Likewise.
	* testsuite/gas/arc/textcoreregister.s: Likewise.
	* testsuite/gas/arc/textpseudoop.d: Likewise.
	* testsuite/gas/arc/textpseudoop.s: Likewise.
	* testsuite/gas/arc/ld2.d: Update test.
	* testsuite/gas/arc/st.d: Likewise.
	* testsuite/gas/arc/taux.d: Likewise.
	* doc/c-arc.texi (ARC Directives): Add .extCondCode,
	.extCoreRegister and .extAuxRegister documentation.
	* config/tc-arc.c (arc_extcorereg): New function.
	(md_pseudo_table): Add .extCondCode, .extCoreRegister and
	.extAuxRegister pseudo-ops.
	(extRegister_t): New type.
	(ext_condcode, arc_aux_hash): New global variable.
	(find_opcode_match): Check for extensions.
	(preprocess_operands): Likewise.
	(md_begin): Add aux registers in a hash.
	(assemble_insn): Update use arc_flags member.
	(tokenize_extregister): New function.
	(create_extcore_section): Likewise.
	* config/tc-arc.h (MAX_FLAG_NAME_LENGHT): Increase to 10.
	(arc_flags): Delete code, add flgp.

include/
2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>

	* opcode/arc.h (flag_class_t): Update.
	(ARC_OPCODE_NONE): Define.
	(ARC_OPCODE_ARCALL): Likewise.
	(ARC_OPCODE_ARCFPX): Likewise.
	(ARC_REGISTER_READONLY): Likewise.
	(ARC_REGISTER_WRITEONLY): Likewise.
	(ARC_REGISTER_NOSHORT_CUT): Likewise.
	(arc_aux_reg): Add cpu.

opcodes/
2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-dis.c (find_format): Check for extension flags.
	(print_flags): New function.
	(print_insn_arc): Update for .extCondCode, .extCoreRegister and
	.extAuxRegister.
	* arc-ext.c (arcExtMap_coreRegName): Use
	LAST_EXTENSION_CORE_REGISTER.
	(arcExtMap_coreReadWrite): Likewise.
	(dump_ARC_extmap): Update printing.
	* arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
	(arc_aux_regs): Add cpu field.
	* arc-regs.h: Add cpu field, lower case name aux registers.

Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-12 10:21:06 +02:00
Claudiu Zissulescu
b99747aeed Add support for .extInstruction pseudo-op.
gas/
2016-04-04  Claudiu Zissulescu  <claziss@synopsys.com>

	* testsuite/gas/arc/textinsn-errors.d: New File.
	* testsuite/gas/arc/textinsn-errors.err: Likewise.
	* testsuite/gas/arc/textinsn-errors.s: Likewise.
	* testsuite/gas/arc/textinsn2op.d: Likewise.
	* testsuite/gas/arc/textinsn2op.s: Likewise.
	* testsuite/gas/arc/textinsn2op01.d: Likewise.
	* testsuite/gas/arc/textinsn2op01.s: Likewise.
	* testsuite/gas/arc/textinsn3op.d: Likewise.
	* testsuite/gas/arc/textinsn3op.s: Likewise.
	* doc/c-arc.texi (ARC Directives): Add .extInstruction
	documentation.
	* config/tc-arc.c (arcext_section): New variable.
	(arc_extinsn): New function.
	(md_pseudo_table): Add .extInstruction pseudo op.
	(attributes_t): New type.
	(suffixclass, syntaxclass, syntaxclassmod): New constant
	structures.
	(find_opcode_match): Remove arc_num_opcodes.
	(md_begin): Likewise.
	(tokenize_extinsn): New function.
	(arc_set_ext_seg): Likewise.
	(create_extinst_section): Likewise.

include/
2016-04-04  Claudiu Zissulescu  <claziss@synopsys.com>

	* opcode/arc.h (arc_num_opcodes): Remove.
	(ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM)
	(ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND)
	(ARC_SUFFIX_FLAG): Define.
	(flags_none, flags_f, flags_cc, flags_ccf): Declare.
	(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
	(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
	(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
	(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
	(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
	(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
	(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
	(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
	(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.

opcodes/
2016-04-04  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
	Initialize.
	(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
	(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
	(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
	(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
	(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
	(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
	(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
	(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
	(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
	(arc_opcode arc_opcodes): Null terminate the array.
	(arc_num_opcodes): Remove.
	* arc-ext.h (INSERT_XOP): Define.
	(extInstruction_t): Likewise.
	(arcExtMap_instName): Delete.
	(arcExtMap_insn): New function.
	(arcExtMap_genOpcode): Likewise.
	* arc-ext.c (ExtInstruction): Remove.
	(create_map): Zero initialize instruction fields.
	(arcExtMap_instName): Remove.
	(arcExtMap_insn): New function.
	(dump_ARC_extmap): More info while debuging.
	(arcExtMap_genOpcode): New function.
	* arc-dis.c (find_format): New function.
	(print_insn_arc): Use find_format.
	(arc_get_disassembler): Enable dump_ARC_extmap only when
	debugging.

Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-12 10:06:07 +02:00
Claudiu Zissulescu
8ddf6b2a13 [ARC] Fix support for double assist instructions.
opcodes/
2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>

        * arc-regs.h: Add a new subclass field.  Add double assist
        accumulator register values.
        * arc-tbl.h: Use DPA subclass to mark the double assist
        instructions.  Use DPX/SPX subclas to mark the FPX instructions.
        * arc-opc.c (RSP): Define instead of SP.
        (arc_aux_regs): Add the subclass field.

include/
2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>

        * opcode/arc.h (DPA, DPX, SPX): New subclass enums.
        (ARC_FPUDA): Define.
        (arc_aux_reg): Add new field.

gas/
2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>

        * config/tc-arc.c (is_code_density_p): Compare directly the
        subclass field.
        (is_spfp_p, is_dpfp_p, is_spfp_p): Define.
        (check_cpu_feature): New function.
        (find_opcode_match): Use check_cpu_feature function.
        (preprocess_operands): Likewise.
        (md_parse_option): Use mfpuda, mdpfp, mspfp options.
        * testsuite/gas/arc/tdpfp.d: New file.
        * testsuite/gas/arc/tfpuda.d: Likewise.
        * testsuite/gas/arc/tfpx.s: Likewise.
2016-04-05 17:37:45 +02:00
Claudiu Zissulescu
094fb06395 [ARC] 24 bit reloc and overflow detection fix.
bfd/
2016-04-05  Cupertino Miranda  <cmiranda@synopsys.com>

	* elf32-arc.c (name_for_global_symbol): Changed assert.
	(get_replace_function): Created.:
	(struct arc_relocation_data): Changed to signed types.
	(defines S, L, P, PDATA): Casted to signed type.
	(defines SECTSTART, _SDA_BASE_, TLS_REL): Likewise.
	(PRINT_DEBUG_RELOC_INFO_BEFORE): Changed.
	(arc_do_relocation): Changed.

include/
2016-04-05  Cupertino Miranda  <cmiranda@synopsys.com>

	* opcode/arc-func.h (replace_bits24): Changed.
	(replace_bits24_be): Created.
2016-04-05 17:05:09 +02:00
Claudiu Zissulescu
f2dd88387a [ARC] Add support for Quarkse opcodes.
gas/
2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>

        * testsuite/gas/arc/ext2op.d: New file.
        * testsuite/gas/arc/ext2op.s: Likewise.
        * testsuite/gas/arc/ext3op.d: Likewise.
        * testsuite/gas/arc/ext3op.s: Likewise.

opcodes/
2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>

        * arc-tbl.h (invld07): Remove.
        * arc-ext-tbl.h: New file.
        * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
        * arc-opc.c (arc_opcodes): Add ext-tbl include.

include/
2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>

        * opcode/arc.h (insn_subclass_t): Add QUARKSE subclass.
        (FIELDA, FIELDB, FIELDC, FIELDF, FIELDQ, INSN3OP, INSN2OP)
        (INSN2OP, INSN3OP_ABC, INSN3OP_ALC, INSN3OP_ABL, INSN3OP_ALL)
        (INSN3OP_0BC, INSN3OP_0LC, INSN3OP_0BL, INSN3OP_0LL, INSN3OP_ABU)
        (INSN3OP_ALU, INSN3OP_0BU, INSN3OP_0LU, INSN3OP_BBS, INSN3OP_0LS)
        (INSN3OP_CBBC, INSN3OP_CBBL, INSN3OP_C0LC, INSN3OP_C0LL)
        (INSN3OP_CBBU, INSN3OP_C0LU, MINSN3OP_ABC, MINSN3OP_ALC)
        (MINSN3OP_ABL, MINSN3OP_ALL, MINSN3OP_0BC, MINSN3OP_0LC)
        (MINSN3OP_0BL, MINSN3OP_0LL, MINSN3OP_ABU, MINSN3OP_ALU)
        (MINSN3OP_0BU, MINSN3OP_0LU, MINSN3OP_BBS, MINSN3OP_0LS)
        (MINSN3OP_CBBC, MINSN3OP_CBBL, MINSN3OP_C0LC, MINSN3OP_C0LL)
        (MINSN3OP_CBBU, MINSN3OP_C0LU, INSN2OP_BC, INSN2OP_BL, INSN2OP_0C)
        (INSN2OP_0L INSN2OP_BU, INSN2OP_0U, MINSN2OP_BC, MINSN2OP_BL)
        (MINSN2OP_0C, MINSN2OP_0L, MINSN2OP_BU, MINSN2OP_0U): Define.
2016-03-29 14:49:22 +02:00
Trevor Saunders
b9bb4a9356 make more variables const
gas/ChangeLog:

2016-03-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-h8300.c (h8300_elf_section): Add const qualifiers.
	* config/tc-ia64.c (obj_elf_vms_common): Likewise.
	* config/tc-m68hc11.c (md_begin): Likewise.
	(print_opcode_list): Likewise.
	* config/tc-msp430.c (msp430_section): Likewise.
	* config/tc-score.c (struct s3_insn_to_dependency): Likewise.
	(s3_build_dependency_insn_hsh): Likewise.
	* config/tc-score7.c (struct s7_insn_to_dependency): Likewise.
	(s7_build_dependency_insn_hsh): Likewise.
	* config/tc-tic4x.c: Likewise.
	* config/tc-tic54x.c (tic54x_set_default_include): Likewise.
	(subsym_get_arg): Likewise.
	* config/tc-xtensa.c (struct suffix_reloc_map): Likewise.
	(get_directive): Likewise.
	(cache_literal_section): Likewise.
	* config/xtensa-relax.c: Likewise.
	* symbols.c (symbol_create): Likewise.
	(local_symbol_make): Likewise.
	(symbol_relc_make_expr): Likewise.

include/ChangeLog:

2016-03-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* opcode/i960.h: Add const qualifiers.
	* opcode/tic4x.h (struct tic4x_inst): Likewise.
2016-03-22 19:16:06 -04:00
Andrew Burgess
e23e8ebee3 arc/nps400: Add first nps400 instructions
Adds the first few nps400 instructions.

gas/ChangeLog:

	* testsuite/gas/arc/nps400-0.d: New file.
	* testsuite/gas/arc/nps400-0.s: New file.
	* testsuite/gas/arc/nps400-1.d: New file.
	* testsuite/gas/arc/nps400-1.s: New file.

include/ChangeLog:

	* opcodes/arc.h (insn_class_t): Add BITOP type.

opcodes/ChangeLog:

	* arc-nps400-tbl.h: New file.
	* arc-opc.c: Add top level comment.
	(insert_nps_3bit_dst): New function.
	(extract_nps_3bit_dst): New function.
	(insert_nps_3bit_src2): New function.
	(extract_nps_3bit_src2): New function.
	(insert_nps_bitop_size): New function.
	(extract_nps_bitop_size): New function.
	(arc_flag_operands): Add nps400 entries.
	(arc_flag_classes): Add nps400 entries.
	(arc_operands): Add nps400 entries.
	(arc_opcodes): Add nps400 include.
2016-03-21 16:44:50 +00:00
Andrew Burgess
1ae8ab4714 arc/opcodes: Use flag operand class to handle multiple flag matches
When parsing the operand instruction flags we don't currently detect the
case where multiple flags are provided from the same class set, these
will be accepted and the bit values merged together, resulting in the
wrong instruction being assembled.  For example:

    adc.n.eq r0,r0,r2

Will assemble without error, yet, upon disassembly, the instruction will
actually be:

    adc.c r0,r0,r2

In a later commit the concept of required flags will be introduced.
Required flags are just like normal instruction flags, except that they
must be present for the instruction to match.  Adding this will allow
for simpler instructions in the instruction table, and allow for more
sharing of operand extraction and insertion functions.

To solve both of the above issues (multiple flags being invalid, and
required flags), this commit reworks the flag class mechanism.
Currently the flag class is never used.  Each instruction can reference
multiple flag classes, each flag class has a class type and a set of
flags.  However, at present, the class type is never used.  The current
values identify the type of instruction that the flag will be used in,
but this is not required information.

Instead, this commit discards the old flag classes, and introduces 3 new
classes.  The first F_CLASS_NONE, is just a NULL marker value, and is
only used in the NULL marker flag class.  The other two flag classes are
F_FLAG_OPTIONAL, and F_FLAG_REQUIRED.

The class F_FLAG_OPTIONAL has the property that at most one of the flags
in the flag set for that class must be present in the instruction.  The
"at most" one means that no flags being present is fine.

The class F_FLAG_REQUIRED is not currently used, but will be soon.  With
this class, exactly one of the flags from this class must be present in
the instruction.  If the flag class contains a single flag, then of
course that flag must be present.  However, if the flag class contained
two or more, then one, and only one of them must be present.

gas/ChangeLog:

	* config/tc-arc.c (find_opcode_match): Move lnflg, and i
	declarations to start of block.  Reset code on all flags before
	attempting to match them.  Handle multiple hits on the same flag.
	Handle flag class.
	* testsuite/gas/arc/asm-errors.d: New file.
	* testsuite/gas/arc/asm-errors.err: New file.
	* testsuite/gas/arc/asm-errors.s: New file.

include/ChangeLog:

	* opcode/arc.h (flag_class_t): Remove all old flag classes, add 3
	new classes instead.

opcodes/ChangeLog:

	* arc-opc.c (arc_flag_classes): Convert all flag classes to use
	the new class enum values.
2016-03-21 16:44:50 +00:00
Andrew Burgess
8699fc3e88 arc: Add nps400 machine type, and assembler flag.
This commit introduces the nps400 machine type as a variant of arc.
There's a new flag in the assembler to select this machine type.  All
other changes are just adding handling of the new machine type into the
relevant places.

The nps400 is an arc700 variant with some vendor specific instructions
added into the instruction set.  This commit does not add any of the new
instructions, this is just laying the groundwork for future commits.
However, in preparation for these new instructions a new opcode define for
nps400 has been added to include/opcode/arc.h, this new opcode define is
used in the assembler and disassembler along with the existing define
for arc700 such that when assembling and disassembling for nps400 the
user will have access to all arc700 instructions and all the nps400
vendor extension instructions.

bfd/ChangeLog:

	* archures.c (bfd_mach_arc_nps400): Define.
	* bfd-in2.h: Regenerate.
	* cpu-arc.c (arch_info_struct): New entry for nps400, renumber
	some existing entries to make space.
	* elf32-arc.c (arc_elf_object_p): Add nps400 case.
	(arc_elf_final_write_processing): Likewise.

binutils/ChangeLog:

	* readelf.c (decode_ARC_machine_flags): Handle nps400.

gas/ChangeLog:

	* config/tc-arc.c (cpu_types): Add nps400 entry.
	(check_zol): Handle nps400.

include/ChangeLog:

	* elf/arc.h (E_ARC_MACH_NPS400): Define.
	* opcode/arc.h (ARC_OPCODE_NPS400): Define.

opcodes/ChangeLog:

	* arc-dis.c (print_insn_arc): Handle nps400.
2016-03-21 16:44:49 +00:00
Andrew Burgess
a9522a2168 arc: Remove EF_ARC_CPU_GENERIC constant.
The constant EF_ARC_CPU_GENERIC is defined in the include/elf/arc.h
file, and is used in a few places in binutils, however, this constant
should never make it into the elf header flags; we always set a valid
cpu type in the assembler, which should then be copied over during
linking.

There are some non-gnu arc compilers that don't write an architecture
type into the e_flags field, instead leaving the field as 0, which is
the EF_ARC_CPU_GENERIC value.  This non-gnu compiler uses the machine
type to distinguish between the old and newer arc architectures, setting
the machine type to EM_ARC_COMPACT for old arc600, arc601, and arc700
architectures, while using EM_ARC_COMPACT2 for newer arcem and archs
architectures.

Previously when displaying the machine flags for an older EM_ARC_COMPACT
machine, if the e_flags had not been filled in, then we relied on the
default case statement to display the message "Generic ARCompact", while
in the EM_ARC_COMPACT2 case we specifically handled EF_ARC_CPU_GENERIC
to print "ARC Generic", leaving the default case to print a message
about unrecognised cpu flag.

After this commit EF_ARC_CPU_GENERIC has been removed, for both machine
types EM_ARC_COMPACT and EM_ARC_COMPACT2 we now rely on the default case
statement to handle the situation where the e_flags has not been filled
in.  The message displayed is now "Unknown ARCompact" (for older arc
architectures) and "Unknown ARC" (for the newer architectures).  The
switch from "Generic" to "Unknown" in the message string is for clarity,
calling the file "Generic" can give the impression that the file is
compiled for a common sub-set of the architectures, and would therefore
run on any type of machine (or at least any type of new or old machine
depending on if the machine type is ARC or ARCv2).  However, this was
not what "Generic" meant, it really meant "Unknown", so that's what we
now say.

As part of the merging of the readelf flag reading code, I have unified
the strings used in displaying the ELF ABI.  This means that for older
arc machines (arc600, arc601, and arc700) the string used for the
original ABI, and ABIv2 have changed, the current ABIv3 remains the
same.  For the newer architectures (arcem and archs) the abi strings
remain unchanged in all cases.

bfd/ChangeLog:

	* elf32-arc.c (arc_elf_print_private_bfd_data): Remove use of
	EF_ARC_CPU_GENERIC.
	(arc_elf_final_write_processing): Don't bother setting cpu field
	in e_flags, this will have been set elsewhere.

binutils/ChangeLog:

	* readelf.c (get_machine_flags): Move arc processing into...
	(decode_ARC_machine_flags): ... new function.  Remove use of
	EF_ARC_CPU_GENERIC, change default case from "generic arc" to
	"unknown arc".  Merged ABI printing between two machine types.

gas/ChangeLog:

	* config/tc-arc.c (arc_select_cpu): Remove use of
	EF_ARC_CPU_GENERIC.

include/ChangeLog:

	* elf/arc.h (EF_ARC_CPU_GENERIC): Delete.  Update related comment.
2016-03-21 16:44:49 +00:00
Andrew Burgess
c033458051 arc: Remove duplicated constant in include/elf/arc.h
In the include/elf/arc.h there are two constants that mask out the
machine architecture field.  One is used lots (EF_ARC_MACH_MSK), the
other is used only once (EF_ARC_MACH).  Remove EF_ARC_MACH.

bfd/ChangeLog:

	* elf32-arc.c (arc_elf_final_write_processing): Switch to using
	EF_ARC_MACH_MSK.

include/ChangeLog:

	* elf/arc.h (EF_ARC_MACH): Delete.
	(EF_ARC_MACH_MSK): Remove out of date comment.
2016-03-21 16:44:49 +00:00
Andrew Burgess
24740d83e4 arc/gas: default mach is arc700, initialised in md_begin
This commit restructures the selection of the default cpu/mach so that
the choice is made from md_begin (if the user has not provided a command
line choice).  This will reduce the amount of change needed in a later
patch.

At the request of Synopsys, the default architecture changes to ARC700
from this commit, previously the default was a non-existent
super-architecture that contained all instructions from all arc
variants.  There's some clean up associated with removing the default
merged architecture, and a small test fix now that the default is
ARC700.

binutils/ChangeLog:

	* testsuite/binutils-all/objdump.exp (cpus_expected): Add ARC700
	to the architecture list.

gas/ChangeLog:

	* config/tc-arc.c (arc_target): Delay initialisation until
	arc_select_cpu.
	(arc_target_name): Likewise.
	(arc_features): Likewise.
	(arc_mach_type): Likewise.
	(cpu_types): Remove "all" entry.
	(arc_select_cpu): New function, most of the content is from...
	(md_parse_option): ... here.  Call new arc_select_cpu.
	(md_begin): Call arc_select_cpu if needed, default is now arc700.

include/ChangeLog:

	* opcode/arc.h (ARC_OPCODE_BASE): Delete.

opcodes/ChangeLog:

	* arc-opc.c (BASE): Delete.
2016-03-21 16:44:49 +00:00
H.J. Lu
4c10bbaa09 Add -z noreloc-overflow option to x86-64 ld
Add -z noreloc-overflow command-line option to the x86-64 ELF linker to
disable relocation overflow check.  This can be used to avoid relocation
overflow check if there will be no dynamic relocation overflow at
run-time.

bfd/

	PR ld/19807
	* elf64-x86-64.c (elf_x86_64_relocate_section): Check
	no_reloc_overflow_check to diable R_X86_64_32/R_X86_64_32S
	relocation overflow check.

include/

	PR ld/19807
	* bfdlink.h (bfd_link_info): Add no_reloc_overflow_check.

ld/

	PR ld/19807
	* Makefile.am (ELF_X86_DEPS): Add
	$(srcdir)/emulparams/reloc_overflow.sh.
	* Makefile.in: Regenerated.
	* NEWS: Mention -z noreloc-overflow.
	* ld.texinfo: Document -z noreloc-overflow.
	* emulparams/elf32_x86_64.sh: Source
	${srcdir}/emulparams/reloc_overflow.sh.
	* emulparams/elf_x86_64.sh: Likewise.
	* emulparams/reloc_overflow.sh: New file.
	* testsuite/ld-x86-64/pr19807-1.s: New file.
	* testsuite/ld-x86-64/pr19807-1a.d: Likewise.
	* testsuite/ld-x86-64/pr19807-1b.d: Likewise.
	* testsuite/ld-x86-64/pr19807-2.s: Likewise.
	* testsuite/ld-x86-64/pr19807-2a.d: Likewise.
	* testsuite/ld-x86-64/pr19807-2b.d: Likewise.
	* testsuite/ld-x86-64/pr19807-2c.d: Likewise.
	* testsuite/ld-x86-64/pr19807-2d.d: Likewise.
	* testsuite/ld-x86-64/pr19807-2e.d: Likewise.
	* testsuite/ld-x86-64/x86-64.exp: Run PR ld/19807 tests.
2016-03-15 11:07:54 -07:00
Claudiu Zissulescu
72f3b6aae7 [ARC] Allow non-instruction relocations within .text sections
bfd/
2016-03-08  Cupertino Miranda  <Cupertino.Miranda@synopsys.com>
	    Andrew Burgess  <andrew.burgess@embecosm.com>

	* elf32-arc.c (arc_bfd_get_32): Becomes an alias for bfd_get_32.
	(arc_bfd_put_32): Becomes an alias for bfd_put_32.
	(arc_elf_howto_init): Added assert to validate relocations.
	(get_middle_endian_relocation): Delete.
	(middle_endian_convert): New function.
	(ME): Redefine, now does nothing.
	(IS_ME): New define.
	(arc_do_relocation): Extend the attached 'ARC_RELOC_HOWTO'
	definition to call middle_endian_convert.  Add a new local
	variable and make use of this throughout. Added call to
	arc_bfd_get_8 and arc_bfd_put_8 for 8 bit relocations.

gas/
2016-03-08  Andrew Burgess  <andrew.burgess@embecosm.com>

	* testsuite/gas/arc/inline-data-1.d: New file.
	* testsuite/gas/arc/inline-data-1.s: New file.

include/
2016-03-08  Cupertino Miranda  <Cupertino.Miranda@synopsys.com>
	    Andrew Burgess  <andrew.burgess@embecosm.com>

	* elf/arc-reloc.def: Add a call to ME within the formula for each
	relocation that requires middle-endian correction.
2016-03-08 14:19:52 +01:00
Trevor Saunders
f86f586366 Add const qualifiers at various places.
opcodes	* mcore-opc.h: Add const qualifiers.
	* microblaze-opc.h (struct op_code_struct): Likewise.
	* sh-opc.h: Likewise.
	* tic4x-dis.c (tic4x_print_indirect): Likewise.
	(tic4x_print_op): Likewise.

include	* opcode/dlx.h (struct dlx_opcode): Add const qualifiers.
	* opcode/h8300.h (struct h8_opcode): Likewise.
	* opcode/hppa.h (struct pa_opcode): Likewise.
	* opcode/msp430.h: Likewise.
	* opcode/spu.h (struct spu_opcode): Likewise.
	* opcode/tic30.h (struct _register): Likewise.
	* opcode/tic4x.h (struct tic4x_register): Likewise.
	(struct tic4x_cond): Likewise.
	(struct tic4x_indirect): Likewise.
	(struct tic4x_inst): Likewise.
	* opcode/visium.h (struct reg_entry): Likewise.

gas	* config/tc-arc.c: Add const qualifiers.
	* config/tc-h8300.c (md_begin): Likewise.
	* config/tc-ia64.c (print_prmask): Likewise.
	* config/tc-msp430.c (msp430_operands): Likewise.
	* config/tc-nds32.c (struct suffix_name): Likewise.
	(struct nds32_parse_option_table): Likewise.
	(struct nds32_set_option_table): Likewise.
	(do_pseudo_pushpopm): Likewise.
	(do_pseudo_pushpop_stack): Likewise.
	(nds32_relax_relocs): Likewise.
	(nds32_flag): Likewise.
	(struct nds32_hint_map): Likewise.
	(nds32_find_reloc_table): Likewise.
	(nds32_match_hint_insn): Likewise.
	* config/tc-s390.c: Likewise.
	* config/tc-sh.c (get_specific): Likewise.
	* config/tc-tic30.c: Likewise.
	* config/tc-tic4x.c (tic4x_inst_add): Likewise.
	(tic4x_indirect_parse): Likewise.
	* config/tc-vax.c (vax_cons): Likewise.
	* config/tc-z80.c (struct reg_entry): Likewise.
	* config/tc-epiphany.c (md_assemble): Adjust.
	(epiphany_assemble): New function.
	(epiphany_elf_section_rtn): Call do_align directly.
	(epiphany_elf_section_text): Likewise.
	* config/tc-ip2k.c (ip2k_elf_section_rtn): Likewise.
	(ip2k_elf_section_text): Likewise.
	* read.c (do_align): Make it not static.
	* read.h (do_align): New prototype.
2016-03-07 15:16:28 +00:00
Cary Coutant
9b738e36e6 Fix datestamps on ChangeLog entries to read 2015 instead of 2016. 2016-03-04 14:19:12 -08:00
H.J. Lu
3f1f41f55f Add missing ChangeLog entries for commit 82838
Fix gold/testsuite/plugin_layout_with_alignment.sh permission.
2016-03-04 08:28:12 -08:00
Matthew Wahab
643afb90da [ARM] Add feature check for ARMv8.1 AdvSIMD instructions.
gas/
2016-03-04  Matthew Wahab  <matthew.wahab@arm.com>

	* config/gas/tc-arm.c (fpu_neon_ext_v8_1): Restrict to the ARMv8.1 RDMA
	feature.
	(record_feature_use): New.
	(mark_feature_used): Use record_feature_use.
	(do_neon_qrdmlah): New.
	(insns): Use do_neon_qrdmlah for vqrdmlah and vqrdmlsh and
	variants.
	(arm_extensions): Put into alphabetical order.  Re-indent "simd"
	and "rdma" entries.  Fix the incorrect merge value for "+rdma".
	* testsuite/gas/arm/armv8-a+rdma-warning.d: New.
	* testsuite/gas/arm/armv8-a+rdma.d: Add assembler command line options.
	Make source file explicit.
	* testsuite/gas/arm/armv8-a+rdma.l: New.
	* testsuite/gas/arm/armv8-a+rdma.s: Remove .arch and .arch_extension
	directives.  Fix white-space.
	* testsuite/gas/arm/armv8_1-a+simd.d: New.

include/opcode
2016-03-04  Matthew Wahab  <matthew.wahab@arm.com>

	* arm.h (ARM_ARCH_V8_1A): Add FPU_NEON_EXT_RDMA.
	(ARM_CPU_HAS_FEATURE): Add comment.

Change-Id: Ie19250e8fa50aed44e44ab40ff30b04b38bc1a3d
2016-03-04 11:32:04 +00:00
Evgenii Stepanov
95ecdfbfcb get_symbols() plugin API tweak to support --start-lib/--end-lib.
Let the plugin know that a file is not being included in the link by
returning LDPS_NO_SYMS from get_symbols().

include/
	* plugin-api.h (enum ld_plugin_tag): Add LDPT_GET_SYMBOLS_V3.

gold/
	* plugin.h (Pluginobj::get_symbol_resolution_info): Add version
	parameter.
	* plugin.cc (get_symbols_v3): New function.
	(Plugin::load): Add LDPT_GET_SYMBOLS_V3.
	(Pluginobj::get_symbol_resolution_info): Return LDPS_NO_SYMS when using
	new version.
2016-03-03 11:42:13 -08:00
H.J. Lu
11e5f1ec54 Add ChangeLog entries for PR ld/19645 2016-02-26 06:44:03 -08:00
H.J. Lu
aec6b87e0b [x86] Resolve non-PIC undefweak symbols in executable
For i386 and x86-64, non-PIC references to undefined weak symbols are
resolved without dynamic relocation when creating executable.  Resolved
undefined weak symbols are removed from the dynamic symbol table in
executable.  One exception is on i386, we need resolved undefined weak
symbols in the dynamic symbol table in PIE if input relocatable files
contain branchs without PLT so that we can branch to 0 with dynamic
relocation in text section.

This makes behaviors of dynamic executable and position independent
executable predictable with mixed PIC and non-PIC references to undefined
weak symbols.  If all references to undefined weak symbols are PIC,
dynamic relocations against undefined weak symbols will be generated
in executable unless -z nodynamic-undefined-weak is passed to linker.

bfd/

	PR ld/19636
	PR ld/19704
	PR ld/19719
	* elf32-i386.c (UNDEFINED_WEAK_RESOLVED_TO_ZERO): New.
	(elf_i386_link_hash_entry): Add has_got_reloc and
	has_non_got_reloc.
	(elf_i386_link_hash_table): Add interp.
	(elf_i386_link_hash_newfunc): Initialize has_got_reloc and
	has_non_got_reloc.
	(elf_i386_copy_indirect_symbol): Copy has_got_reloc and
	has_non_got_reloc.
	(elf_i386_check_relocs): Set has_got_reloc and has_non_got_reloc.
	(elf_i386_fixup_symbol): New function.
	(elf_i386_pie_finish_undefweak_symbol): Likewise.
	(elf_i386_allocate_dynrelocs): Don't allocate space for dynamic
	relocations and discard relocations against resolved undefined
	weak symbols in executable.  Don't make resolved undefined weak
	symbols in executable dynamic.  Keep dynamic non-GOT/non-PLT
	relocation against undefined weak symbols in PIE.
	(elf_i386_size_dynamic_sections): Set interp to .interp section.
	(elf_i386_relocate_section): Don't generate dynamic relocations
	against resolved undefined weak symbols in PIE, except for
	R_386_PC32.
	(elf_i386_finish_dynamic_symbol): Keep PLT/GOT entries without
	dynamic PLT/GOT relocations for resolved undefined weak symbols.
	Don't generate dynamic relocation against resolved undefined weak
	symbol in executable.
	(elf_i386_finish_dynamic_sections): Call
	elf_i386_pie_finish_undefweak_symbol on all symbols in PIE.
	(elf_backend_fixup_symbol): New.
	* elf64-x86-64.c (UNDEFINED_WEAK_RESOLVED_TO_ZERO): New.
	(elf_x86_64_link_hash_entry): Add has_got_reloc and
	has_non_got_reloc.
	(elf_x86_64_link_hash_table): Add interp.
	(elf_x86_64_link_hash_newfunc): Initialize has_got_reloc and
	has_non_got_reloc.
	(elf_x86_64_copy_indirect_symbol): Copy has_got_reloc and
	has_non_got_reloc.
	(elf_x86_64_check_relocs): Set has_got_reloc and
	has_non_got_reloc.
	(elf_x86_64_fixup_symbol): New function.
	(elf_x86_64_pie_finish_undefweak_symbol): Likewise.
	(elf_x86_64_allocate_dynrelocs): Don't allocate space for dynamic
	relocations and discard relocations against resolved undefined
	weak symbols in executable.  Don't make resolved undefined weak
	symbols in executable dynamic.
	(elf_x86_64_size_dynamic_sections): Set interp to .interp section.
	(elf_x86_64_relocate_section): Check relocation overflow for
	dynamic relocations against unresolved weak undefined symbols.
	Don't generate dynamic relocations against resolved weak
	undefined symbols in PIE.
	(elf_x86_64_finish_dynamic_symbol): Keep PLT/GOT entries without
	dynamic PLT/GOT relocations for resolved undefined weak symbols.
	Don't generate dynamic relocation against resolved undefined weak
	symbol in executable.
	(elf_x86_64_finish_dynamic_sections): Call
	elf_x86_64_pie_finish_undefweak_symbol on all symbols in PIE.
	(elf_backend_fixup_symbol): New.

include/

	PR ld/19636
	PR ld/19704
	PR ld/19719
	* bfdlink.h (bfd_link_info): Add dynamic_undefined_weak.

ld/

	PR ld/19636
	PR ld/19704
	PR ld/19719
	* Makefile.am (ELF_X86_DEPS): Add dynamic_undefined_weak.sh.
	* Makefile.in: Regenerated.
	* NEWS: Mention -z nodynamic-undefined-weak.
	* ld.texinfo: Document -z nodynamic-undefined-weak.
	* ldmain.c (main): Initialize dynamic_undefined_weak to -1.
	* emulparams/dynamic_undefined_weak.sh: New file.
	* emulparams/elf32_x86_64.sh: Source dynamic_undefined_weak.sh.
	* emulparams/elf_i386.sh: Likewise.
	* emulparams/elf_i386_be.sh: Likewise.
	* emulparams/elf_i386_chaos.sh: Likewise.
	* emulparams/elf_i386_ldso.sh: Likewise.
	* emulparams/elf_i386_vxworks.sh: Likewise.
	* emulparams/elf_iamcu.sh: Likewise.
	* emulparams/elf_k1om.sh: Likewise.
	* emulparams/elf_l1om.sh: Likewise.
	* emulparams/elf_x86_64.sh: Likewise.
	* emulparams/extern_protected_data.sh (PARSE_AND_LIST_OPTIONS):
	Append.
	(PARSE_AND_LIST_ARGS_CASE_Z): Likewise.
	* testsuite/ld-elf/pr19719a.c: New file.
	* testsuite/ld-elf/pr19719b.c: Likewise.
	* testsuite/ld-elf/pr19719c.c: Likewise.
	* testsuite/ld-elf/pr19719d.c: Likewise.
	* testsuite/ld-i386/pr19636-1.s: Likewise.
	* testsuite/ld-i386/pr19636-1a.d: Likewise.
	* testsuite/ld-i386/pr19636-1b.d: Likewise.
	* testsuite/ld-i386/pr19636-1c.d: Likewise.
	* testsuite/ld-i386/pr19636-1d-nacl.d: Likewise.
	* testsuite/ld-i386/pr19636-1d.d: Likewise.
	* testsuite/ld-i386/pr19636-1e.d: Likewise.
	* testsuite/ld-i386/pr19636-1f.d: Likewise.
	* testsuite/ld-i386/pr19636-1g.d: Likewise.
	* testsuite/ld-i386/pr19636-1h.d: Likewise.
	* testsuite/ld-i386/pr19636-1i.d: Likewise.
	* testsuite/ld-i386/pr19636-2.s: Likewise.
	* testsuite/ld-i386/pr19636-2a.d: Likewise.
	* testsuite/ld-i386/pr19636-2b.d: Likewise.
	* testsuite/ld-i386/pr19636-2c-nacl.d: Likewise.
	* testsuite/ld-i386/pr19636-2c.d: Likewise.
	* testsuite/ld-i386/pr19636-2d-nacl.d: Likewise.
	* testsuite/ld-i386/pr19636-2d.d: Likewise.
	* testsuite/ld-i386/pr19636-2e-nacl.d: Likewise.
	* testsuite/ld-i386/pr19636-2e.d: Likewise.
	* testsuite/ld-i386/pr19636-3.s: Likewise.
	* testsuite/ld-i386/pr19636-3a.d: Likewise.
	* testsuite/ld-i386/pr19636-3b.d: Likewise.
	* testsuite/ld-i386/pr19636-3c.d: Likewise.
	* testsuite/ld-i386/pr19636-3d.d: Likewise.
	* testsuite/ld-i386/pr19636-3e.d: Likewise.
	* testsuite/ld-i386/pr19636-3f.d: Likewise.
	* testsuite/ld-i386/pr19636-3g.d: Likewise.
	* testsuite/ld-i386/pr19636-4.s: Likewise.
	* testsuite/ld-i386/pr19636-4a.d: Likewise.
	* testsuite/ld-i386/pr19636-4b.d: Likewise.
	* testsuite/ld-i386/pr19636-4c.d: Likewise.
	* testsuite/ld-i386/pr19636-4d.d: Likewise.
	* testsuite/ld-i386/pr19704.out: Likewise.
	* testsuite/ld-i386/pr19704a.c: Likewise.
	* testsuite/ld-i386/pr19704b.c: Likewise.
	* testsuite/ld-x86-64/pr19636-1.s: Likewise.
	* testsuite/ld-x86-64/pr19636-1a.d: Likewise.
	* testsuite/ld-x86-64/pr19636-1b.d: Likewise.
	* testsuite/ld-x86-64/pr19636-1c.d: Likewise.
	* testsuite/ld-x86-64/pr19636-1d.d: Likewise.
	* testsuite/ld-x86-64/pr19636-1e.d: Likewise.
	* testsuite/ld-x86-64/pr19636-1f.d: Likewise.
	* testsuite/ld-x86-64/pr19636-1g.d: Likewise.
	* testsuite/ld-x86-64/pr19636-2.s: Likewise.
	* testsuite/ld-x86-64/pr19636-2a.d: Likewise.
	* testsuite/ld-x86-64/pr19636-2b.d: Likewise.
	* testsuite/ld-x86-64/pr19636-2c.d: Likewise.
	* testsuite/ld-x86-64/pr19636-2d-nacl.d: Likewise.
	* testsuite/ld-x86-64/pr19636-2d.d: Likewise.
	* testsuite/ld-x86-64/pr19636-2e.d: Likewise.
	* testsuite/ld-x86-64/pr19636-2f.d: Likewise.
	* testsuite/ld-x86-64/pr19636-2g.d: Likewise.
	* testsuite/ld-x86-64/pr19636-2h.d: Likewise.
	* testsuite/ld-x86-64/pr19636-2i.d: Likewise.
	* testsuite/ld-x86-64/pr19636-3.s: Likewise.
	* testsuite/ld-x86-64/pr19636-3a.d: Likewise.
	* testsuite/ld-x86-64/pr19636-3b.d: Likewise.
	* testsuite/ld-x86-64/pr19636-3c.d: Likewise.
	* testsuite/ld-x86-64/pr19636-3d.d: Likewise.
	* testsuite/ld-x86-64/pr19704.out: Likewise.
	* testsuite/ld-x86-64/pr19704a.c: Likewise.
	* testsuite/ld-x86-64/pr19704b.c: Likewise.
	* testsuite/ld-elf/shared.exp (mix_pic_and_non_pic): New.
	Run mix_pic_and_non_pic.
	* testsuite/ld-i386/i386.exp (undefined_weak): New.
	Run undefined_weak and PR ld/19636 tests.
	* testsuite/ld-x86-64/x86-64.exp: Likewise.
	* testsuite/ld-x86-64/pr13082-3b.d: Updated.
	* testsuite/ld-x86-64/pr13082-4b.d: Likewise.
2016-02-26 04:55:57 -08:00
Jiong Wang
b8ec4e871e [ARM] Add FP16 feature extension for ARMv8.2 architecture
include/
  * opcode/arm.h (ARM_EXT2_FP16_INSN): New.

gas/
  * config/tc-arm.c (arm_ext_fp16): New.
  (arm_extensions): New entry for "fp16".
2016-02-19 14:27:23 +00:00
Claudiu Zissulescu
4670103e86 Add support for ARC instruction relaxation in the assembler.
gas/
2016-01-26  Claudiu Zissulescu  <claziss@synopsys.com>
	    Janek van Oirschot <jvanoirs@synopsys.com>

        * config/tc-arc.h (TC_FRAG_TYPE, TC_PCREL_ADJUST, MAX_INSN_ARGS)
        (MAX_INSN_FLGS, MAX_FLAG_NAME_LENGHT, TC_GENERIC_RELAX_TABLE):
        Define.
        (arc_flags, arc_relax_type): New structure.
        * config/tc-arc.c (FRAG_MAX_GROWTH, RELAX_TABLE_ENTRY)
	(RELAX_TABLE_ENTRY_MAX): New define.
        (relaxation_state, md_relax_table, arc_relaxable_insns)
	(arc_num_relaxable_ins): New variable.
	(rlx_operand_type, arc_rlx_types): New enums.
	(arc_relaxable_ins): New structure.
        (OPTION_RELAX): New option.
        (arc_insn): New relax member.
        (arc_flags): Remove.
        (relax_insn_p): New function.
        (apply_fixups): Likewise.
        (relaxable_operand): Likewise.
        (may_relax_expr): Likewise.
        (relaxable_flag): Likewise.
        (arc_pcrel_adjust): Likewise.
        (md_estimate_size_before_relax): Implement.
        (md_convert_frag): Likewise.
        (md_parse_option): Handle new mrelax option.
        (md_show_usage): Likewise.
        (assemble_insn): Set relax member.
        (emit_insn0): New function.
        (emit_insn1): Likewise.
        (emit_insn): Handle relaxation case.
	* NEWS: Mention the new relaxation option.
	* doc/c-arc.texi (ARC Options): Document new mrelax option.

gas/testsuite
2016-01-26  Claudiu Zissulescu  <claziss@synopsys.com>

        * gas/arc/relax-avoid1.d: New file.
        * gas/arc/relax-avoid1.s: Likewise.
        * gas/arc/relax-avoid2.d: Likewise.
        * gas/arc/relax-avoid2.s: Likewise.
        * gas/arc/relax-avoid3.d: Likewise.
        * gas/arc/relax-avoid3.s: Likewise.
	* gas/arc/relax-b.d: Likewise.
        * gas/arc/relax-b.s: Likewise.

include/opcode/
2016-01-26  Claudiu Zissulescu  <claziss@synopsys.com>
	    Janek van Oirschot  <jvanoirs@synopsys.com>

        * arc.h (arc_opcode arc_relax_opcodes, arc_num_relax_opcodes):
        Declare.

opcodes/
2016-01-26  Claudiu Zissulescu  <claziss@synopsys.com>
	    Janek van Oirschot  <jvanoirs@synopsys.com>

        * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
        variable.
2016-02-10 12:09:01 +00:00
Nick Clifton
609332f15c Fix compile time warnings building the binutils with a gcc6 compiler.
include	* opcode/metag.h (metag_scondtab): Mark as possibly unused.
	* opcode/nds32.h (nds32_r45map): Likewise.
	(nds32_r54map): Likewise.
	* opcode/visium.h (gen_reg_table): Likewise.
	(fp_reg_table, cc_table, opcode_table): Likewise.

bfd	* oasys.c (oasys_archive_p): Fix indentation.
	* elf32-nds32.c (nds32_elf_relax_section): Use an unsigned
	constant for left shifting.
2016-02-09 16:34:24 +00:00
Alan Modra
24f5f69a8a Fix macro redefinition error on Solaris
PR 16583
	* elf/common.h (AT_SUN_HWCAP): Undef before defining.
2016-02-09 13:11:16 +10:30
Nick Clifton
c1d9289fef Fix the encoding of the MSP430's RRUX instruction.
PR target/19561
opcdoe	* msp430-dis.c (print_insn_msp430): Add a special case for
	decoding an RRC instruction with the ZC bit set in the extension
	word.

include	* opcode/msp430.h (IGNORE_CARRY_BIT): New define.
	(RRUX): Synthesise using case 2 rather than 7.

gas	* config/tc-msp430.c (msp430_operands): Remove case 7.  Use case 2
	to handle encoding of RRUX instruction.
	* testsuite/gas/msp430/msp430x.s: Add more tests of the extended
	shift instructions.
	* testsuite/gas/msp430/msp430x.d: Update expected disassembly.
2016-02-04 09:55:10 +00:00
John Baldwin
f4ddf30f11 Add support to readelf for reading FreeBSD ELF core notes.
binutils/ChangeLog:

	* readelf.c (get_freebsd_elfcore_note_type): New
	(process_note): Add support for FreeBSD core notes.

include/ChangeLog:

	* elf/common.h (NT_FREEBSD_THRMISC): Define.
	(NT_FREEBSD_PROCSTAT_PROC): Define.
	(NT_FREEBSD_PROCSTAT_FILES): Define.
	(NT_FREEBSD_PROCSTAT_VMMAP): Define.
	(NT_FREEBSD_PROCSTAT_GROUPS): Define.
	(NT_FREEBSD_PROCSTAT_UMASK): Define.
	(NT_FREEBSD_PROCSTAT_RLIMIT): Define.
	(NT_FREEBSD_PROCSTAT_OSREL): Define.
	(NT_FREEBSD_PROCSTAT_PSSTRINGS): Define.
	(NT_FREEBSD_PROCSTAT_AUXV): Define.
2016-01-19 08:15:08 -08:00
Miranda Cupertino
34e967a5f3 Add PIC and TLS support to the ARC target.
bfd/ChangeLog:
	* arc-plt.def: New file.
	* arc-plt.h: Likewise.
	* elf32-arc.c (elf_arc_abs_plt0_entry, elf_arc_abs_pltn_entry,
		       elf_arcV2_abs_plt0_entry, elf_arcV2_abs_pltn_entry,
		       elf_arc_pic_plt0_entry, elf_arc_pic_pltn_entry,
		       elf_arcV2_pic_plt0_entry, elf_arcV2_pic_pltn_entry): Remove.
	(name_for_global_symbol): Added.
	(ADD_RELA): Helper to create dynamic relocs.
	(new_got_entry_to_list): Create a new got entry in linked list.
	(symbol_has_entry_of_type): Search for specific type of entry in
	list.
	(is_reloc_for_GOT): return FALSE for any TLS related relocs.
	(is_reloc_for_TLS, arc_elf_set_private_flags)
	(arc_elf_print_private_bfd_data, arc_elf_copy_private_bfd_data)
	(arc_elf_merge_private_bfd_data): New functions.
	(debug_arc_reloc): Cleaned debug info printing.
	(PDATA reloc): Changed not to perform address alignment.
	(reverse_me): Added. Fix for ARC_32 relocs.
	(arc_do_relocation): Return bfd_reloc_of when no relocation should
	occur.
	(arc_get_local_got_ents): Renamed from arc_get_local_got_offsets.
	Changed function to access an array of list of GOT entries instead
	of just an array of offsets.
	(elf_arc_relocate_section): Added support for PIC and TLS related relocations.
	(elf_arc_check_relocs): Likewise.
	(elf_arc_adjust_dynamic_symbol, elf_arc_finish_dynamic_symbol,
	(elf_arc_finish_dynamic_sections): Likewise
	(arc_create_dynamic_sections): Modified conditions to create
	dynamic sections.
	(ADD_SYMBOL_REF_SEC_AND_RELOC): New macro.
	(plt_do_relocs_for_symbol, relocate_plt_for_symbol)
	(relocate_plt_for_entry): Changed to support new way to define PLT
	related code.
	(add_symbol_to_plt): Likewise.
	(arc_elf_link_hash_table_create): New function.

include/ChangeLog:
	* elf/arc-reloc.def (ARC_32, ARC_GOTPC, ARC_TLS_GD_GOT)
	(ARC_TLS_IE_GOT, ARC_TLS_DTPOFF, ARC_TLS_DTPOFF_S9, ARC_TLS_LE_S9)
	(ARC_TLS_LE_32): Fixed formula.
	(ARC_TLS_GD_LD): Use new special function.
	* opcode/arc-func.h: Changed all the replacement
	functions to clear the patching bits before doing an or it with the value
	argument.
2016-01-19 15:25:58 +00:00
Nick Clifton
9ae678af99 Use a 32-bit value to hold the section number in the internal COFF symbol structure.
PR ld/19440
inc	* coff/internal.h (internal_syment): Use int to hold section
	number.
	(N_UNDEF): Cast to int not short.
	(N_ABS): Likewise.
	(N_DEBUG): Likewise.
	(N_TV): Likewise.
	(P_TV): Likewise.

bfd	PR ld/19440
	* coff-rs6000.c (_bfd_xcoff_swap_sym_in): Sign extend external
	section number into internal section number.
	* coff64-rs6000.c (_bfd_xcoff64_swap_sym_in): Likewise.
	* coffswap.h (coff_swap_sym_in): Likewise.
	* peXXigen.c (_bfd_XXi_swap_sym_in): Likewise.
	* coffcode.h (_coff_bigobj_swap_sym_in): Make sure that internal
	section number field is big enough to hold the external value.
2016-01-18 15:58:47 +00:00
Nick Clifton
4849dfd8f4 Import changes made to files shared with the FSF GCC project.
Import the following changes from the GCC mainline:

	2015-11-13  Tsvetkova Alexandra  <aleksandra.tsvetkova@intel.com>

	* configure.ac: Enable libmpx by default.
	* configure: Regenerated.

	2015-11-19  Martin Liska  <mliska@suse.cz>

	* .gitignore: Add .clang-format to ignored files.
	* Makefile.tpl: Add clang-format.
	* Makefile.in: Regenerate.

	2015-12-01  Andreas Tobler  <andreast@gcc.gnu.org>

	PR libffi/65726
	* Makefile.def (lang_env_dependencies): Make libffi depend
	on cxx.
	* Makefile.in: Regenerate.

	2015-12-02  Ian Lance Taylor  <iant@google.com>

	PR go/66147
	* Makefile.tpl (HOST_EXPORTS): Add XGCC_FLAGS_FOR_TARGET.
	* Makefile.in: Regenerate.

	2015-12-17  Nathan Sidwell  <nathan@acm.org>

	* config/isl.m4 (ISL_CHECK_VERSION): Add gmp libs.
	* configure: Regenerate.

	2015-12-17  Sebastian Pop  <s.pop@samsung.com>

	* Makefile.in: Replace ISL with isl.
	* Makefile.tpl: Same.
	* config/isl.m4: Same.
	* configure.ac: Same.
	* contrib/download_prerequisites: Same.
	* configure: Regenerate.

	2016-01-01  Ben Elliston  <bje@gnu.org>

	* config.guess: Import version 2016-01-01.
	* config.sub: Likewise.

include	2016-01-07  Mike Frysinger  <vapier@gentoo.org>

	* longlong.h: Change !__SHMEDIA__ to
	(!defined (__SHMEDIA__) || !__SHMEDIA__).
	Change __SHMEDIA__ to defined (__SHMEDIA__) && __SHMEDIA__.
2016-01-11 11:06:56 +00:00
Maciej W. Rozycki
b31e480331 MIPS/include: opcode/mips.h: Add a summary of MIPS16 operand codes
include/
	* opcode/mips.h: Add a summary of MIPS16 operand codes.
2016-01-06 18:37:58 +00:00
Mike Frysinger
b36c1ccb1f libiberty: {count,dup,write}argv: constify argv input slightly
Would be more useful if we could use "const char * const *", but there's
a long standing bug where gcc warns about incompatible pointers when you
try to pass in "char **".  We can at least constify the array itself as
gcc will not warn in that case.
2016-01-05 15:25:13 -05:00
Alan Modra
6f2750feaf Copyright update for binutils 2016-01-01 23:00:01 +10:30
Alan Modra
3499769a6a New 2016 binutils ChangeLog files
Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog
and include/*/ChangeLog files.
2016-01-01 22:59:42 +10:30
Alan Modra
4120fa118f binutils ChangeLog rotation 2016-01-01 22:59:17 +10:30
Alan Modra
331e61312e Fix assorted ChangeLog errors 2015-12-30 11:44:35 +10:30
Mickael Guene
ac4c9b0459 Add support for ARM's NOREAD section flag.
include/elf
     * arm.h: Add arm SHF_ARM_NOREAD section flag.

bfd  * bfd-in2.h: Regenerate.
     * section.c: Add SEC_ELF_NOREAD.
     * elf32-arm.c (elf32_arm_post_process_headers): Only set
     PF_X attribute if a segment only contains section with
     SHF_ARM_NOREAD flag.
     (elf32_arm_fake_sections): Add SEC_ELF_NOREAD conversion.
     (elf32_arm_section_flags): New function to convert SHF_ARM_NOREAD
     to bfd flag.
     (elf32_arm_lookup_section_flags): New function to allow
     INPUT_SECTION_FLAGS directive with SHF_ARM_NOREAD flag.
     (elf32_arm_special_sections): Add special sections array
     to catch section prefix by '.text.noread' pattern.

ld/testsuite
     * ld-arm/arm-elf.exp: New tests.
     * ld-arm/thumb1-input-section-flag-match.d: New
     * ld-arm/thumb1-input-section-flag-match.s: New
     * ld-arm/thumb1-noread-not-present-mixing-two-section.d: New
     * ld-arm/thumb1-noread-not-present-mixing-two-section.s: New
     * ld-arm/thumb1-noread-present-one-section.d: New
     * ld-arm/thumb1-noread-present-one-section.s: New
     * ld-arm/thumb1-noread-present-two-section.d: New
     * ld-arm/thumb1-noread-present-two-section.s: New

binutils
	* readelf.c (get_elf_section_flags): Add support for ARM specific
	section flags.
2015-12-22 14:12:35 +00:00
Christophe Lyon
0bef041426 Add forgotten ChangeLog updates for 72d98d16ed:
2015-12-16  Mickael Guene <mickael.guene@st.com>

	bfd/
	* bfd-in2.h: Regenerate.
	* reloc.c: Add new relocations.
	* libbfd.h (bfd_reloc_code_real_names): Add new relocations
	display names.
	* elf32-arm.c (elf32_arm_howto_table_1): Add HOWTO for new
	relocations.
	(elf32_arm_reloc_map): Add bfd/arm mapping for new relocations.
	(elf32_arm_final_link_relocate): Implement new relocations
	resolution.

	gas/
	* doc/c-arm.texi: Add documentation about new directives
	* config/tc-arm.c (group_reloc_table): Add mapping between gas
	syntax and new relocations.
	(do_t_add_sub): Keep new relocations for add operand.
	(do_t_mov_cmp): Keep new relocations for mov operand.
	(insns): Use 'shifter operand with possible group relocation'
	operand parse code for movs operand.
	(md_apply_fix): Implement mov and add encoding when new
	relocations on them.
	(tc_gen_reloc): Add new relocations.
	(arm_fix_adjustable): Since offset has a limited range ([0:255])
	we disable adjust_reloc_syms() for new relocations.

	gas/testsuite/
	* gas/arm/adds-thumb1-reloc-local.d: New
	* gas/arm/adds-thumb1-reloc-local.s: New
	* gas/arm/movs-thumb1-reloc-local.d: New
	* gas/arm/movs-thumb1-reloc-local.s: New

	include/
	* elf/arm.h: Add new arm relocations.

	ld/testsuite/
	* ld-arm/arm-elf.exp (armelftests_common): Add new relocations
	tests.
	* ld-arm/thumb1-adds.d: New
	* ld-arm/thumb1-adds.s: New
	* ld-arm/thumb1-movs.d: New
	* ld-arm/thumb1-movs.s: New
2015-12-17 11:14:37 +01:00
Alan Modra
bbb1afc89b Invoke aout N_* macros with pointer to struct internal_exec
No functional changes here.

BTW, some of these headers don't seem to be used anywhere:
include/aout/dynix3.h, include/aout/encap.h, include/aout/hp.h,
gas/config/aout_gnu.h

bfd/
	* aout-adobe.c: Invoke aout N_* macros with pointer to
	struct internal_exec.
	* aout-arm.c: Likewise.
	* aout-cris.c: Likewise.
	* aout-target.h: Likewise.
	* aout-tic30.c: Likewise.
	* aoutf1.h: Likewise.
	* aoutx.h: Likewise.
	* bout.c: Likewise.
	* freebsd.h: Likewise.
	* gen-aout.c: Likewise.
	* hp300hpux.c: Likewise.
	* i386aout.c: Likewise.
	* i386linux.c: Likewise.
	* i386lynx.c: Likewise.
	* i386mach3.c: Likewise.
	* i386os9k.c: Likewise.
	* libaout.h: Likewise.
	* m68klinux.c: Likewise.
	* m88kmach3.c: Likewise.
	* mipsbsd.c: Likewise.
	* netbsd.h: Likewise.
	* pc532-mach.c: Likewise.
	* pdp11.c: Likewise.
	* riscix.c: Likewise.
	* sparclinux.c: Likewise.
	* sparclynx.c: Likewise.
gas/
	* config/aout_gnu.h: Invoke aout N_* macros with pointer to
	struct internal_exec.
include/
	* bout.h: Invoke aout N_* macros with pointer to
	struct internal_exec.
	* os9k.h: Likewise.
include/aout/
	* adobe.h: Invoke aout N_* macros with pointer to
	struct internal_exec.
	* aout64.h: Likewise.
	* dynix3.h: Likewise.
	* encap.h: Likewise.
	* hp.h: Likewise.
	* hp300hpux.h: Likewise.
	* sun4.h: Likewise.
2015-12-01 13:40:05 +10:30
Rainer Orth
87746c154a Port libvtv to Solaris
libstdc++-v3:
	* acinclude.m4 (GLIBCXX_ENABLE_VTABLE_VERIFY) <solaris2*>: Use
	-Wl,-R in VTV_CXXLINKFLAGS.
	* configure: Regenerate.

	* testsuite/18_support/bad_exception/23591_thread-1.c: Use
	-fvtable-verify=none on Solaris 12+.

	libgcc:
	* Makefile.in (VTV_CFLAGS): New variable.
	(vtv_start$(objext), vtv_end$(objext), vtv_end$(objext))
	(vtv_start_preinit$(objext), vtv_end_preinit$(objext)): Use it.
	* config.host (*-*-solaris2*): Add t-crtstuff-pic to tmake_file.
	Add vtv_start.o, vtv_end.o, vtv_start_preinit.o, vtv_end_preinit.o
	to extra_parts if $enable_vtable_verify = yes.

	libvtv:
	* configure.tgt (*-*-solaris2.[1-9]*): Declare supported.
	* configure.ac: Call AC_USE_SYSTEM_EXTENSIONS.
	<*-*-solaris2*>: Check for init priority support.
	Check for getexecname, __fortify_fail, _obstack_begin.
	(VTV_NO_OBSTACK): New conditional.
	* configure: Regenerate.
	* Makefile.am [VTV_NO_OBSTACK] (obstack.c): Use new condition.
	Create empty config.h
	* Makefile.in: Regenerate.

	* vtv_rts.cc [HAVE_GETEXECNAME] (program_invocation_name): New
	variable.
	(read_section_offset_and_length) [HAVE_GETEXECNAME]: Set it.
	(dl_iterate_phdr_callback) [HAVE_GETEXECNAME]: Set it.

	(__fortify_fail): Wrap in HAVE___FORTIFY_FAIL
	[!HAVE___FORTIFY_FAIL]: Provide non-Cygwin implementation.

	(read_section_offset_and_length): Assert sh_size >= VTV_PAGE_SIZE.
	(iterate_modules): Fix typo.
	Use VTV_PAGE_SIZE.
	(dl_iterate_phdr_callback): Fix typo.
	Use VTV_PAGE_SIZE.
	(__VLTChangePermission): Fix typos.

	include:
	* vtv-change-permission.h (VTV_PAGE_SIZE) [__sun__ && __svr4__ &&
	__sparc__]: Define.

	gcc:
	* config/sol2.h (SUPPORTS_INIT_PRIORITY): Move up.
	(STARTFILE_VTV_SPEC, ENDFILE_VTV_SPEC): Define.
	(STARTFILE_SPEC): Use %(startfile_vtv).
	(ENDFILE_SPEC): Use %(endfile_vtv).
	(SUBTARGET_EXTRA_SPECS): Handle STARTFILE_VTV_SPEC,
	ENDFILE_VTV_SPEC.

	* gcc.c (LINK_COMMAND_SPEC): Move VTABLE_VERIFICATION_SPEC after %{L*}.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@230865 138bc75d-0d04-0410-961f-82ee72b054a4
2015-11-28 16:39:32 +00:00
Rich Felker
f4936735c5 SH FDPIC backend support
gcc/ChangeLog
	* config.gcc: Handle --enable-fdpic.
	* config/sh/constraints.md (Ccl): New constraint.
	* config/sh/linux.h (SUBTARGET_LINK_EMUL_SUFFIX): Handle -mfdpic.
	* config/sh/sh-c.c (sh_cpu_cpp_builtins): Add __FDPIC__ and
	__SH_FDPIC__.
	* config/sh/sh-mem.cc (expand_block_move): Support FDPIC for calls
	to library functions.
	* config/sh/sh-protos.h (function_symbol_result): New struct.
	(function_symbol): Return function_symbol_result.
	(sh_get_fdpic_reg_initial_val, sh_load_function_descriptor): New
	declarations.
	* config/sh/sh.c (TARGET_ASM_INTEGER, sh_assemble_integer):
	Implement target hook.
 	(TARGET_CANNOT_FORCE_CONST_MEM, sh_cannot_force_const_mem_p):
	Likewise.
	(sh_option_override): Force -fPIC if FDPIC is in effect.
 	(sh_asm_output_addr_const_extra): Add UNSPEC_GOTFUNCDESC and
	UNSPEC_GOTOFFFUNCDESC cases.
	(prepare_move_operands): Use FDPIC initial GOT register for
	TLS-related GOT access; inhibit cross-section address offset
	constants for FDPIC.
	(sh_assemble_integer): New function.
	(sh_cannot_copy_insn_p): Inhibit copying insns that are FDPIC
	PC-relative call sites.
	(expand_ashiftrt): Adapt invocation of function_symbol.
	(sh_expand_prologue): Inhibit PC-relative GOT address load for
	FDPIC.
	(nonpic_symbol_mentioned_p): Add cases for UNSPEC_GOTFUNCDESC and
	UNSPEC_GOTOFFFUNCDESC.
	(legitimize_pic_address): Resolve function symbols to function
	descriptors for FDPIC.  Do not use GOT-relative addressing for
	local data that may be read-only on FDPIC.
	(sh_emit_storesi, sh_emit_storehi): New functions.
	(sh_trampoline_init): Generate FDPIC trampolines.
	(sh_function_ok_for_sibcall): Add TARGET_FDPIC check.
	(sh_expand_sym_label2reg): Don't assume sibcalls are local.
	(sh_output_mi_thunk): Generate FDPIC call.
	(function_symbol): Return function_symbol_result.  For
	SFUNC_STATIC on FDPIC, generate call site labels to use
	PC-relative addressing rather than GOT-relative addressing.
	(sh_conditional_register_usage): Make PIC register fixed and call used
	when FDPIC is in effect.
	(sh_legitimate_constant_p): Impose FDPIC
	constant constraints.
	(sh_cannot_force_const_mem_p, sh_load_function_descriptor)
	(sh_get_fdpic_reg_initial_val): New functions.
	* config/sh/sh.h (SUBTARGET_ASM_SPEC, SUBTARGET_LINK_EMUL_SUFFIX):
	Handle -mfdpic.
	(FDPIC_SELF_SPECS, SUBTARGET_DRIVER_SELF_SPECS)
	(PIC_OFFSET_TABLE_REG_CALL_CLOBBERED)
	(SH_OFFSETS_MUST_BE_WITHIN_SECTIONS_P): New macros.
	(DRIVER_SELF_SPECS): Add SUBTARGET_DRIVER_SELF_SPECS and
	FDPIC_SELF_SPECS.
	(TRAMPOLINE_SIZE): Select trampoline size for FDPIC.
	(ASM_PREFERRED_EH_DATA_FORMAT): Add EH format constraints for
	FDPIC.
	(ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX): Handle FDPIC case.
	* config/sh/sh.md (UNSPEC_GOTFUNCDESC, UNSPEC_GOTOFFFUNCDESC): New
	constants.
	(calli_fdpic, call_valuei_fdpic, sibcalli_fdpic)
	(sibcalli_pcrel_fdpic, sibcall_pcrel_fdpic, sibcall_valuei_fdpic)
	(sibcall_valuei_pcrel_fdpic, sibcall_value_pcrel_fdpic)
	(sym2GOTFUNCDESC, symGOTFUNCDESC2reg, sym2GOTOFFFUNCDESC)
	(symGOTOFFFUNCDESC2reg): New patterns.
	(udivsi3_i1, udivsi3_i4, udivsi3_i4_single, udivsi3,
	*divsi_inv_call_combine, divsi3_i4, divsi3_i4_single, divsi3)
	(ashlsi3, ashlsi3_d_call, ashrsi3_n, lshrsi3, lshrsi3_d_call)
	(calli, call_valuei, call, call_value, sibcalli, sibcalli_pcrel)
	(sibcall_pcrel, sibcall, sibcall_valuei, sibcall_valuei_pcrel)
	(sibcall_value_pcrel, sibcall_value, GOTaddr2picreg, symGOT_load)
	(symGOTOFF2reg, block_move_real, block_lump_real)
	(block_move_real_i4, block_lump_real_i4): Add support for FDPIC
	calls.
	(mulsi3, ic_invalidate_line, initialize_trampoline, call_pop,
	call_value_pop): Adjust for new function_symbol signature.
	* config/sh/sh.opt (-mfdpic): New option.
	* doc/install.texi (Options specification): Document
	--enable-fdpic.
	* doc/invoke.texi (SH Options): Document -mfdpic.

include/ChangeLog:
	* longlong.h (udiv_qrnnd): Add FDPIC compatible version for SH.

libitm/ChangeLog:
	* config/sh/sjlj.S (_ITM_beginTransaction): Bypass PLT calling
	GTM_begin_transaction for compatibility with FDPIC.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@229438 138bc75d-0d04-0410-961f-82ee72b054a4
2015-11-28 16:39:31 +00:00
Iain Sandoe
35a88fa501 Fix PR63758 by using the _NSGetEnviron() API on Darwin
include/

	Roland McGrath  <roland@gnu.org>

	PR other/63758
	* environ.h: New file.

libiberty/

	Roland McGrath  <roland@gnu.org>
	Iain Sandoe  <iain@codesourcery.com>

	PR other/63758
	* pex-unix.c: Obtain the environment interface from settings in environ.h
	rather than in-line code.  Update copyright date.
	* setenv.c: Likewise.
	* xmalloc.c: Likewise.




git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@228942 138bc75d-0d04-0410-961f-82ee72b054a4
2015-11-28 16:39:30 +00:00
Alan Modra
e9f40d7d68 Modify obstack.[hc] to avoid having to include other gnulib files
Using the standard gnulib obstack source requires importing quite a
lot of other files from gnulib, and requires build changes.

include/
	PR gdb/17133
	* obstack.h (__attribute_pure__): Expand _GL_ATTRIBUTE_PURE.
libiberty/
	PR gdb/17133
	* obstack.c (__alignof__): Expand alignof_type from alignof.h.
	(obstack_exit_failure): Don't use exitfail.h.
	(_): Include libintl.h when HAVE_LIBINTL_H and nls enabled.
	Provide default.  Don't include gettext.h.
	(_Noreturn): Define.
	* obstacks.texi: Adjust node references to external libc info files.
2015-11-09 15:18:35 +10:30
Alan Modra
314dee8ea9 Copy gnulib obstack files
This copies obstack.[ch] from gnulib, and updates the docs.  The next
patch should be applied if someone repeats the import at a later date.

include/
	PR gdb/17133
	* obstack.h: Import current gnulib file.
libiberty/
	PR gdb/17133
	* obstack.c: Import current gnulib file.
	* obstacks.texi: Updated doc, from glibc's manual/memory.texi.
2015-11-09 15:12:45 +10:30
H.J. Lu
caa65211bb Add "-z call-nop=PADDING" option to ld
The ld linker can transform indirect call to a locally defined function,
foo, via its GOT slot, to either "NOP call foo" or "call foo NOP" where
NOP is a 1-byte NOP padding.  This patch adds a "-z call-nop=PADDING"
option to x86 ld to control 1-byte NOP padding for x86 call instruction.
PADDING is one of prefix-addr, prefix-nop, suffix-nop, prefix-NUMBER or
suffix-NUMBER.

bfd/

	* elf32-i386.c (elf_i386_convert_load): Use call_nop_byte and
	check call_nop_as_suffix for 1-byte NOP padding to pad call.
	* elf64-x86-64.c (elf_x86_64_convert_load): Likewise.

include/

	* bfdlink.h (bfd_link_info): Add call_nop_as_suffix and
	call_nop_byte.

ld/

	* ld/ld.texinfo: Document "-z call-nop=PADDING" option.
	* emulparams/call_nop.sh: New file.
	* emulparams/elf_i386_be.sh: Source
	${srcdir}/emulparams/call_nop.sh.
	* emulparams/elf_i386_chaos.sh: Likewise.
	* emulparams/elf_i386_ldso.sh: Likewise.
	* emulparams/elf_i386_vxworks.sh: Likewise.
	* emulparams/elf_iamcu.sh: Likewise.
	* emulparams/elf_k1om.sh: Likewise.
	* emulparams/elf_l1om.sh: Likewise.
	* emulparams/elf_x86_64.sh: Likewise.
	* emultempl/elf32.em (gld${EMULATION_NAME}_before_parse): Set
	link_info.call_nop_byte if $CALL_NOP_BYTE isn't empty.

ld/testsuite/

	* ld-i386/call3.s: New file.
	* ld-i386/call3a.d: Likewise.
	* ld-i386/call3b.d: Likewise.
	* ld-i386/call3c.d: Likewise.
	* ld-i386/call3d.d: Likewise.
	* ld-i386/call3e.d: Likewise.
	* ld-i386/call3f.d: Likewise.
	* ld-i386/call3g.d: Likewise.
	* ld-i386/call3h.d: Likewise.
	* ld-i386/load1-nacl.d: Likewise.
	* ld-x86-64/call1.s: Likewise.
	* ld-x86-64/call1a.d: Likewise.
	* ld-x86-64/call1b.d: Likewise.
	* ld-x86-64/call1c.d: Likewise.
	* ld-x86-64/call1d.d: Likewise.
	* ld-x86-64/call1e.d: Likewise.
	* ld-x86-64/call1f.d: Likewise.
	* ld-x86-64/call1g.d: Likewise.
	* ld-x86-64/call1h.d: Likewise.
	* ld-x86-64/call1i.d: Likewise.
	* ld-x86-64/load1a-nacl.d: Likewise.
	* ld-x86-64/load1b-nacl.d: Likewise.
	* ld-x86-64/load1c-nacl.d: Likewise.
	* ld-x86-64/load1d-nacl.d: Likewise.
2015-10-22 04:56:39 -07:00
Nick Clifton
886a250647 New ARC implementation.
bfd	* archures.c: Remove support for older ARC. Added support for new
	ARC cpus (ARC600, ARC601, ARC700, ARCV2).
	* bfd-in2.h: Likewise.
	* config.bfd: Likewise.
	* cpu-arc.c: Likewise.
	* elf32-arc.c: Totally changed file with a refactored
	inplementation of the ARC port.
	* libbfd.h: Added ARC specific relocation types.
	* reloc.c: Likewise.

gas     * config/tc-arc.c: Revamped file for ARC support.
        * config/tc-arc.h: Likewise.
        * doc/as.texinfo: Add new ARC options.
        * doc/c-arc.texi: Likewise.

ld	* configure.tgt: Added target arc-*-elf* and arc*-*-linux-uclibc*.
	* emulparams/arcebelf_prof.sh: New file
	* emulparams/arcebelf.sh: Likewise.
	* emulparams/arceblinux_prof.sh: Likewise.
	* emulparams/arceblinux.sh: Likewise.
	* emulparams/arcelf_prof.sh: Likewise.
	* emulparams/arcelf.sh: Likewise.
	* emulparams/arclinux_prof.sh: Likewise.
	* emulparams/arclinux.sh: Likewise.
	* emulparams/arcv2elfx.sh: Likewise.
	* emulparams/arcv2elf.sh: Likewise.
	* emultempl/arclinux.em: Likewise.
	* scripttempl/arclinux.sc: Likewise.
	* scripttempl/elfarc.sc: Likewise.
	* scripttempl/elfarcv2.sc: Likewise
	* Makefile.am: Add new ARC emulations.
	* Makefile.in: Regenerate.
	* NEWS: Mention the new feature.

opcodes * arc-dis.c: Revamped file for ARC support
	* arc-dis.h: Likewise.
	* arc-ext.c: Likewise.
	* arc-ext.h: Likewise.
	* arc-opc.c: Likewise.
	* arc-fxi.h: New file.
	* arc-regs.h: Likewise.
	* arc-tbl.h: Likewise.

binutils * readelf.c (get_machine_name): Remove A5 reference. Add ARCompact
	and ARCv2.
	(get_machine_flags): Handle EM_ARCV2 and EM_ARCOMPACT.
	(guess_is_rela): Likewise.
	(dump_relocations): Likewise.
	(is_32bit_abs_reloc): Likewise.
	(is_16bit_abs_reloc): Likewise.
	(is_none_reloc): Likewise.
	* NEWS: Mention the new feature.

include	* dis-asm.h (arc_get_disassembler): Correct declaration.
	* arc-reloc.def: Macro file with definition of all relocation
	types.
	* arc.h: Changed macros for the newly supported ARC cpus.  Altered
	enum defining the supported relocations.
	* common.h: Changed EM_ARC_A5 definition to EM_ARC_COMPACT. Added
	macro for EM_ARC_COMPACT2.
        * arc-func.h: New file.
        * arc.h: Likewise.
2015-10-07 14:20:19 +01:00
Nick Clifton
6899683948 Resync files in the binutils repository that are maintained in the gcc repository.
.	2015-08-23  Francois-Xavier Coudert  <fxcoudert@gcc.gnu.org>

	PR libfortran/54572
	* Makefile.def: Make libgfortran depend on libbacktrace.
	* Makefile.in: Regenerate.

	2015-08-12  Tom de Vries  <tom@codesourcery.com>

	PR other/67092
	PR other/67098
	* configure.ac: Remove --with_host_libstdcxx support.
	* configure: Regenerate.

	2015-08-10  Thomas Schwinge  <thomas@codesourcery.com>
	    Jakub Jelinek  <jakub@redhat.com>

	* configure.ac (noconfigdirs): Don't add "target-libgomp" for target
	nvptx*-*-*.
	* configure: Regenerate.

include	2015-08-14  Pierre-Marie de Rodat  <derodat@adacore.com>

	* dwarf2.def (DW_AT_GNU_bias): New attribute.

	2015-08-14  Pierre-Marie de Rodat  <derodat@adacore.com>

	* dwarf2.def (DW_AT_GNU_numerator, DW_AT_GNU_denominator): New
	attributes.

libiberty  2015-08-15  Ian Lance Taylor  <iant@google.com>

	* cp-demangle.c (d_abi_tags): Preserve di->last_name across any
	ABI tags.
2015-09-30 17:55:16 +01:00