regops.d, relocs1.d,
(relocs1.c): Add file for reference.
(relocs1b.d): Split reloc table contents test to different test file.
(relocs2.c): Add test that uses various types (char, short, int, ...) of
static and global variables with data shuffling to generate lots of ld/st
instructions for the different types.
(relocs2.d): New file, expected code for relocs2 test.
(relocs2.lst): New file, TI assembler listing for reference.
(relocs2.s): New file, assembly source for relocs2 test.
(relocs2b.d): New file, expected reloc table contents for relocs2 test.
(tic80.exp): Run the relocs1b, relocs2, and relocs2b tests.
* configure, configure.in: Move itbl-cpu.h to mips specific configure.
* itbl-ops.h: Include itbl-cpu.h only if HAVE_ITBL_CPU is defined.
* config/tc-mips.h: Define HAVE_ITBL_CPU.
* gas/mips/itbl.s: Add comments. Prefix register names with $.
* gas/all/itbl: Generic table for testing for itbl support.
* gas/all/itbl.s: Generic assembly for testing for itbl support.
* gas/mips/itbl-test.c: Moved to gas/all.
* gas/all/itbl-test.c: Moved from gas/mips.
Change mips_opcodes from const array to a pointer,
and change bfd_mips_num_opcodes from const int to int,
so that we can increase the size of the mips opcodes table
dynamically.
Change mips_opcodes from const array to a pointer,
and change bfd_mips_num_opcodes from const int to int,
so that we can increase the size of the mips opcodes table
dynamically.
* itbl-lex.l: Fix indentation mistakes from indent program.
* itbl-ops.h: Add include for ansidecl.h.
Add PARAMS around function arguments.
Add declaration for itbl_have_entries.
* itbl-ops.c: Add PARAMS around function arguments.
* Makefile.in: Add itbl build rules.
Add dependancies for itbl files to mips target.
* as.c: Add itbl support.
Add new option "--insttbl" for dynamically extending instruction set.
* as.h: Declare insttbl_file_name;
the name of file defining extensions to the basic instruction set
* configure.in, configure: Add itbl-parse.o, itbl-lex.o, and
itbl-ops.o to extra_objects for mips configuration.
Add include file link from itbl-cpu.h to
config/itbl-${target_cpu_type}.h.
* config/tc-mips.c: Allow copz instructions.
Add notes for future additions to the itbl support.
Add debug macros.
(macro): Call itbl_assemble to assemble itbl instructions.
See if an unknown register is specified in an itbl entry.
store BITNUM values in the table in one's complement form
to match behavior when assembler is given a raw numeric
value for a BITNUM operand.
* tic80-dis.c (print_operand_bitnum): Ditto.
description.
start-sanitize-tic80
* config/tc-tic80.h (NEED_FX_R_TYPE): Define.
* config/tc-tic80.c (find_opcode): Add code to support O_symbol
operands.
(build_insn): Grab a frag early so we can use the address in
fixups. Take one's complement of BITNUM values before insertion
in opcode. Add code to support O_symbol operands.
(md_apply_fix): Replace unimplemented warning with implementation.
(md_pcrel_from): Ditto.
(tc_coff_fix2rtype): Ditto.
end-sanitize-tic80
endmask.lst, regops.lst}: Remove ^M's from end of lines.
* gas/tic80/bitnum.s: Add comment to each line showing value
that symbolic BITNUM assembles to. Add coverage for raw
numeric values for the BITNUM operand.
* gas/tic80/bitnum.d: Update due to bitnum.s changes.
* gas/tic80/regops.d: Update due to opcode library additions
of floating point test BITNUM values that are ambiguous with
the integral ones.
* gas/tic80/relocs1.s: New test case that tests simple relocs.
* gas/tic80/relocs1.d: Expected output for above.
* gas/tic80/relocs1.lst: TI assembler listing for above.
* gas/tic80/tic80.exp: Add relocs1 test.
with template parameters containing `::'.
* valops.c (search_struct_field, search_struct_method):
Pass correct valaddr parameter to baseclass_offset.
Prevent gdb crashes by making sure that the virtual base pointer
from an user object still points to accessible memory.
somewhat.
(mn10200_elf_relax_section): Correctly compute a symbol's value
when the symbol is local, but not in the same section as we are
relaxing. Implement abs24 -> abs16, imm24 -> imm16 and d24 -> d16
relaxing.
Another 1.3% size reduction for hello world. Only relaxing left todo is
imm16 -> imm8 and d16 -> d8 where applicable.
Store lower 16 bits of addend in R_M32R_HI16_[SU]LO insns.
Add small data area support (R_M32R_SDA16).
* reloc.c: Document BFD_RELOC_M32R_SDA16.
* bfd-in2.h,libbfd.h: Regenerated.
These changes are related to Ian's gas/libgloss changes of Dec 13/Dec 18.
* tc-mips.c (mips_ip): If configured for an embedded ELF system,
don't set the section alignment to 2**4.
* mips/ddb.ld: Align the location counter before setting _gp, and
before setting edata. Remove ALIGN from _gp computation.
* mips/idt.ld, mips/pmon.ld: Before setting _gp, use ALIGN(8) instead
of ALIGN(16). Remove ALIGN from _gp computation.
(do_scrub_begin): Don't set lex['*'].
(do_scrub_chars): When handling LEX_IS_TWOCHAR_COMMENT_1ST, don't
check for LEX_IS_TWOCHAR_COMMENT_2ND. Instead, just check for
a literal '*'.
short conditional branch around a long unconditional branch.
Showing the reloc will allow the linker to shorten the long unconditional
branch or remove the long unconditional branch entirely when relaxing.
