2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
* gas/config/tc-i386.c (output_insn): Support Intel Merom New
Instructions.
* gas/config/tc-i386.h (CpuMNI): New.
(CpuUnknownFlags): Add CpuMNI.
gas/testsuite/
2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Add merom and x86-64-merom.
* gas/i386/merom.d: New file.
* gas/i386/merom.s: Likewise.
* gas/i386/x86-64-merom.d: Likewise.
* gas/i386/x86-64-merom.s: Likewise.
include/opcode/
2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (i386_optab): Support Intel Merom New Instructions.
opcodes/
2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
Intel Merom New Instructions.
(THREE_BYTE_0): Likewise.
(THREE_BYTE_1): Likewise.
(three_byte_table): Likewise.
(dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
THREE_BYTE_1 for entry 0x3a.
(twobyte_has_modrm): Updated.
(twobyte_uses_SSE_prefix): Likewise.
(print_insn): Handle 3-byte opcodes used by Intel Merom New
Instructions.
* sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
(v9_hpriv_reg_names): New table.
(print_insn_sparc): Allow values up to 16 for '?' and '!'.
New cases '$' and '%' for read/write hyperprivileged register.
* sparc-opc.c (sparc_opcodes): Add new entries for UA2005
window handling and rdhpr/wrhpr instructions.
2006-02-11 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Add "x86-64-crx" and "x86-64-crx-suffix".
* gas/i386/x86-64-crx-suffix.d: New file.
* gas/i386/x86-64-crx.d: Likewise.
* gas/i386/x86-64-crx.s: Likewise.
opcodes/
2006-02-11 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c ('Z'): Add a new macro.
(dis386_twobyte): Use "movZ" for control register moves.
instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
save/restore encoding of the args field.
* mips16-opc.c: Add MIPS16e save/restore opcodes.
* mips-dis.c (print_mips16_insn_arg): Handle printing of 'm'/'M'
codes for save/restore.
* config/tc-mips.c (mips16_ip): Add handling of 'm' and 'M' codes
for the MIPS16e save/restore instructions.
* gas/mips/mips.exp: Run new save/restore tests.
* gas/testsuite/gas/mips/mips16e-save.s: New test for generating
different styles of save/restore instructions.
* gas/testsuite/gas/mips/mips16e-save.d: New.
* All CGEN-generated sources: Regenerate.
Contribute the following changes:
2005-09-19 Dave Brolley <brolley@redhat.com>
* disassemble.c (disassemble_init_for_target): Add 'break' to case for
bfd_arch_tic4x. Use cgen_bitset_create and cgen_bitset_set for
bfd_arch_m32c case.
2005-02-16 Dave Brolley <brolley@redhat.com>
* cgen-dis.in: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
cgen_isa_mask_* to cgen_bitset_*.
* cgen-opc.c: Likewise.
2003-11-28 Richard Sandiford <rsandifo@redhat.com>
* cgen-dis.in (print_insn_@arch@): Fix comparison with cached isas.
* *-dis.c: Regenerate.
2003-06-05 DJ Delorie <dj@redhat.com>
* cgen-dis.in (print_insn_@arch@): Copy prev_isas, don't assign
it, as it may point to a reused buffer. Set prev_isas when we
change cpus.
2002-12-13 Dave Brolley <brolley@redhat.com>
* cgen-opc.c (cgen_isa_mask_create): New support function for
CGEN_ISA_MASK.
(cgen_isa_mask_init): Ditto.
(cgen_isa_mask_clear): Ditto.
(cgen_isa_mask_add): Ditto.
(cgen_isa_mask_set): Ditto.
(cgen_isa_supported): Ditto.
(cgen_isa_mask_compare): Ditto.
(cgen_isa_mask_intersection): Ditto.
(cgen_isa_mask_copy): Ditto.
(cgen_isa_mask_combine): Ditto.
* cgen-dis.in (libiberty.h): #include it.
(isas): Renamed from 'isa' and now (CGEN_ISA_MASK *).
(print_insn_@arch@): Use CGEN_ISA_MASK and support functions.
* Makefile.am (CGENDEPS): Add utils-cgen.scm and attrs.scm.
* Makefile.in: Regenerated.
2005-10-24 Jan Beulich <jbeulich@novell.com>
* ia64.h (enum ia64_opnd): Move memory operand out of set of
indirect operands.
bfd/
2005-10-24 Jan Beulich <jbeulich@novell.com>
* cpu-ia64-opc.c (elf64_ia64_operands): Move memory operand out of
set of indirect operands.
gas/
2005-10-24 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (enum reg_symbol): Delete IND_MEM.
(dot_rot): Change type of num_* variables. Check for positive count.
(ia64_optimize_expr): Re-structure.
(md_operand): Check for general register.
gas/testsuite/
2005-10-24 Jan Beulich <jbeulich@novell.com>
* gas/ia64/index.[sl]: New.
* gas/ia64/rotX.[sl]: New.
* gas/ia64/ia64.exp: Run new tests.
opcodes/
2005-10-24 Jan Beulich <jbeulich@novell.com>
* ia64-asmtab.c: Regenerate.
2005-09-28 Jan Beulich <jbeulich@novell.com>
* gas/i386/x86-64-stack.s, gas/i386/x86-64-stack.d,
gas/i386/x86-64-stack-suffix.d, gas/i386/x86-64-stack-intel.d: New.
* gas/i386/i386.exp: Run new tests.
ld/testsuite/
2005-09-28 Jan Beulich <jbeulich@novell.com>
* ld-x86-64/tlspic.dd: Adjust.
opcodes/
2005-09-28 Jan Beulich <jbeulich@novell.com>
* i386-dis.c (stack_v_mode): Renamed from branch_v_mode.
(indirEv): Use it.
(stackEv): New.
(Ob64, Ov64): Rename to Ob, Ov. Delete unused original definitions.
(dis386): Document and use new 'V' meta character. Use it for
single-byte push/pop opcode forms. Use stackEv for mod-r/m push/pop
opcode forms. Correct typo in 'pop ss'. Replace Ob64/Ov64 by Ob/Ov.
(putop): 'q' suffix for 'T' and 'U' meta depends on DFLAG. Mark
data prefix as used whenever DFLAG was examined. Handle 'V'.
(intel_operand_size): Use stack_v_mode.
(OP_E): Use stack_v_mode, but handle only the special case of
64-bit mode without operand size override here; fall through to
v_mode case otherwise.
(OP_REG): Special case rAX_reg ... rDI_reg only when 64-bit mode
and no operand size override is present.
(OP_J): Use get32s for obtaining the displacement also when rex64
is present.
(mips_builtin_opcodes): Move "bc0f", "bc0fl", "bc0t", "bc0tl" to the
bottom to avoid opcode collision with "mftr" and "mttr".
Add MT instructions.
* mips-dis.c (mips_arch_choices): Enable INSN_MT for mips32r2.
(print_insn_args): Add supports for +t, +T, !, $, *, &, g operand
formats.
bfd/
* libbdf.h: Regenerate.
* bfd-in2.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/
* config/tc-arm.c (encode_arm_cp_address): Use
BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
mode.
(md_assemble): Only allow coprocessor instructions when Thumb-2 is
available.
(cCE, cC3): Define.
(insns): Use them for coprocessor instructions.
(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
(get_thumb32_insn): New function.
(put_thumb32_insn): New function.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
gas/testsuite/
* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
opcodes/
* arm-dis.c (coprocessor_opcodes): New.
(arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
(print_insn_coprocessor): New function.
(print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
format characters.
(print_insn_thumb32): Use print_insn_coprocessor.
2005-08-26 Jan Beulich <jbeulich@novell.com>
* i386-dis.c (intel_operand_size): New, broken out from OP_E for
re-use.
(OP_E): Call intel_operand_size, move call site out of mode
dependent code.
(OP_OFF): Call intel_operand_size if suffix_always. Remove
ATTRIBUTE_UNUSED from parameters.
(OP_OFF64): Likewise.
(OP_ESreg): Call intel_operand_size.
(OP_DSreg): Likewise.
(OP_DIR): Use colon rather than semicolon as separator of far
jump/call operands.
gas/testsuite/
2005-08-26 Jan Beulich <jbeulich@novell.com>
* gas/i386/intelok.d: Adjust.
* s390-mkopc.c (s390_opcode_cpu_val): Add support for cpu type z9-109.
(main): Likewise.
* s390-opc.c (I32_16, U32_16, M_16): Add defines 32 bit immediates
and 4 bit optional masks.
(INSTR_RIL_RI, INSTR_RIL_RU, INSTR_RRF_M0RR, INSTR_RSE_CCRD,
INSTR_RSY_CCRD, INSTR_SSF_RRDRD): Add new instruction formats.
(MASK_RIL_RI, MASK_RIL_RU, MASK_RRF_M0RR, MASK_RSE_CCRD,
MASK_RSY_CCRD, MASK_SSF_RRDRD): Likewise.
(s390_opformats): Likewise.
* s390-opc.txt: Add new instructions for cpu type z9-109.
2005-07-14 Jim Blandy <jimb@redhat.com>
* configure.in: Add cases for Renesas m32c.
* configure: Regenerated.
bfd/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
Add support for m32c-*-elf (Renesas m32c and m16c).
* Makefile.am (ALL_MACHINES): Add cpu-m32c.lo.
(ALL_MACHINES_CFILES): Add cpu-m32c.c.
(BFD32_BACKENDS): Add elf32-m32c.lo.
(BFD32_BACKENDS_CFILES): Add elf32-m32c.c.
(cpu-m32c.lo, elf32-m32c.lo): New rules, generated by 'make dep-am'.
* Makefile.in: Regenerated.
* archures.c (bfd_arch_m32c, bfd_mach_m16c, bfd_mach_m32c): New
arch and mach codes.
(bfd_m32c_arch): New arch info object.
(bfd_archures_list): List bfd_m32c_arch.
* bfd-in2.h: Regenerated.
* config.bfd: Add case for the m32c.
* configure.in: Add case for the m32c.
* configure: Regenerated.
* cpu-m32c.c, elf32-m32c.c: New files.
* libbfd.h: Regenerated.
* targets.c (bfd_elf32_m32c_vec): Declare.
(_bfd_target_vector): List bfd_elf32_m32c_vec.
binutils/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
* readelf.c: #include "elf/m32c.h"
(guess_is_rela, dump_relocations, get_machine_name): Add cases for
EM_M32C.
* Makefile.am (readelf.o): Update dependencies.
* Makefile.in: Regenerated.
cpu/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
* m32c.cpu, m32c.opc: Machine description for the Renesas M32C.
gas/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
Add support for the Renesas M32C.
* Makefile.am (CPU_TYPES): List m32c.
(TARGET_CPU_CFILES): List config/tc-m32c.c.
(TARGET_CPU_HFILES): List config/tc-m32c.h.
* configure.in: Add case for m32c.
* configure.tgt: Add cases for m32c and m32c-*-elf.
* configure: Regenerated.
* config/tc-m32c.c, config/tc-m32c.h: New files.
* doc/Makefile.am (CPU_DOCS): Add c-m32c.texi.
* doc/Makefile.in: Regenerated.
* doc/all.texi: Set M32C.
* doc/as.texinfo: Add text for the M32C-specific options and line
comment characters, and refer to c-m32c.texi.
* doc/c-m32c.texi: New file.
include/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
* dis-asm.h (print_insn_m32c): New declaration.
include/elf/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
Add support for Renesas M32C and M16C.
* common.h (EM_M32C): New machine number.
* m32c.h: New file.
ld/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
Add support for the Renesas M32C and M16C.
* Makefile.am (ALL_EMULATIONS): Add eelf32m32c.o.
(eelf32m32c.c): New target.
* Makefile.in: Regenerated.
* configure.tgt: Add case for m32c-*-elf.
* emulparams/elf32m32c.sh: New file.
opcodes/ChangeLog:
2005-07-14 Jim Blandy <jimb@redhat.com>
Add support for the Renesas M32C and M16C.
* m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c: New.
* m32c-desc.h, m32c-opc.h: New.
* Makefile.am (HFILES): List m32c-desc.h and m32c-opc.h.
(CFILES): List m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c,
m32c-opc.c.
(ALL_MACHINES): List m32c-asm.lo, m32c-desc.lo, m32c-dis.lo,
m32c-ibld.lo, m32c-opc.lo.
(CLEANFILES): List stamp-m32c.
(M32C_DEPS): List stamp-m32c, if CGEN_MAINT.
(CGEN_CPUS): Add m32c.
(m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c)
(m32c-desc.h, m32c-opc.h): Depend on M32C_DEPS.
(m32c_opc_h): New variable.
(stamp-m32c, m32c-asm.lo, m32c-desc.lo, m32c-dis.lo, m32c-ibld.lo)
(m32c-opc.lo): New rules.
* Makefile.in: Regenerated.
* configure.in: Add case for bfd_m32c_arch.
* configure: Regenerated.
* disassemble.c (ARCH_m32c): New.
[ARCH_m32c]: #include "m32c-desc.h".
(disassembler) [ARCH_m32c]: Add case for bfd_arch_m32c.
(disassemble_init_for_target) [ARCH_m32c]: Same.
* cgen-ops.h, cgen-types.h: New files.
* Makefile.am (HFILES): List them.
* Makefile.in: Regenerated.
2005-07-05 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.h (CpuSVME): New.
(CpuUnknownFlags): Include CpuSVME.
* config/tc-i386.c (cpu_arch): Add .pacifica and .svme. Add opteron
as alias of sledgehammer.
(md_assemble): Include invlpga in the check for insns with two source
operands.
(process_operands): Include SVME insns in the check for ignored
segment overrides. Adjust diagnostic.
(i386_index_check): Special-case SVME insns with memory operands.
gas/testsuite/
2005-07-05 Jan Beulich <jbeulich@novell.com>
* gas/i386/svme.d: New.
* gas/i386/svme.s: New.
* gas/i386/svme64.d: New.
* gas/i386/i386.exp: Run new tests.
include/opcode/
2005-07-05 Jan Beulich <jbeulich@novell.com>
* i386.h (i386_optab): Add new insns.
opcodes/
2005-07-05 Jan Beulich <jbeulich@novell.com>
* i386-dis.c (SVME_Fixup): New.
(grps): Use it for the lidt entry.
(PNI_Fixup): Call OP_M rather than OP_E.
(INVLPG_Fixup): Likewise.
* arm-opc.h: Delete; fold contents into ...
* arm-dis.c: ... here. Move includes of internal COFF headers
next to includes of internal ELF headers.
(streq, WORD_ADDRESS, BDISP, BDISP23): Delete, unused.
(struct arm_opcode): Rename struct opcode32. Make 'assembler' const.
(struct thumb_opcode): Rename struct opcode16. Make 'assembler' const.
(arm_conditional, arm_fp_const, arm_shift, arm_regname, regnames)
(iwmmxt_wwnames, iwmmxt_wwssnames):
Make const.
(regnames): Remove iWMMXt coprocessor register sets.
(iwmmxt_regnames, iwmmxt_cregnames): New statics.
(get_arm_regnames): Adjust fourth argument to match above changes.
(set_iwmmxt_regnames): Delete.
(print_insn_arm): Constify 'c'. Use ISO syntax for function
pointer calls. Expand sole use of BDISP. Use iwmmxt_regnames
and iwmmxt_cregnames, not set_iwmmxt_regnames.
(print_insn_thumb16, print_insn_thumb32): Constify 'c'. Use
ISO syntax for function pointer calls.
include:
* dis-asm.h (get_arm_regnames): Update prototype.
that the ARM and 16-bit Thumb opcode tables each have comments
preceding them that describe all the codes, and only the codes,
valid in those tables. (32-bit Thumb table is already like this.)
Reorder the lists in all three comments to match the order in
which the codes are implemented.
Remove all forward declarations of static functions. Convert all
function definitions to ISO C format.
(print_insn_arm, print_insn_thumb16, print_insn_thumb32):
Return nothing.
(print_insn_thumb16): Remove unused case 'I'.
(print_insn): Update for changed calling convention of subroutines.
2005-05-25 Jan Beulich <jbeulich@novell.com>
* gas/i386/intelok.d: Account for 32-bit displacements being shown
in hex.
opcodes/
2005-05-25 Jan Beulich <jbeulich@novell.com>
* i386-dis.c (OP_E): In Intel mode, display 32-bit displacements in
hex (but retain it being displayed as signed). Remove redundant
checks. Add handling of displacements for 16-bit addressing in Intel
mode.
* arm.h: Import complete list of official relocation names
and numbers from AAELF. Define FAKE_RELOCs for old names.
Remove a few old names no longer used anywhere.
bfd:
* elf32-arm.c: Wherever possible, use official reloc names
from AAELF.
(elf32_arm_howto_table, elf32_arm_tls_gd32_howto)
(elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto)
(elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto)
(elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto)
(elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel)
(elf32_arm_r_howto): Replace with elf32_arm_howto_table_1,
elf32_arm_howto_table_2, and elf32_arm_howto_table_3.
Add many new relocations from AAELF.
(elf32_arm_howto_from_type): Update to match.
(elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24,
R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8,
R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY.
(elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type.
(elf32_arm_final_link_relocate): Add support for
R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove
case entries redundant with default.
* reloc.c: Reorganize ARM relocations. Add Thumb
assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8,
BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE.
Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7,
BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25.
Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY.
* bfd-in2.h, libbfd.h: Regenerate.
opcodes:
* arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
instructions. Adjust disassembly of some opcodes to match
unified syntax.
(thumb32_opcodes): New table.
(print_insn_thumb): Rename print_insn_thumb16; don't handle
two-halfword branches here.
(print_insn_thumb32): New function.
(print_insn): Choose among print_insn_arm, print_insn_thumb16,
and print_insn_thumb32. Be consistent about order of
halfwords when printing 32-bit instructions.
gas:
* hash.c (hash_lookup): Add len parameter. All callers changed.
(hash_find_n): New interface.
* hash.h: Prototype hash_find_n.
* sb.c: Include as.h.
(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
(sb_scrub_and_add_sb): New interface.
* sb.h: Prototype sb_scrub_and_add_sb.
* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
reference to BFD_RELOC_ARM_GOT12 which is never generated.
* config/tc-arm.c: Rewrite, adding Thumb-2 support.
gas/testsuite:
* gas/arm/arm.exp: Convert all existing "gas_test" tests to
"run_dump_test" tests. Run more tests unconditionally. Run new tests.
* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
Adjust to work as a dump test.
* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
New files.
* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
diagnostics that don't happen in the first pass anymore.
* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
* gas/arm/vfp-bad.l:
Update expected diagnostics.
* gas/arm/pic.d: Update expected reloc name.
* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
* gas/arm/r15-bad.s: Avoid two-argument mul.
* gas/arm/req.s: Adjust comments.
* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
use of PC.
* gas/arm/macro-1.d, gas/arm/macro1.s
* gas/arm/t16-bad.l, gas/arm/t16-bad.s
* gas/arm/tcompat.d, gas/arm/tcompat.s
* gas/arm/tcompat2.d, gas/arm/tcompat2.s
* gas/arm/thumb32.d, gas/arm/thumb32.s
New test pair.
ld/testsuite:
* ld-arm/mixed-app.d: Adjust expected disassembly a little.
* config/tc-i386.c (md_begin): Allow hyphens in mnemonics.
include/opcode/ChangeLog:
* i386.h: Insert hyphens into selected VIA PadLock extensions.
Add xcrypt-ctr. Provide aliases without hyphens.
opcodes/ChangeLog:
* i386-dis.c: Insert hyphens into selected VIA PadLock extensions.
Add xcrypt-ctr.
2005-04-01 Jan Beulich <jbeulich@novell.com>
* i386-dis.c (PNI_Fixup): Neither mwait nor monitor have any
visible operands in Intel mode. The first operand of monitor is
%rax in 64-bit mode.
2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run segment and inval-seg for i386. Run
x86-64-segment and x86-64-inval-seg for x86-64.
* gas/i386/intel.d: Expect movw for moving between memory and
segment register.
* gas/i386/naked.d: Likewise.
* gas/i386/opcode.d: Likewise.
* gas/i386/x86-64-opcode.d: Likewise.
* gas/i386/opcode.s: Use movw for moving between memory and
segment register.
* gas/i386/x86-64-opcode.s: Likewise.
* : Likewise.
* gas/i386/inval-seg.l: New.
* gas/i386/inval-seg.s: New.
* gas/i386/segment.l: New.
* gas/i386/segment.s: New.
* gas/i386/x86-64-inval-seg.l: New.
* gas/i386/x86-64-inval-seg.s: New.
* gas/i386/x86-64-segment.l: New.
* gas/i386/x86-64-segment.s: New.
include/opcode/
2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (i386_optab): Don't allow the `l' suffix for moving
moving between memory and segment register. Allow movq for
moving between general-purpose register and segment register.
opcodes/
2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (SEG_Fixup): New.
(Sv): New.
(dis386): Use "Sv" for 0x8c and 0x8e.
* ppc-opc.c (insert_sprg, extract_sprg): New Functions.
(powerpc_operands <SPRG>): Call the above. Bit field is 5 bits.
(SPRG_MASK): Delete.
(XSPRG_MASK): Mask off extra bits now part of sprg field.
(powerpc_opcodes): Asjust mfsprg and mtsprg to suit new mask. Move
mfsprg4..7 after msprg and consolidate.
gas/testsuite
* gas/ppc/booke.s: Add new m[t,f]sprg testcases.
* gas/ppc/booke.d: Likewise.
* opcodes/arc-dis.c:Add enum a4_decoding_class.
(dsmOneArcInst): Use the enum values for the decoding class
Remove redundant case in the switch for decodingClass value 11
2005-02-07 Jim Blandy <jimb@redhat.com>
* cgen-opc.scm: Don't load fixup.scm here. (See corresponding
changes in the opcodes directory.)
opcodes/ChangeLog:
2005-02-07 Jim Blandy <jimb@redhat.com>
* Makefile.am (CGEN): Load guile.scm before calling the main
application script.
* Makefile.in: Regenerated.
* cgen.sh: Be prepared for the 'cgen' argument to contain spaces.
Simply pass the cgen-opc.scm path to ${cgen} as its first
argument; ${cgen} itself now contains the '-s', or whatever is
appropriate for the Scheme being used.
2005-01-31 Jan Beulich <jbeulich@novell.com>
* config/tc-ia64.c (parse_operands): Also handle alloc without first
input being ar.pfs.
gas/testsuite/
2005-01-31 Jan Beulich <jbeulich@novell.com>
* gas/ia64/pseudo.[ds]: New.
* gas/ia64/ia64.exp: Run new test.
opcodes/
2005-01-31 Jan Beulich <jbeulich@novell.com>
* ia64-gen.c (NELEMS): Define.
(shrink): Generate alias with missing second predicate register when
opcode has two outputs and these are both predicates.
* ia64-opc-i.c (FULL17): Define.
(ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17
here to generate output template.
(TBITCM, TNATCM): Undefine after use.
* ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as
first input. Add ld16 aliases without ar.csd as second output. Add
st16 aliases without ar.csd as second input. Add cmpxchg aliases
without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/
ar.ccv as third/fourth inputs. Consolidate through...
(CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8,
CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define.
* ia64-asmtab.c: Regenerate.
* mips-dis.c (no_aliases): New disassembly option flag.
(set_default_mips_dis_options): Init no_aliases to zero.
(parse_mips_dis_option): Handle no-aliases option.
(print_insn_mips): Ignore table entries that are aliases
if no_aliases is set.
(print_insn_mips16): Ditto.
* mips-opc.c (mips_builtin_opcodes): Add initializer column for
new pinfo2 member and add INSN_ALIAS initializers as needed. Also
move WR_MACC and RD_MACC initializers from pinfo to pinfo2.
* mips16-opc.c (mips16_opcodes): Ditto.
2005-01-12 H.J. Lu <hongjiu.lu@intel.com>
* i386/i386.exp: Run "sib".
* gas/i386/sib.d: New file.
* gas/i386/sib.s: Likewise.
opcodes/
2005-01-12 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
* configure.in: Don't define SKIP_ZEROES.
* configure: Regenerate.
* objdump.c (disassemble_data): Set skip_zeroes and
skip_zeroes_at_end in disasm_info to defaults.
(DEFAULT_SKIP_ZEROES): Rename from SKIP_ZEROES and always define.
(DEFAULT_SKIP_ZEROES_AT_END): Rename from SKIP_ZEROES_AT_END and
always define.
(disassemble_bytes): Use skip_zeroes and skip_zeroes_at_end from
objdump_disasm_info.
include/:
* dis-asm.h (struct disassemble_info): Add skip_zeroes and
skip_zeroes_at_end.
opcodes/:
* disassemble.c (disassemble_init_for_target) <case
bfd_arch_ia64>: Set skip_zeroes to 16.
<case bfd_arch_tic4x>: Set skip_zeroes to 32.
* crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
(no_op_insn): Initialize array with instructions that have no
operands.
* crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
