This patch backports the AArch64 support for Arm's Neoverse N2 CPU to
binutils 2.35.
gas/ChangeLog:
* config/tc-aarch64.c (aarch64_cpus): Add neoverse-n2.
* doc/c-aarch64.texi: Document support for Neoverse N2.
This patch backports the AArch32 support for Arm's Neoverse N2 CPU to
binutils 2.35.
gas/ChangeLog:
* config/tc-arm.c (arm_cpus): Add Neoverse N2.
* doc/c-arm.texi: Document -mcpu=neoverse-n2.
This patch backports the AArch32 support for Arm's Neoverse V1 CPU to
binutils 2.35.
gas/ChangeLog:
* config/tc-arm.c (arm_cpus): Add Neoverse V1.
* doc/c-arm.texi: Document Neoverse V1 support.
When the address size prefix applies to both the memory and the register
operand, we need to extract the address size prefix from the register
operand if the memory operand has no real registers, like symbol, DISP
or symbol(%rip).
NB: GCC always generates symbol(%rip) for RIP-relative addressing for
both x32 and x86-64.
Move the .code16 tests in movdir.s to movdir-16bit to show the correct
output from objdump.
gas/
PR gas/26685
* config/tc-i386.c (process_suffix): Also check the register
operand for the address size prefix if the memory operand has
no real registers.
* testsuite/gas/i386/enqcmd-16bit.d: New file.
* testsuite/gas/i386/enqcmd-16bit.s: Likewise.
* testsuite/gas/i386/movdir-16bit.d: Likewise.
* testsuite/gas/i386/movdir-16bit.s: Likewise.
* testsuite/gas/i386/enqcmd.s: Add tests with symbol and DISP.
* testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
* testsuite/gas/i386/x86-64-movdir.s: Likewise.
* testsuite/gas/i386/movdir.s: Add tests with symbol and DISP.
Remove the .code16 test.
* testsuite/gas/i386/i386.exp: Run movdir-16bit and enqcmd-16bit.
* testsuite/gas/i386/x86-64-enqcmd-intel.d: Updated.
* testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
* testsuite/gas/i386/x86-64-movdir-intel.d: Likewise.
* testsuite/gas/i386/x86-64-movdir.d: Likewise.
* testsuite/gas/i386/enqcmd-intel.d: Likewise.
* testsuite/gas/i386/enqcmd.d: Likewise.
* testsuite/gas/i386/movdir-intel.d: Likewise.
* testsuite/gas/i386/movdir.d: Likewise.
* testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
* testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
* testsuite/gas/i386/x86-64-movdir-intel.d: Likewise.
* testsuite/gas/i386/x86-64-movdir.d: Likewise.
opcodes/
PR gas/26685
* i386-dis.c (mod_table): Replace Gv with Gdq on movdiri.
(cherry picked from commit b3a3496f83)
If the address prefix changes the register operand, we need to check the
register operand when the memory operand is RIP-relative.
PR gas/26685
* config/tc-i386.c (process_suffix): Check the register operand
for the address size prefix if the memory operand is symbol(%rip).
* testsuite/gas/i386/x86-64-enqcmd.s: Add tests with RIP-relative
addressing.
* testsuite/gas/i386/x86-64-movdir.s: Likewise.
* testsuite/gas/i386/x86-64-enqcmd-intel.d: Updated.
* testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
* testsuite/gas/i386/x86-64-movdir-intel.d: Likewise.
* testsuite/gas/i386/x86-64-movdir.d: Likewise.
(cherry picked from commit 27f134698a)
This reverts commit 04c662e2b6.
In my underlying suggestion I neglected the fact that in those
cases (,%eiz,1) is the only visible indication that 32-bit
addressing is in effect.
(cherry picked from commit bf4ba07ca6)
This patch fixes a bogus use of type punning in parse_barrier() which
was causing an assembly failure on big endian LP64 hosts when attempting
to assemble "isb sy" for AArch64.
The type of the entries in aarch64_barrier_opt_hsh is
aarch64_name_value_pair. We were incorrectly casting this to the
locally-defined asm_barrier_opt which has a wider type (on LP64) for the
second member. This happened to work on little-endian hosts but fails on
LP64 big endian.
The fix is to use the correct type in parse_barrier(). This makes the
locally-defined asm_barrier_opt redundant, so remove it.
gas/ChangeLog:
PR 26699
* config/tc-aarch64.c (asm_barrier_opt): Delete.
(parse_barrier): Fix bogus type punning.
* testsuite/gas/aarch64/system.d: Update disassembly.
* testsuite/gas/aarch64/system.s: Add isb sy test.
(cherry picked from commit 05cfb0d8cc)
This backports the AArch64 support for Arm's Neoverse V1 CPU to binutils
2.35.
gas/ChangeLog:
* config/tc-aarch64.c (aarch64_cpus): Add Neoverse V1.
* doc/c-aarch64.texi: Document Neoverse V1 support.
These shouldn't be optional. The record form of vector instructions
set CR6, giving an expectation that omitting BF should be the same as
specifying CR6.
opcodes/
* ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
vcmpuq and xvtlsbb.
gas/
* testsuite/gas/ppc/int128.s: Correct vcmpuq.
* testsuite/gas/ppc/int128.d: Update.
* testsuite/gas/ppc/xvtlsbb.d: Update.
(cherry picked from commit 18a8a00ebe)
Import from mainline:
2020-09-14 Nick Clifton <nickc@redhat.com>
* read.c (s_nop): New function. Handles the .nop directive.
(potable): Add entry for "nop".
(s_nops): Code tidy.
* read.h (s_nop): Add prototype.
* config/tc-bpf.h (md_single_noop_insn): Define.
* config/tc-mmix.h (md_single_noop_insn): Define.
* config/tc-or1k.h (md_single_noop_insn): Define.
* config/tc-ia64.h (md_single_noop_insn): Define.
* write.c (relax_segment): Update error message regarding
non-absolute values passed to .fill and .nops.
* NEWS: Mention the new directive.
* doc/as.texi: Document the new directive.
* doc/internals.texi: Document the new internal macros used to
implement the new directive.
* testsuite/gas/all/nop.s: New test.
* testsuite/gas/all/nop.d: New test control file.
* testsuite/gas/all/gas.exp: Run the new test.
* testsuite/gas/elf/dwarf-5-nop-for-line-table.s: New test.
* testsuite/gas/elf/dwarf-5-nop-for-line-table.d: New test
control file.
* testsuite/gas/elf/elf.exp: Run the new test.
* testsuite/gas/i386/space1.l: Adjust expected output.
When -g was used to generate DWARF gas would error out when a .debug_line
already exists. But when a .debug_info section already exists it would
simply skip generating one without warning or error. Do the same for
.debug_line. It is only an error when the user explicitly uses .loc
directives and also generates the .debug_line table itself.
The tests are unfortunately arch specific because the line table is only
generated when actual instructions have been emitted. Use i386 because
that is probably the most used architecture. Before this patch the new
dwarf-line-2 testcase would fail, with this patch it succeeds (and doesn't
try to add its own line table).
gas/ChangeLog:
* as.texi (-g): Explicitly mention when .debug_info and .debug_line
are generated for the DWARF format.
(Loc): Add that it is an error to both use a .loc directive and
generate a .debug_line yourself.
* dwarf2dbg.c (dwarf2_any_loc_directive_seen): New static variable.
(dwarf2_directive_loc): Set dwarf2_any_loc_directive_seen to TRUE.
(dwarf2_finish): Check dwarf2_any_loc_directive_seen before emitting
an error. Only create .debug_line if it is empty (or doesn't exist).
* testsuite/gas/i386/i386.exp: Add dwarf2-line-{1,2,3,4} when testing
an elf target.
* testsuite/gas/i386/dwarf2-line-{1,2,3,4}.{s,d,l}: New test files.
* dwarf2dbg.c (add_line_strp): New function.
(out_dir_and_file_list): Take line_seg and sizeof_offset as
arguments, Use DW_FORM_line_strp for dir and file. Call
add_line_strp and set symbol offset for DWARF2_LINE_VERSION 5.
(out_debug_line): Call out_dir_and_file_list with line_seg and
sizeof_offset.
* gas/testsuite/gas/elf/dwarf-5-file0.d: Expect indirect line
strings.
* dwarf2dbg.c (DWARF2_RNGLISTS_VERSION): New constant.
(out_debug_ranges): Add ranges_sym argument and set it.
(out_debug_rnglists): New function.
(out_debug_info): Change ranges_seg argument to ranges_sym
and use it to set DW_AT_ranges value.
(dwarf2_finish): Remove ranges_seg, add ranges_sym. For
DWARF2_VERSION 5 call out_debug_rnglists.
Older DWARF versions used DW_FORM_data4 or DW_FORM_data8 for offsets
into sections for e.g. DW_AT_stmt_list ot DW_AT_ranges. But version 4
introduced a dedicated form for such section offsets. Make sure to emit
the proper form for newer DWARF versions.
gas/ChangeLog:
* dwarf2dbg.c (out_debug_abbrev): Use DW_FORM_sec_offset for DWARF
version 4 or higher.
parse_args uses getopt_long_only so it can handle long options both
with double and single dash. But this means that some single dash
options like -gdwarf-1 don't generate an error (unlike --gdwarf-1).
This is especially confusing since there is also --gdwarf2, but no
--gdwarf4 (it is --gdwarf-4). When giving -gdwarf4 the option is
silently interpreted as -g (which set dwarf_version to 2). This causes
some confusion for people who don't expect this and suddenly get
DWARF2 instead of DWARF4 as they might expect.
So make it so that the -gdwarf<unknown> creates an error, just like
--gdwarf<unknown> would.
This patch adds support for xBPF, another ISA targetting the BPF
virtual architecture. For now, the primary difference between eBPF
and xBPF is that xBPF supports indirect calls through the
'call %reg' form of the call instruction.
bfd/
* archures.c (bfd_mach_xbpf): Define.
* bfd-in2.h: Regenerate.
* cpu-bpf.c (bfd_xbpf_arch) New.
(bfd_bpf_arch) Update next in list field to point to xbpf arch.
cpu/
* bpf.cpu (arch bpf): Add xbpf mach and isas.
(define-xbpf-isa) New pmacro.
(all-isas) Add xbpfle,xbpfbe.
(endian-isas): New pmacro.
(mach xbpf): New.
(model xbpf-def): Likewise.
(h-gpr): Add xbpf mach.
(f-dstle, f-srcle, dstle, srcle): Add xbpfle isa.
(f-dstbe, f-srcbe, dstbe, srcbe): Add xbpfbe isa.
(define-alu-insn-un): Use new endian-isas pmacro.
(define-alu-insn-bin, define-alu-insn-mov): Likewise.
(define-endian-insn, define-lddw): Likewise.
(dlind, dxli, dxsi, dsti): Likewise.
(define-cond-jump-insn, define-call-insn): Likewise.
(define-atomic-insns): Likewise.
gas/
* config/tc-bpf.c: Add option -mxbpf to select xbpf isa.
* testsuite/gas/bpf/indcall-1.d: New file.
* testsuite/gas/bpf/indcall-1.s: Likewise.
* testsuite/gas/bpf/indcall-bad-1.l: Likewise.
* testsuite/gas/bpf/indcall-bad-1.s: Likewise.
* testsuite/gas/bpf/bpf.exp: Run new tests.
opcodes/
* bpf-desc.c: Regenerate.
* bpf-desc.h: Likewise.
* bpf-opc.c: Likewise.
* bpf-opc.h: Likewise.
* disassemble.c (disassemble_init_for_target): Set bits for xBPF
ISA when appropriate.
(cherry picked from commit 4449c81a85)
2020-08-04 Mark Wielaard <mark@klomp.org>
* dwarf2dbg.c (out_debug_abbrev): When DWARF2_VERSION >= 4, use
DW_FORM_udata for DW_AT_high_pc.
(out_debug_info): Use emit_leb128_expr for DW_AT_high_pc, when
DWARF2_VERSION >= 4.
* read.c (emit_leb128_exp): No longer static.
* read.h (emit_leb128_exp): Define.
2020-08-02 Mark Wielaard <mark@klomp.org>
* gas/dwarf2dbg.c (out_dir_and_file_list): For DWARF5 emit at
least one directory if there is at least one file. Use dirs[1]
if dirs[0] is not set, or if there is no dirs[1] the current
working directory. Use files[1] filename, when files[0] filename
isn't set.
2020-08-02 Mark Wielaard <mark@klomp.org>
* dwarf2dbg.c (out_debug_info): Emit unit type and abbrev offset
for DWARF5.
* gas/testsuite/gas/elf/dwarf-4-cu.d: New file.
* gas/testsuite/gas/elf/dwarf-4-cu.s: Likewise.
* gas/testsuite/gas/elf/dwarf-5-cu.d: Likewise.
* gas/testsuite/gas/elf/dwarf-5-cu.s: Likewise.
* testsuite/gas/elf/elf.exp: Run dwarf-4-cu and dwarf-5-cu.
The xvcvbf16sp mnemonic has been renamed to xvcvbf16spn, to be consistent
with the other non-signaling conversion instructions which all end with "n".
opcodes/
Backported from master:
2020-08-18 Peter Bergner <bergner@linux.ibm.com>
* ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
<xvcvbf16spn>: ...to this.
gas/
Backported from master:
2020-08-18 Peter Bergner <bergner@linux.ibm.com>
* testsuite/gas/ppc/vsx4.s: Update test to use new mnemonic.
* testsuite/gas/ppc/vsx4.d: Likewise.
(cherry picked from commit f5fc30d05c)
This patch fixes an incorrect parsing of vcvtne for MVE. Even when it appeared
in an IT block, vcvtne would be parsed as a VPT-predicated vcvtn, instead of an
IT-predicated vcvt. This change extends the existing handling of MVE vcvt to
properly account for IT predication.
gas/ChangeLog:
2020-08-13 Joe Ramsay <joe.ramsay@arm.com>
Backported from master
2020-08-04 Joe Ramsay <joe.ramsay@.arm.com>
* config/tc-arm.c (do_neon_cvt_1): Parse vcvtne as vcvt-ne for
NS_FD shape when MVE is present
* testsuite/gas/arm/mve-vcvtne-it-bad.d: New test.
* testsuite/gas/arm/mve-vcvtne-it-bad.l: New test.
* testsuite/gas/arm/mve-vcvtne-it-bad.s: New test.
* testsuite/gas/arm/mve-vcvtne-it.d: New test.
* testsuite/gas/arm/mve-vcvtne-it.s: New test.
Since (%bp)/(%ebp)/(%rbp) are encoded as 0(%bp)/0(%ebp)/0(%rbp), use
disp32/disp16 on 0(%bp)/0(%ebp)/0(%rbp) for {disp32}.
Note: Since there is no disp32 on 0(%bp), use disp16 instead.
PR gas/26305
* config/tc-i386.c (build_modrm_byte): Use disp32/disp16 on
(%bp)/(%ebp)/(%rbp) for {disp32}.
* doc/c-i386.texi: Update {disp32} documentation.
* testsuite/gas/i386/pseudos.s: Add (%bp)/(%ebp) tests.
* testsuite/gas/i386/x86-64-pseudos.s: Add (%ebp)/(%rbp) tests.
* testsuite/gas/i386/pseudos.d: Updated.
* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
(cherry picked from commit 1a02d6b0ff)
Change
67 48 8b 1c 25 ef cd ab 89 mov 0x89abcdef(,%eiz,1),%rbx
to
67 48 8b 1c 25 ef cd ab 89 mov 0x89abcdef,%rbx
in AT&T syntax and
67 48 8b 1c 25 ef cd ab 89 mov rbx,QWORD PTR [eiz*1+0x89abcdef]
to
67 48 8b 1c 25 ef cd ab 89 mov rbx,QWORD PTR ds:0x89abcdef
in Intel syntax.
gas/
PR gas/26237
* testsuite/gas/i386/evex-no-scale-64.d: Updated.
* testsuite/gas/i386/addr32.d: Likewise.
* testsuite/gas/i386/x86-64-addr32-intel.d: Likewise.
* testsuite/gas/i386/x86-64-addr32.d: Likewise.
opcodes/
PR gas/26237
* i386-dis.c (OP_E_memory): Don't display eiz with no scale
without base nor index registers.
(cherry picked from commit 04c662e2b6)
Since the addr32 (0x67) prefix zero-extends the lower 32 bits address to
64 bits, change disassembler to zero-extend the lower 32 bits displacement
to 64 bits when there is no base nor index registers.
gas/
PR gas/26237
* testsuite/gas/i386/addr32.s: Add tests for 32-bit wrapped around
address.
* testsuite/gas/i386/x86-64-addr32.s: Likewise.
* testsuite/gas/i386/addr32.d: Updated.
* testsuite/gas/i386/x86-64-addr32-intel.d: Likewise.
* testsuite/gas/i386/x86-64-addr32.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-addr32-intel.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-addr32.d: Likewise.
opcodes/
PR gas/26237
* i386-dis.c (OP_E_memory): Without base nor index registers,
32-bit displacement to 64 bits.
(cherry picked from commit 8e58ef803c)
When encoding a 32-bit offset, there is no need to sign-extend it to 64
bits since only the lower 32 bits are used.
PR gas/26237
* config/tc-i386.c (offset_in_range): Remove 32-bit sign
extension.
(cherry picked from commit 7a70531559)
* write.c (create_note_reloc): Add desc2_size parameter. Zero out
the addend field of REL relocations. Store the full addend into
the note for REL relocations.
The upper 16 vector registers were added by AVX512.
PR gas/26212
* doc/c-i386.texi: Remove an incorrect AVX2 entry.
(cherry picked from commit dbdba9b04d)
We check register-only source operand to decide if two source operands of
VEX encoded instructions should be swapped. But source operands in AMX
instructions with two source operands swapped are all register-only
operand. Add SwapSources to indicate two source operands should be
swapped.
gas/
* config/tc-i386.c (build_modrm_byte): Check vexswapsources to
swap two source operands.
opcodes/
* i386-gen.c (opcode_modifiers): Add VexSwapSources.
* i386-opc.h (VexSwapSources): New.
(i386_opcode_modifier): Add vexswapsources.
* i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
with two source operands swapped.
* i386-tbl.h: Regenerated.
This patch fixes a segfault which occurs when the AArch64 backend parses
a symbol operand that begins with a register name and ends with a
unicode byte (byte value > 127).
For example, the following input causes the crash:
x0é: udf x0é
gas/ChangeLog:
2020-07-02 Alex Coplan <alex.coplan@arm.com>
* config/tc-aarch64.c (reg_name_p): Fix cast so that we don't
segfault on negative chars.
* testsuite/gas/aarch64/reglike-label-unicode-segv.d: New test.
* testsuite/gas/aarch64/reglike-label-unicode-segv.s: Input.
