(RELAX_MIPS16_ENCODE): Add dslot and jal_dslot arguments, and
store them. Adjust other RELAX_MIPS16 macros.
(RELAX_MIPS16_DSLOT): Define.
(RELAX_MIPS16_JAL_DSLOT): Define.
(append_insn): Pass new arguments to RELAX_MIPS16_ENCODE. Correct
handling of whether previous instruction has a fixup. Set
prev_insn_reloc_type.
(mips_no_prev_insn): Clear prev_insn_reloc_type.
(mips16_extended_frag): Use the right base address for a PC
relative add or load.
(md_convert_frag): Likewise. If a PC relative add or load is
used, record the alignment for the section.
system, don't set the section alignment to 2**4.
(s_change_sec): Likewise.
(append_insn): Call record_alignment for the section.
(md_section_align): Don't align the section size for an embedded
ELF system.
arguments, and store them. Adjust other RELAX_MIPS16 macros.
(RELAX_MIPS16_USER_SMALL): Define.
(RELAX_MIPS16_USER_EXT): Define.
(mips16_small, mips16_ext): New static variables.
(append_insn): Pass mips16_small and mips16_ext to
RELAX_MIPS16_ENCODE.
(mips16_ip): Set mips16_small and mips16_ext.
(mips16_immed): Don't check mips16_autoextend.
(mips16_extended_frag): Check USER_SMALL and USER_EXT.
* config/tc-d10v.c (md_assemble): Check to see if prev_seg
is initialized before using it.
(d10v_cleanup): No longer uses its argument, so make it void.
* config/tc-d10v.h (d10v_cleanup): Change prototype.
(tc_fix_adjustable): Don't adjust relocs against weak symbols or
pc-relative relocs.
* config/tc-mn10300.c (md_begin): Set linkrelax.
(md_assemble): Create fixups as needed.
(md_apply_fix3): Gut. It shouldn't ever get called anymore.
First stab at fixups/relocs.
the extension part of the instruction if necessary.
(mn10300_insert_operand): Accept pointer to extension word
argument. Make insn a pointer argument too. Return type
is now void. All callers changed.
So we can correct insert operands into any instruction except those
which have 32bit operands.
* config/tc-v850.c: Fix some indention problems.
(md_relax_table): Define for D9->D99 branch displacement
relaxing.
(md_convert_frag): Do something useful instead of aborting.
(md_estimate_size_before_relax): Likewise.
(md_assemble): Note if the matching instruction has a relaxable
operand. If it does, allocate frag with frag_var and don't
do any fixups.
So we can do 9bit displacement to 22bit displacement relaxing.
hacks to improve parsing of complex hi, lo, zda, etc
expressions.
(md_assemble): Don't demand and eat a trailing ')' after finding
a v850 relocation prefix. Sign extend the constant in a
BFD_RELOC_LO16 expression. Do eat a trailing ')' after a complete
operand.
(parse_cons_expression_v850): Don't eat a trailing ')' after
finding a v850 relocation prefix.
Trying to get nec's sample code to assemble. Why oh why didn't JT try
to assemble any of their code...
(TC_CONS_FIX_NEW): Likewise.
* config/tc-v850.c (parse_cons_expression_v850): New function.
(cons_fix_new_v850): Likewise.
So we can handle ".hword lo(_foo)".
(md_pcrel_from_section): New function.
* config/tc-v850.h (MD_PCREL_FROM_SECTION): Define.
So we don't screw up pc-relative jumps/calls from one section
into another section within the same .o file.
Fixes global ctors/dtors to work with DECL_ONE_ONLY stuff.
* config/obj-elf.c (elf_frob_file): Move ECOFF debug processing to ...
(elf_frob_file_after_relocs): ... here. New function.
* config/obj-elf.h (obj_from_file_after_relocs): New macro.
* write.c (write_object_file): Call *frob_after_relocs after the
call to write_relocs.
* config/tc-alpha.c: Use new BFD_RELOC_ALPHA_ELF_LITERAL reloc.
* config/tc-alpha.c (load_expression): Don't SET_VALUE on the section
symbol, as this messes up linking. Instead, expand the recursive call
inline and change up the appropriate bits to get the 0x8000 offset
in the reloc addend.
