tic4x fails due to being a 4 octets per byte target, while tic54x is 2
octets per byte.
mmix still fails with
fill-1.s:4: Error: unknown pseudo-op: `.l1:'
fill-1.s:6: Error: unknown pseudo-op: `.l2:'
fill-1.s:3: Error: .space specifies non-absolute value
and if the labels are changed to L1 and L2 then mep-elf fails with
fill-1.s:3: Error: .space specifies non-absolute value
Since both of those look like they ought to be investigated by the
target maintainers, I'm tweaking the test to fail on both targets.
* testsuite/gas/all/fill-1.d: Exclude tic4x and tic54x.
* testsuite/gas/all/fill-1.s: Use L1 rather than .L1.
These are all invalid instructions, so they should not disassemble.
opcodes/ChangeLog
2017-10-24 Andrew Waterman <andrew@sifive.com>
* riscv-opc.c (match_c_addi16sp) : New function.
(match_c_addi4spn): New function.
(match_c_lui): Don't allow 0-immediate encodings.
(riscv_opcodes) <addi>: Use the above functions.
<add>: Likewise.
<c.addi4spn>: Likewise.
<c.addi16sp>: Likewise.
gas/ChangeLog
2017-10-24 Andrew Waterman <andrew@sifive.com>
* testsuite/gas/riscv/c-addi16sp-fail.d: New test.
testsuite/gas/riscv/c-addi16sp-fail.l: Likewise.
testsuite/gas/riscv/c-addi16sp-fail.s: Likewise.
testsuite/gas/riscv/c-addi4spn-fail.d: Likewise.
testsuite/gas/riscv/c-addi4spn-fail.l: Likewise.
testsuite/gas/riscv/c-addi4spn-fail.s: Likewise.
testsuite/gas/riscv/riscv.exp: Add new tests.
This matches the ISA specification. This also adds two tests: one to
make sure the assembler rejects invalid 'c.lui's, and one to make sure
we only relax valid 'c.lui's.
bfd/ChangeLog
2017-10-24 Andrew Waterman <andrew@sifive.com>
* elfnn-riscv.c (_bfd_riscv_relax_lui): Don't relax to c.lui
when rd is x0.
include/ChangeLog
2017-10-24 Andrew Waterman <andrew@sifive.com>
* opcode/riscv.h (VALID_RVC_LUI_IMM): c.lui can't load the
immediate 0.
gas/ChangeLog
2017-10-24 Andrew Waterman <andrew@sifive.com>
* testsuite/gas/riscv/c-lui-fail.d: New testcase.
gas/testsuite/gas/riscv/c-lui-fail.l: Likewise.
gas/testsuite/gas/riscv/c-lui-fail.s: Likewise.
gas/testsuite/gas/riscv/riscv.exp: Likewise.
ld/ChangeLog
2017-10-24 Andrew Waterman <andrew@sifive.com>
* ld/testsuite/ld-riscv-elf/c-lui.d: New testcase.
ld/testsuite/ld-riscv-elf/c-lui.s: Likewise.
ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp: New test suite.
Without 64-bit bfd, we can't properly support .code64 directive in
32-bit mode.
* config/tc-i386.c (md_pseudo_table): Add .code64 directive
only if BFD64 is defined.
* testsuite/gas/i386/code64-inval.l: New file.
* gas/testsuite/gas/i386/code64-inval.s: Likewise.
* gas/testsuite/gas/i386/code64.d: Likewise.
* gas/testsuite/gas/i386/code64.s: Likewise.
* testsuite/gas/i386/i386.exp: Run mixed-mode-reloc32,
att-regs, intel-regs, intel-expr and string-ok tests only if
assembler supports x86-64. Run code64 and code64-inval.
Systems without the C extension mandate 4-byte alignment for
instructions, so there is no reason to allow for 2-byte alignment. This
change avoids emitting lots of unimplemented instructions into object
files on non-C targets, which users keep reporting as a bug. While this
isn't actually a bug (as none of the offsets in object files are
relevant until RISC-V), it is ugly.
gas/ChangeLog
2017-10-23 Palmer Dabbelt <palmer@dabbelt.com>
* config/tc-riscv.c (riscv_frag_align_code): Align code by 4
bytes on non-RVC systems.
Fix a bug in MIPS n32 ELF object file generation and make such objects
consistent with the n32 BFD requested, by presetting the EF_MIPS_ABI2
flag in the `e_flags' member of the newly created ELF file header, as it
is this flag that tells n32 objects apart from o32 objects.
This flag will then stay set through to output file generation for
writers such as GAS or GDB's `generate-core-file' command. Readers will
overwrite the whole of `e_flags' along with the rest of the ELF file
header in `elf_swap_ehdr_in' and then verify in `mips_elf_n32_object_p'
that the flag is still set before accepting an input file as an n32
object.
The issue was discovered with GDB's `generate-core-file' command making
o32 core files out of n32 debuggees.
bfd/
* elfn32-mips.c (mips_elf_n32_mkobject): New prototype and
function.
(bfd_elf32_mkobject): Use `mips_elf_n32_mkobject' rather than
`_bfd_mips_elf_mkobject'.
gas/
* config/tc-mips.c (mips_elf_final_processing): Don't set
EF_MIPS_ABI2 in `e_flags'.
With a 32-bit bfd (default on an ILP32 system) the previous markings
on tests *were* correct. There, the results have been consistent
since they were added. The tests would appear to "spuriously" xpass
"only" on LP64 hosts, which were not the norm in 2000. (But, now CRIS
requires a 64-bit BFD.)
PR 22324
* read.c (s_rept): Use size_t type for count parameter.
(do_repeat): Change type of count parameter to size_t.
Issue an error is the count parameter is negative.
(do_repeat_with_expression): Likewise.
* read.h: Update prototypes for do_repeat and
do_repeat_with_expression.
* doc/as.texinfo (Rept): Document that a zero count is allowed but
negative counts are not.
* config/tc-rx.c (rx_rept): Use size_t type for count parameter.
* config/tc-tic54x.c (tic54x_loop): Cast count parameter to size_t
type.
* testsuite/gas/macros/end.s: Add a test using a negative repeat
count.
* testsuite/gas/macros/end.l: Add expected error message.
In the medany code model the compiler generates PCREL_HI20+PCREL_LO12
relocation pairs against local symbols because HI20+LO12 relocations
can't reach high addresses. We relax HI20+LO12 pairs to GPREL
relocations when possible, which is an important optimization for
Dhrystone. Without this commit we are unable to relax
PCREL_HI20+PCREL_LO12 pairs to GPREL when possible, causing a 10%
permormance hit on Dhrystone on Rocket.
Note that we'll now relax
la gp, __global_pointer$
to
mv gp, gp
which probably isn't what you want in your entry code. Users who want
gp-relative symbols to continue to resolve should add ".option norelax"
accordingly. Due to this, the assembler now pairs PCREL relocations
with RELAX relocations when they're expected to be relaxed just like
every other relaxable relocation.
bfd/ChangeLog
2017-10-19 Palmer Dabbelt <palmer@dabbelt.com>
* elfnn-riscv.c (riscv_pcgp_hi_reloc): New structure.
(riscv_pcgp_lo_reloc): Likewise.
(riscv_pcgp_relocs): Likewise.
(riscv_init_pcgp_relocs): New function.
(riscv_free_pcgp_relocs): Likewise.
(riscv_record_pcgp_hi_reloc): Likewise.
(riscv_record_pcgp_lo_reloc): Likewise.
(riscv_delete_pcgp_hi_reloc): Likewise.
(riscv_use_pcgp_hi_reloc): Likewise.
(riscv_record_pcgp_lo_reloc): Likewise.
(riscv_find_pcgp_lo_reloc): Likewise.
(riscv_delete_pcgp_lo_reloc): Likewise.
(_bfd_riscv_relax_pc): Likewise.
(_bfd_riscv_relax_section): Handle R_RISCV_PCREL_* relocations
via the new functions above.
gas/ChangeLog
2017-10-19 Palmer Dabbelt <palmer@dabbelt.com>
* config/tc-riscv.c (md_apply_fix): Mark
BFD_RELOC_RISCV_PCREL_HI20 as relaxable when relaxations are
enabled.
PR 21621
* config/tc-avr.h (struct avr_frag_data): Add prev_opcode field.
(TC_FRAG_INIT): Define.
(avr_frag_init): Add prototype.
* config/tc-avr.c (avr_frag_init): New function.
(avr_operands): Replace static local 'prev' variable with
prev_opcode field in current frag.
* testsuite/gas/avr/pr21621.s: New test source file.
* testsuite/gas/avr/pr21621.d: New test driver file.
* testsuite/gas/avr/pr21621.s: New test error output file.
This fixes various issues with the fill-1 testcase causing fails on a
couple of targets.
gas/ChangeLog:
2017-10-19 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* testsuite/gas/all/fill-1.s: Use normal labels. Change .text to
.data. Pick different values. Use .dc.w instead of .word.
* testsuite/gas/all/fill-1.d: New objdump output check.
* testsuite/gas/all/gas.exp: Use run_dump_test to execute fill-1
testcase.
There are individual comments that explain why each test isn't
supported, but the vast majority of them are due to RISC-V's aggressive
linker relaxation. The SLEB test cases should eventually be supported,
but the remaining ones probably won't ever be.
2017-10-18 Palmer Dabbelt <palmer@dabbelt.com>
* testsuite/gas/all/align.d: Mark as unsupported on RISC-V.
testsuite/gas/all/relax.d: Likewise.
testsuite/gas/all/sleb128-2.d: Likewise.
testsuite/gas/all/sleb128-4.d: Likewise.
testsuite/gas/all/sleb128-5.d: Likewise.
testsuite/gas/all/sleb128-7.d: Likewise.
testsuite/gas/elf/section11.d: Likewise.
testsuite/gas/all/gas.exp (diff1.s): Likewise.
2017-10-16 Sandra Loosemore <sandra@codesourcery.com>
Henry Wong <henry@stuffedcow.net>
gas/
* config/tc-nios2.c (nios2_translate_pseudo_insn): Check for
correct number of arguments.
(md_assemble): Handle failure of nios2_translate_pseudo_insn.
* testsuite/gas/nios2/illegal_pseudoinst.l: New file.
* testsuite/gas/nios2/illegal_pseudoinst.s: New file.
* testsuite/gas/nios2/nios2.exp: Add illegal_pseudoinst test.
FT32B is a new FT32 family member. It has a code
compression scheme, which requires the use of linker
relaxations. The change is quite large, so submission
is in several parts.
Part 1 adds a 15-bit instruction field, and CPU-specific functions for
the code compression that are used in binutils and GDB.
bfd/ChangeLog:
2017-10-12 James Bowman <james.bowman@ftdichip.com>
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* elf32-ft32.c: Add HOWTO R_FT32_15.
* reloc.c: Add BFD_RELOC_FT32_15.
gas/ChangeLog:
2017-10-12 James Bowman <james.bowman@ftdichip.com>
* config/tc-ft32.c (md_assemble): Replace FT32_FLD_K8 with
K15.
(md_apply_fix, tc_gen_reloc): Add BFD_RELOC_FT32_15.
include/ChangeLog:
2017-10-12 James Bowman <james.bowman@ftdichip.com>
* elf/ft32.h: Add R_FT32_15.
* opcode/ft32.h: Replace FT32_FLD_K8 with K15.
(ft32_shortcode, sc_compar, ft32_split_shortcode,
ft32_merge_shortcode, ft32_merge_shortcode): New functions.
opcodes/ChangeLog:
2017-10-12 James Bowman <james.bowman@ftdichip.com>
* opcodes/ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
* opcodes/ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
K15. Add jmpix pattern.
sim/ChangeLog:
2017-10-12 James Bowman <james.bowman@ftdichip.com>
* sim/ft32/interp.c (step_once): Replace FT32_FLD_K8 with K15.
PR 21977
* listing.c (listing_newline): Use the name of the current
physical input file, rather than the current logical input file,
unless including high level source in the listing.
* input-scrub.c (as_where_physical): New function. Returns the
name of the current physical input file.
* as.h: Add prototype for as_where_physical.
prno, tpei, and irbm are missing in the optable.
gas/ChangeLog:
2017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* testsuite/gas/s390/zarch-arch12.d (prno, tpei, irbm): New
instructions added.
* testsuite/gas/s390/zarch-arch12.s: Likewise.
* testsuite/gas/s390/zarch-z13.d: Rename ppno to prno.
opcodes/ChangeLog:
2017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-opc.txt (prno, tpei, irbm): New instructions added.
PR 22133
* config/tc-msp430.c (parse_exp): Skip an 'h' suffix to constant
expressions.
(msp430_srcoperand): Check that the entire text was parsed by
parse_exp.
(msp430_operands): Likewise.
* testsuite/gas/msp430/pr22133.s: New test file.
* testsuite/gas/msp430/pr22133.d: New test driver.
* testsuite/gas/msp430/pr22133.s: Expected error output.
* testsuite/gas/msp430/msp430.exp: Run the new test.
This fixes a wart I've known about for years, but haven't done
anything about because BFD treats relocation sections as an adjunct to
the section they relocate. SHF_GROUP on the section thus implicitly
applies to its relocation section(s), but it is an error that the
reloc sections aren't part of the group.
Like many patches to gas, this wasn't as straightforward as it could
be due to a number of backends, i386, cr16 and others, removing relocs
in tc_get_reloc rather than marking them as "done" earlier in
md_apply_reloc. So it isn't possible for the group support to
reliably detect the presence of relocs by looking at fixups earlier
than write_relocs. However the group support needs to create
signature symbols, and that must be done before the symbol table is
frozen, before write_relocs. So split off the group sizing from
elf_adjust_symtab and put it in elf_frob_file_after_relocs.
bfd/
PR 21167
* elf.c (_bfd_elf_setup_sections): Don't trim reloc sections from
groups.
(_bfd_elf_init_reloc_shdr): Pass sec_hdr, use it to copy SHF_GROUP
flag from section.
(elf_fake_sections): Adjust calls. Exit immediately on failure.
(bfd_elf_set_group_contents): Add associated reloc section indices
to group contents
gas/
PR 21167
* config/obj-elf.c (struct group_list): Delete elt_count.
(groups): New static.
(build_group_lists): Don't count elements.
(elf_adjust_symtab): Use groups rather than auto list. Set up
pointer from group member to SHT_GROUP section. Don't size
SHT_GROUP section or clean up here..
(elf_frob_file_after_relocs): ..do so here instead.
* testsuite/gas/arc/jli-1.d,
* testsuite/gas/elf/groupautob.d,
* testsuite/gas/mips/compact-eh-eb-2.d,
* testsuite/gas/mips/compact-eh-eb-5.d,
* testsuite/gas/mips/compact-eh-el-2.d,
* testsuite/gas/mips/compact-eh-el-5.d: Adjust.
ld/
PR 21167
* testsuite/ld-elf/group9b.d: Adjust for relocs included in group.
opcodes/
* ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
VLE multimple load/store instructions. Old e_ldm* variants are
kept as aliases.
Add missing e_lmvmcsrrw and e_stmvmcsrrw.
gas/
* testsuite/gas/ppc/vle-mult-ld-st-insns.s: New file: Tests the
support for the VLE multiple load/store instructions.
* testsuite/gas/ppc/vle-mult-ld-st-insns.d: New file: Test
driver.
* testsuite/gas/ppc/ppc.exp: Run it.
PR 22179
opcodes * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
names for the fmv.x.s and fmv.s.x instructions respectively.
gas * testsuite/gas/riscv/fmv.x.s: New file: Tests the support for the
renamed fmv.x.s and fmv.s.x instructions.
* testsuite/gas/riscv/fmv.x.d: New file: Test driver.
Fix commit e407c74b5b ("Support for MIPS R5900 (Sony Playstation 2)"),
<https://sourceware.org/ml/binutils/2012-12/msg00240.html>, and add the
handling of E_MIPS_MACH_5900, correctly showing `5900' among `Flags:' in
the output of `-h' rather than `unknown CPU'.
binutils/
* readelf.c (get_machine_flags) <E_MIPS_MACH_5900>: New case.
gas/
* testsuite/gas/mips/elf_mach_5900.d: New test.
* testsuite/gas/mips/mips.exp: Run it.
If a .stabs directive was used before another .set directive in a MIPS
source file, s_mips_stab would call mips_mark_labels without having
initialized the mips_opts structure yet. Fix this by calling
file_mips_check_options which will initialize mips_opts if necessary.
gas/
PR gas/21762
* config/tc-mips.c (s_mips_stab): Insert call to
file_mips_check_options.
* testsuite/gas/mips/micromips@stabs-symbol-type.d: New test.
* testsuite/gas/mips/mips.exp: Run the new tests.
* testsuite/gas/mips/mips16@stabs-symbol-type.d: New test.
* testsuite/gas/mips/stabs-symbol-type.d: New test.
* testsuite/gas/mips/stabs-symbol-type.s: New test source.
PowerPC64 .cfi directives use DW_EH_PE_sdata4 encoding for .eh_frame,
so there is no real reason why .eh_frame should be 8 byte aligned.
gas/
* config/tc-ppc.h (EH_FRAME_ALIGNMENT): Define.
ld/
* testsuite/ld-powerpc/tlsopt5.wf: Update for reduced alignment.
"sec" gets set to NULL on errors in the offset expression. This patch
disables part of the reloc expression processing that needs "sec"
valid. I didn't disable the entire reloc expression handling so that
errors in the reloc expression are reported even when the offset
expression has an error.
PR 22127
* write.c (resolve_reloc_expr_symbols): Don't segfault when
sec has been set to NULL.
Since the NOTRACK prefix is no longer required to be the last prefix
before the REX prefix, restriction on the NOTRACK prefix position is
removed from assembler as well as disassembler. Assembler encodes the
NOTRACK prefix the same way as the DS segment register, which places
it before other prefixes. Disassembler displays prefixes in the order
they appear.
gas/
* config/tc-i386.c (NOTRACK_PREFIX): Removed.
(REX_PREFIX): Updated.
(MAX_PREFIXES): Likewise.
(parse_insn): Remove restriction on NOTRACK prefix position.
* testsuite/gas/i386/notrack.s: Add tests with NOTRACK prefix
before other prefixes.
* testsuite/gas/i386/x86-64-notrack.s: Likewise.
* testsuite/gas/i386/notrackbad.s: Remove tests with NOTRACK
prefix before other prefixes.
* testsuite/gas/i386/x86-64-notrackbad.s: Likewise.
* testsuite/gas/i386/notrack-intel.d: Updated.
* testsuite/gas/i386/notrack.d: Likewise.
* testsuite/gas/i386/notrackbad.l: Likewise.
* testsuite/gas/i386/x86-64-notrack-intel.d: Likewise.
* testsuite/gas/i386/x86-64-notrack.d: Likewise.
* testsuite/gas/i386/x86-64-notrackbad.l: Likewise.
opcodes/
* i386-dis.c (last_active_prefix): Removed.
(ckprefix): Don't set last_active_prefix.
(NOTRACK_Fixup): Don't check last_active_prefix.
When linking the following code
.global _prog_start
_prog_start:
mv x1, x1
mv x2, x2
.align 2
rvc_boundry:
.option norvc
.align 3
mv x3, x3
we currently emit an invalid two-byte 0 instruction. The actual output
code looks like
0000000080000000 <_prog_start>:
80000000: 8086 mv ra,ra
80000002: 810a mv sp,sp
0000000080000004 <rvc_boundry>:
80000004: 0000 unimp
80000006: 0001 nop
80000008: 00018193 mv gp,gp
This ends up manifesting due to the two-byte compressed NOP that's
pessimisticly emitted by the ".align 2", which results in "rvc_boundry"
being 2-byte aligned. frag_align_code() then goes and outputs a 2-byte
NOP (which is invalid in no-RVC mode) to align the code back to a 4-byte
boundry, which can't be relaxed away by the linker as it's not part of
the R_RISCV_RELAX relocation.
The fix is to just always emit the worst case possible alignment into
the output as a single R_RISCV_RELAX, which the linker will then fix up.
With this patch I get the expected code generation
0000000080000000 <_prog_start>:
80000000: 8086 mv ra,ra
80000002: 810a mv sp,sp
0000000080000004 <rvc_boundry>:
80000004: 00000013 nop
80000008: 00018193 mv gp,gp
gas/ChangeLog
2017-09-07 Palmer Dabbelt <palmer@dabbelt.com>
* config/tc-riscv.c (riscv_frag_align_code): Emit the entire
alignment sequence inside R_RISCV_ALIGN.
Fix a bug in commit a6ebf6169a ("MIPS: Convert cross-mode BAL to
JALX") and in BFD linker relaxation correct the microMIPS interpretation
of the branch offset, which is supposed to be shifted by 1 bit, rather
than 2 as in the regular MIPS case.
bfd/
* elfxx-mips.c (mips_elf_perform_relocation): Correct microMIPS
branch offset interpretation.
gas/
* testsuite/gas/mips/branch-addend-micromips.d: New test.
* testsuite/gas/mips/branch-addend-micromips-n32.d: New test.
* testsuite/gas/mips/branch-addend-micromips-n64.d: New test.
* testsuite/gas/mips/branch-addend-micromips.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* testsuite/ld-mips-elf/bal-jalx-addend-micromips.d: New test.
* testsuite/ld-mips-elf/bal-jalx-addend-micromips-n32.d: New
test.
* testsuite/ld-mips-elf/bal-jalx-addend-micromips-n64.d: New
test.
* testsuite/ld-mips-elf/bal-jalx-local-micromips.d: New test.
* testsuite/ld-mips-elf/bal-jalx-local-micromips-n32.d: New
test.
* testsuite/ld-mips-elf/bal-jalx-local-micromips-n64.d: New
test.
* testsuite/ld-mips-elf/bal-jalx-pic-micromips.d: New test.
* testsuite/ld-mips-elf/bal-jalx-pic-micromips-n32.d: New test.
* testsuite/ld-mips-elf/bal-jalx-pic-micromips-n64.d: New test.
* testsuite/ld-mips-elf/bal-jalx-pic-ignore-micromips.d: New
test.
* testsuite/ld-mips-elf/bal-jalx-pic-ignore-micromips-n32.d: New
test.
* testsuite/ld-mips-elf/bal-jalx-pic-ignore-micromips-n64.d: New
test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
Fix a bug in commit 8b10b0b3e1 ("MIPS: Add options to control branch
ISA checks") and with the `-mignore-branch-isa' command-line option also
lift a GAS check for invalid MIPS16 branches between ISA modes, which is
made separately from regular MIPS and microMIPS checks.
gas/
* config/tc-mips.c (md_convert_frag): Respect
`mips_ignore_branch_isa'.
* testsuite/gas/mips/branch-local-5.d: New test.
* testsuite/gas/mips/branch-local-n32-5.d: New test.
* testsuite/gas/mips/branch-local-n64-5.d: New test.
* testsuite/gas/mips/branch-local-6.d: New test.
* testsuite/gas/mips/branch-local-n32-6.d: New test.
* testsuite/gas/mips/branch-local-n64-6.d: New test.
* testsuite/gas/mips/branch-local-7.d: New test.
* testsuite/gas/mips/branch-local-n32-7.d: New test.
* testsuite/gas/mips/branch-local-n64-7.d: New test.
* testsuite/gas/mips/branch-local-ignore-5.d: New test.
* testsuite/gas/mips/branch-local-ignore-n32-5.d: New test.
* testsuite/gas/mips/branch-local-ignore-n64-5.d: New test.
* testsuite/gas/mips/branch-local-ignore-6.d: New test.
* testsuite/gas/mips/branch-local-ignore-n32-6.d: New test.
* testsuite/gas/mips/branch-local-ignore-n64-6.d: New test.
* testsuite/gas/mips/branch-local-5.l: New stderr output.
* testsuite/gas/mips/branch-local-6.l: New stderr output.
* testsuite/gas/mips/branch-local-5.s: New test source.
* testsuite/gas/mips/branch-local-6.s: New test source.
* testsuite/gas/mips/branch-local-7.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
gas/
* config/tc-sparc.c (tc_gen_reloc): Convert BFD_RELOC_8/16/32/64
into the corresponding BFD_RELOC_8/16/32/64_PCREL relocation
when requested.
* config/tc-sparc.h (DIFF_EXPR_OK): Define to enable PC-relative
diff relocations.
(TC_FORCE_RELOCATION_SUB_LOCAL): Define to ensure only supported
relocations are made PC-relative.
(CFI_DIFF_EXPR_OK): Define to 0 to force BFD_RELOC_32_PCREL to
be used directly, since otherwise BFD_RELOC_SPARC_UA32 will be
used for .eh_frame which cannot in general be converted to a
BFD_RELOC_32_PCREL due to alignment requirements.
We got a report from the linux-arm-kernel folks about getting spurious
warnings when building the kernel with binutils 2.29. See
https://www.spinics.net/lists/arm-kernel/msg599929.html
which boils down to this testcase.
$> cat /tmp/tst.s
lr .req x30
/tmp/tst.s: Assembler messages:
/tmp/tst.s:1: Warning: ignoring attempt to redefine built-in register 'lr'
Instead let's treat this as a proper alias at startup time thus
avoiding the problem and treating these as proper aliases
rather than new registers. This means that attempts to redefine
the alias with the same "name" will provoke no warning and attempts
to redefine the alias to something else will provoke the above mentioned
warning.
Tested make check-gas and no regressions.
Ok to apply to trunk (and backport to 2.29 branch)?
Regards
Ramana
We can't create alias of common symbol. Local alias of common symbol has
been disallowed. But global alias of common symbol is disallowed when the
common symbol is seen first and silently dropped otherwise. This patch
disallows alias of common symbol in all cases.
gas/
PR gas/21667
* read.c (pseudo_set): Update error message for alias of common
symbol.
* write.c (write_object_file): Disallow both local and global
aliases of common symbol.
* testsuite/gas/elf/common5a.d: New file.
* testsuite/gas/elf/common5a.l: Likewise.
* testsuite/gas/elf/common5a.s: Likewise.
* testsuite/gas/elf/common5b.d: Likewise.
* testsuite/gas/elf/common5b.l: Likewise.
* testsuite/gas/elf/common5b.s: Likewise.
* testsuite/gas/elf/common5c.d: Likewise.
* testsuite/gas/elf/common5c.s: Likewise.
* testsuite/gas/elf/common5d.d: Likewise.
* testsuite/gas/elf/common5d.s: Likewise.
* testsuite/gas/elf/elf.exp: Run common5a, common5b, common5c
and common5d.
PR gas/21939
* config/obj-macho.c (obj_mach_o_set_indirect_symbols): Increase
size of indirect_syms array so that it is large enough to hold
every symbol if necessary.
According to ARMv8-A architecture manual, REG_SP is allowed in CRC32
instructions in Thumb mode. It is REG_PC that will cause unpredictable
behaviours on both ARM and Thumb.
This patch removes the incorrect warning on Thumb mode.
Meanwhile the disassembler is updated to use format "<bitfield>R" instead of
"<bitfield>S". "<bitfield>S" is not used elsewhere. so I have deleted related
code from the disassembler.
gas/
* config/tc-arm.c (do_crc32_1): Remove warning on REG_SP for thumb_mode.
* testsuite/gas/arm/crc32-armv8-a-bad.d: Update exepcted result.
* testsuite/gas/arm/crc32-armv8-r-bad.d: Likewise.
* testsuite/gas/arm/crc32-armv8-a.d: Likewise.
* testsuite/gas/arm/crc32-armv8-r.d: Likewise.
* testsuite/gas/arm/crc32-armv8-ar-bad.s: Update test case.
* testsuite/gas/arm/crc32-armv8-ar.s: Likewise.
* testsuite/gas/arm/crc32-bad.l: Update expected error message.
opcode/
* arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
register operands in CRC instructions.
(print_insn_thumb32): Remove "<bitfield>S" support. Updated the
comments.
PR 21809
* config/tc-aarch64.c (aarch64_init_frag): Do not set a mapping
state for frags in debug sections.
* config/tc-arm.c (arm_init_frag): Likewise.
Trying to build (for mmix-knuth-mmixware but I don't think that
matters) yields the following (repeatable on e.g. CompileFarm gcc20
sporting gcc-4.7.2 as default):
gcc -DHAVE_CONFIG_H -I. -I/home/hp/binutils/src/gas -I. -I/home/hp/binutils/src/gas -I../bfd -I/home/hp/binutils/src/gas/config -I/home/hp/binutils/src/gas/../include -I/home/hp/binutils/src/gas/.. -I/home/hp/binutils/src/gas/../bfd -DLOCALEDIR="\"/usr/local/share/locale\"" -W -Wall -Wstrict-prototypes -Wmissing-prototypes -Wshadow -Werror -Wwrite-strings -I/home/hp/binutils/src/gas/../zlib -g -O2 -MT dwarf2dbg.o -MD -MP -MF .deps/dwarf2dbg.Tpo -c -o dwarf2dbg.o /home/hp/binutils/src/gas/dwarf2dbg.c
cc1: warnings being treated as errors
/home/hp/binutils/src/gas/dwarf2dbg.c: In function 'dwarf2dbg_final_check':
/home/hp/binutils/src/gas/dwarf2dbg.c:2246: error: declaration of 'expr' shadows a global declaration
/home/hp/binutils/src/gas/expr.h:180: error: shadowed declaration is here
make[4]: *** [dwarf2dbg.o] Error 1
IIRC this is a false namespace clash and the warning is not observable
with a new-enough gcc. Committed as obvious.
brgds, H-P
PS. Idea: -Wcompiler; warn about constructs problematic with e.g. old gcc. 1/2 ;-)
With IBM z14 officially announced I can add z14 as CPU name.
No regressions with that patch on s390x.
gas/ChangeLog:
2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/tc-s390.c (s390_parse_cpu): Add z14 as alternate CPU
name.
* doc/as.texinfo: Add z14 to CPU string list.
* doc/c-s390.texi: Likewise.
opcodes/ChangeLog:
2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-mkopc.c (main): Enable z14 as CPU string in the opcode
table.
The following relocation types were added to GCC/binutils:
ARC_JLI_SECTOFF is a relocation type in Metaware that is now used by
GCC as well to adjust the index of function calls to functions with
attribute jli_call_always.
bfd/
2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
John Eric Martin <John.Martin@emmicro-us.com>
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* elf32-arc.c (JLI): Define.
* reloc.c: Add JLI relocations.
gas/
2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/jli-1.d: New file.
* testsuite/gas/arc/jli-1.s: Likewise.
* testsuite/gas/arc/taux.d: Update for jli_base.
include/
2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
John Eric Martin <John.Martin@emmicro-us.com>
* elf/arc-reloc.def: Add JLI relocs howto.
* opcode/arc-func.h (replace_jli): New function.
ld/
2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
John Eric Martin <John.Martin@emmicro-us.com>
* emulparams/arcelf.sh (JLI_START_TABLE): Define.
* scripttempl/elfarc.sc: Handle jlitab section.
* scripttempl/elfarcv2.sc: Likewise.
* testsuite/ld-arc/arc.exp: Add JLI test.
* testsuite/ld-arc/jli-script.ld: New file.
* testsuite/ld-arc/jli-simple.dd: Likewise.
* testsuite/ld-arc/jli-simple.rd: Likewise.
* testsuite/ld-arc/jli-simple.s: Likewise.
* testsuite/ld/testsuite/ld-arc/jli-overflow.s: Likewise.
* testsuite/ld/testsuite/ld-arc/jli-overflow.d: Likewise.
* testsuite/ld/testsuite/ld-arc/jli-overflow.err: Likewise.
opcode/
2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
John Eric Martin <John.Martin@emmicro-us.com>
* arc-opc.c (UIMM10_6_S_JLIOFF): Define.
(UIMM3_23): Adjust accordingly.
* arc-regs.h: Add/correct jli_base register.
* arc-tbl.h (jli_s): Likewise.
bfd * elf32-xtensa.c (elf_xtensa_get_plt_section): Increase length of
plt_name buffer.
(elf_xtensa_get_gotplt_section): Increase length of got_name
buffer.
* mach-o-arm.c (bfd_mach_o_arm_canonicalize_one_reloc): Add a
default return of FALSE.
* mach-o-i386.c (bfd_mach_o_i386_canonicalize_one_reloc): Add a
default return of FALSE.
binutils * dwarf.c (dwarf_vmatoa_1): Do not pass a NULL string pointer to
sprintf.
* srconv.c (walk_tree_type): Initialise the spare field of the
IT_dty structure.
gas * config/tc-pru.c (md_assemble): Add continue statement after
handling 'E' operand character.
* config/tc-v850.c (md_assemble): Initialise the 'insn' variable.
This patch adds support for the ARM Cortex-A55 and
Cortex-A75 processors.
The ARM Cortex-A55 and Cortex-A75 procsessors implement the ARMv8-A
architecture, with support for the ARMv8.1-A and ARMv8.2-A extensions,
including support for the 16-bit floating point extensions.
The 16-bit floating-point extensions are optional, and we haven't defined
an option mapping straight to them thus far, so this patch first needs to
add one of those in include/opcode/arm.h, then we can simply add the CPU names
as usual in config/tc-arm.c .
Tested on arm-none-eabi.
2017-07-05 James Greenhalgh <james.greenhalgh@arm.com>
* config/tc-arm.c (arm_cpus): Add Cortex-A55 and Cortex-A75.
* doc/c-arm.texi (-mcpu): Document Cortex-A55 and Cortex-A75.
The instructions are not documented in the Intel SDM but are documented
in the AMD APM as an alias to the group 2, ModRM.reg == 4 variant.
Both AMD and Intel CPUs execute the C[0-1] and D[0-3] instructions as
expected, i.e., like the /4 aliases:
#include <stdio.h>
int main(void)
{
int a = 2;
printf ("a before: %d\n", a);
asm volatile(".byte 0xd0,0xf0" /* SHL %al */
: "+a" (a));
printf("a after : %d\n", a);
return 0;
}
$ ./a.out
a before: 2
a after : 4
This patch adds support mvfr2 control registers for armv8-a as
this was missed from the original port to armv8-a (documented
at G6.2.109 in (Issue B.a) of the ARM-ARM. This was discovered
by an internal user of the GNU toolchain.
I'd like to backport this to the binutils 2.28 and binutils 2.29
release branch if possible (with suitable testing and basically
checking removing the armv8-r parts).
Tristan - are you ok with the backports ?
Applied to trunk.
regards Ramana
2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* gas/config/tc-arm.c (arm_regs): Add MVFR2.
(do_vmrs): Constraint for MVFR2 and armv8.
(do_vmsr): Likewise.
* gas/testsuite/gas/arm/armv8-a+fp.d: Update.
* gas/testsuite/gas/arm/armv8-ar+fp.s: Likewise.
* gas/testsuite/gas/arm/armv8-r+fp.d: Likewise.
* gas/testsuite/gas/arm/vfp-bad.s: Likewise.
* gas/testsuite/gas/arm/vfp-bad.l: Likewise.
* opcodes/arm-dis.c: Support MVFR2 in disassembly
with vmrs and vmsr.
Use a switch on the relaxation type rather than a chain of conditionals
in microMIPS fixup creation, improving source code structure and aiding
the compiler with code generation.
gas/
* config/tc-mips.c (md_convert_frag): Use a switch on the
microMIPS relaxation type rather than a chain of conditionals.
There is no need to use a helper expression in the creation of fixups
made from a frag's symbol and offset, because a simple `symbol+offset'
expression can be handled directly, with the use of a `fix_new' rather
than a `fix_new_exp' call. Rewrite `md_convert_frag' using `fix_new'
then and remove all the unneeded helper expressions, simplifying code.
gas/
* config/tc-mips.c (md_convert_frag): Rewrite `fix_new_exp'
calls in terms of `fix_new'.
Use frag symbols with a non-zero offset directly in `fix_new_exp' calls
made in PIC branch relaxation. There is no need here to make a helper
symbol to hold the result of a `symbol+offset' calculation requested as
only branches to local symbols are relaxed and in this case the LO16
part of the PIC address load sequence will have the offset accounted for
in calculation against the local GOT entry retrieved as the GOT16 high
part. Consequently actual code produed is identical whether a helper
symbol is used or the original `symbol+offset' expression used directly.
Verify that this is indeed the case with GAS and LD tests.
gas/
* config/tc-mips.c (md_convert_frag): Don't make a helper
expression symbol for `fix_new_exp' called with a non-zero
offset.
* testsuite/gas/mips/relax-offset.d: New test.
* testsuite/gas/mips/mips1@relax-offset.d: New test.
* testsuite/gas/mips/r3000@relax-offset.d: New test.
* testsuite/gas/mips/r3900@relax-offset.d: New test.
* testsuite/gas/mips/micromips@relax-offset.d: New test.
* testsuite/gas/mips/relax-offset.l: New stderr output.
* testsuite/gas/mips/relax-offset.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* testsuite/ld-mips-elf/relax-offset.dd: New test.
* testsuite/ld-mips-elf/relax-offset.gd: New test.
* testsuite/ld-mips-elf/relax-offset-umips.dd: New test.
* testsuite/ld-mips-elf/relax-offset-umips.gd: New test.
* testsuite/ld-mips-elf/relax-offset.ld: New test linker script.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
(prune_warnings): New temporary procedure.
PR gas/21683
include * opcode/avr.h (AVR_INSN): Add one for __gcc_isr.
gas * doc/c-avr.texi (AVR Options) <-mgcc-isr>: Document it.
(AVR Pseudo Instructions): New node.
* config/tc-avr.h (md_pre_output_hook): Define to avr_pre_output_hook.
(md_undefined_symbol): Define to avr_undefined_symbol.
(avr_pre_output_hook, avr_undefined_symbol): New protos.
* config/tc-avr.c (struc-symbol.h): Include it.
(ISR_CHUNK_Done, ISR_CHUNK_Prologue, ISR_CHUNK_Epilogue): New enums.
(avr_isr, avr_gccisr_opcode)
(avr_no_sreg_hash, avr_no_sreg): New static variables.
(avr_opt_s) <have_gccisr>: Add field.
(avr_opt): Add initializer for have_gccisr.
(enum options) <OPTION_HAVE_GCCISR>: Add enum.
(md_longopts) <"mgcc-isr">: Add entry.
(md_show_usage): Document -mgcc-isr.
(md_parse_option) [OPTION_HAVE_GCCISR]: Handle it.
(md_undefined_symbol): Remove.
(avr_undefined_symbol, avr_pre_output_hook): New fuctions.
(md_begin) <avr_no_sreg_hash, avr_gccisr_opcode>: Initialize them.
(avr_operand) <pregno>: Add argument and set *pregno if function
is called for a register constraint.
[N]: Handle constraint.
(avr_operands) <avr_operand>: Pass 5th parameter to calls.
[avr_opt.have_gccisr]: Call avr_update_gccisr. Call
avr_gccisr_operands instead of avr_operands.
(avr_update_gccisr, avr_emit_insn, avr_patch_gccisr_frag)
(avr_gccisr_operands, avr_check_gccisr_done): New static functions.
* testsuite/gas/avr/gccisr-01.d: New test.
* testsuite/gas/avr/gccisr-01.s: New test.
* testsuite/gas/avr/gccisr-02.d: New test.
* testsuite/gas/avr/gccisr-02.s: New test.
* testsuite/gas/avr/gccisr-03.d: New test.
* testsuite/gas/avr/gccisr-03.s: New test.
Complement commit a92713e60e ("Preparse MIPS instructions into
tokens"), <https://sourceware.org/ml/binutils/2013-07/msg00143.html>,
and update `match_float_constant' and `match_operand' function
descriptions according to semantics changes.
gas/
* config/tc-mips.c (match_float_constant): Update description.
(match_operand): Likewise.
Add support for the base and Virtualization ASE microMIPS instructions
as per the architecture specifications[1][2][3][4].
Most of this change by Andrew Bennett.
[1] "MIPS Architecture for Programmers Volume II-B: The microMIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00582,
Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit
Instructions", p. 340
[2] "microMIPS32 Architecture for Programmers Volume IV-i:
Virtualization Module of the microMIPS32 Architecture", MIPS
Technologies, Inc., Document Number: MD00848, Revision 1.06,
December 10, 2013, Section 6.1 "Overview", pp. 133, 136
[3] "MIPS Architecture for Programmers Volume II-B: The microMIPS64
Instruction Set", MIPS Technologies, Inc., Document Number: MD00594,
Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit
Instructions", pp. 415, 444
[4] "microMIPS64 Architecture for Programmers Volume IV-i:
Virtualization Module of the microMIPS64 Architecture", MIPS
Technologies, Inc., Document Number: MD00849, Revision 1.06,
December 10, 2013, Section 6.1 "Overview", pp. 134-135, 139-140
binutils/
* NEWS: Mention microMIPS XPA support.
opcodes/
* micromips-opc.c (XPA, XPAVZ): New macros.
(micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
"mthgc0".
gas/
* config/tc-mips.c (mips_ases): Add microMIPS XPA support.
* testsuite/gas/mips/micromips@xpa.d: New test.
* testsuite/gas/mips/mips.exp: Run the new test. Enable
`xpa-virt-err' test for `micromips'.
Add base microMIPS Release 5 ISA support and the ERETNC instruction in
particular, as per the architecture specifications[1][2].
Most of this change by Andrew Bennett.
References:
[1] "MIPS Architecture for Programmers Volume II-B: The microMIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00582,
Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit
Instructions", pp. 266-267
[2] "MIPS Architecture for Programmers Volume II-B: The microMIPS64
Instruction Set", MIPS Technologies, Inc., Document Number: MD00594,
Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit
Instructions", pp. 326-327
binutils/
* NEWS: Mention microMIPS Release 5 ISA support.
opcodes/
* micromips-opc.c (I36): New macro.
(micromips_opcodes): Add "eretnc".
gas/
* testsuite/gas/mips/micromips@r5.d: New test.
* testsuite/gas/mips/mips.exp: Run the new test.
Correct a commit 7d64c587c1 ("Add support for the MIPS eXtended
Physical Address (XPA) ASE.") bug, causing XPA base and Virtualization
ASE instructions to be wrongly always enabled with the selection of the
MIPS32r2 or higher ISA.
For example this source assembles successfully as shown below:
$ cat xpa.s
mfhc0 $2, $1
$ as -32 -mips32 -o xpa.o xpa.s
xpa.s: Assembler messages:
xpa.s:1: Error: opcode not supported on this processor: mips32 (mips32) `mfhc0 $2,$1'
$ as -32 -mips32r2 -o xpa.o xpa.s
$ objdump -d xpa.o
xpa.o: file format elf32-tradbigmips
Disassembly of section .text:
00000000 <.text>:
0: 40420800 mfhc0 v0,c0_random
...
$
To address this issue remove the I33 (INSN_ISA32R2) marking from all XPA
instructions in the opcode table. Additionally, for XPA Virtualization
ASE instructions implement an XPAVZ (ASE_XPA_VIRT) combination ASE flag
and use it in place of IVIRT|XPA (ASE_VIRT|ASE_XPA).
Now the same source is correctly rejected unless the `-mxpa' option is
also used:
$ as -32 -mips32r2 -o xpa.o xpa.s
xpa.s: Assembler messages:
xpa.s:1: Error: opcode not supported on this processor: mips32r2 (mips32r2) `mfhc0 $2,$1'
$ as -32 -mips32r2 -mxpa -o xpa.o xpa.s
$
Add test cases for XPA base and XPA Virtualization ASE instructions.
Parts of this change by Andrew Bennett.
include/
* opcode/mips.h (ASE_XPA_VIRT): New macro.
opcodes/
* mips-dis.c (mips_calculate_combination_ases): Handle the
ASE_XPA_VIRT flag.
(parse_mips_ase_option): New function.
(parse_mips_dis_option): Factor out ASE option handling to the
new function. Call `mips_calculate_combination_ases'.
* mips-opc.c (XPAVZ): New macro.
(mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
"mfhgc0", "mthc0" and "mthgc0".
gas/
* config/tc-mips.c (mips_set_ase): Handle the ASE_XPA_VIRT flag.
* testsuite/gas/mips/xpa.d: Remove `xpa' from `-M' in `objdump'
flags. Add `-mvirt' to `as' flags.
* testsuite/gas/mips/xpa-err.d: New test.
* testsuite/gas/mips/xpa-virt-err.d: New test.
* testsuite/gas/mips/xpa-err.l: New stderr output.
* testsuite/gas/mips/xpa-virt-err.l: New stderr output.
* testsuite/gas/mips/xpa-err.s: New test source.
* testsuite/gas/mips/xpa-virt-err.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
binutils/
* testsuite/binutils-all/mips/mips-xpa-virt-1.d: New test.
* testsuite/binutils-all/mips/mips-xpa-virt-2.d: New test.
* testsuite/binutils-all/mips/mips-xpa-virt-3.d: New test.
* testsuite/binutils-all/mips/mips-xpa-virt-4.d: New test.
* testsuite/binutils-all/mips/mips-xpa-virt.s: New test source.
* testsuite/binutils-all/mips/mips.exp: Run the new tests.
Correct a commit 25499ac7ee ("MIPS16e2: Add MIPS16e2 ASE support")
disassembler bug with the handling of the ASE_MIPS16E2_MT combination
ASE flag, where the calculation uses MIPS ABI Flags directly rather than
calculated internal ASE flags. Consequently code does not correctly set
the ASE_MIPS16E2_MT flag when the MIPS16e2 ASE flag and the MT ASE flag
come from different sources, i.e. one from the BFD chosen and the other
one from MIPS ABI Flags.
Fix this by using internal ASE_MT and ASE_MIPS16E2 flags in a separate
subsequent step, factored out to a dedicated function for use with
future combination ASE flags. Adjust the `mips16e2@mips16e2-mt-sub.d'
test case accordingly, where the MT flag comes from the BFD selected for
the disassembler and the MIPS16e2 flag comes from the ELF binary itself.
opcodes/
* mips-dis.c (mips_calculate_combination_ases): New function.
(mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
calculation to the new function.
(set_default_mips_dis_options): Call the new function.
gas/
* testsuite/gas/mips/mips16e2@mips16e2-mt-sub.d: Adjust for the
ASE_MIPS16E2_MT flag disassembler fix.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e2-mt-sub.d:
Likewise.
Correct a commit 25499ac7ee ("MIPS16e2: Add MIPS16e2 ASE support") GAS
bug with the handling of the ASE_MIPS16E2_MT combination ASE flag, which
is not correctly calculated as `.set nomips16e2' and `.set nomt'
pseudo-ops are processed. This leads to code like:
$ cat foo.s
.set nomt
evpe
.align 4, 0
$ cat bar.s
.set nomips16e2
dvpe
.align 4, 0
$
to successfully assemble where it should not:
$ as -32 -mips32r3 -mmt -mips16 -mmips16e2 -o foo.o foo.s
$ as -32 -mips32r3 -mmt -mips16 -mmips16e2 -o bar.o bar.s
$ objdump -m mips:16 -d foo.o
foo.o: file format elf32-tradbigmips
Disassembly of section .text:
00000000 <.text>:
0: f027 6700 evpe
...
bar.o: file format elf32-tradbigmips
Disassembly of section .text:
00000000 <.text>:
0: f026 6700 dvpe
...
$
This happens because ASE_MIPS16E2_MT once set in `mips_set_ase' is never
cleared. Fix the problem by clearing it there before it is calculated
based on the ASE_MT and ASE_MIPS16E2 flags, making assembly fail as
expected:
$ as -32 -mips32r3 -mmt -mips16 -mmips16e2 -o foo.o foo.s
foo.s: Assembler messages:
foo.s:2: Error: opcode not supported on this processor: mips32r3 (mips32r3) `evpe'
$ as -32 -mips32r3 -mmt -mips16 -mmips16e2 -o bar.o bar.s
bar.s: Assembler messages:
bar.s:2: Error: opcode not supported on this processor: mips32r3 (mips32r3) `dvpe'
$
gas/
* config/tc-mips.c (mips_set_ase): Clear the ASE_MIPS16E2_MT
flag before recalculating.
* testsuite/gas/mips/mips16e2-mt-err.d: New test.
* testsuite/gas/mips/mips16e2-mt-err.l: New stderr output.
* testsuite/gas/mips/mips16e2-mt-err.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
This patch add assembler and disassembler support for new Dot Product
Extension.
The support can be enabled through the new "+dotprod" extension.
include/
* opcode/arm.h (FPU_NEON_EXT_DOTPROD): New macro.
(FPU_ARCH_DOTPROD_NEON_VFP_ARMV8): New macro.
gas/
* config/tc-arm.c (fpu_neon_ext_dotprod): New variable.
(neon_scalar_for_mul): Improve comments.
(do_neon_dotproduct): New function to encode Dot Product instructions.
(do_neon_dotproduct_s): Wrapper function for signed Dot Product
instructions.
(do_neon_dotproduct_u): Wrapper function for unsigned Dot Product
instructions.
(insns): New entries for vsdot and vudot.
(arm_extensions): New entry for "dotprod".
* doc/c-arm.texi: Document new "dotprod" extension.
* testsuite/gas/arm/dotprod.s: New test source.
* testsuite/gas/arm/dotprod-illegal.s: New test source.
* testsuite/gas/arm/dotprod.d: New test.
* testsuite/gas/arm/dotprod-thumb2.d: New test.
* testsuite/gas/arm/dotprod-illegal.d: New test.
* testsuite/gas/arm/dotprod-legacy-arch.d: New test.
* testsuite/gas/arm/dotprod-illegal.l: New error file.
* testsuite/gas/arm/dotprod-legacy-arch.l: New error file.
opcodes/
* arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
Add GAS tests to verify Imagination interAptiv MR2 instruction assembly,
disassembly and ELF object file flags.
Add LD tests to verify Imagination interAptiv MR2 ELF object file
link-time compatibility and flag merging/propagation. Use the framework
enhancement added with commit 7575e6a752 ("MIPS/LD/testsuite:
mips-elf-flags: Add MIPS ABI Flags handling").
gas/
* testsuite/gas/mips/elf_mach_interaptiv-mr2.d: New test.
* testsuite/gas/mips/save-err.d: New test.
* testsuite/gas/mips/save-sub.d: New test.
* testsuite/gas/mips/interaptiv-mr2@save.d: New test.
* testsuite/gas/mips/mips1@save-sub.d: New test.
* testsuite/gas/mips/mips2@save-sub.d: New test.
* testsuite/gas/mips/mips3@save-sub.d: New test.
* testsuite/gas/mips/mips4@save-sub.d: New test.
* testsuite/gas/mips/mips5@save-sub.d: New test.
* testsuite/gas/mips/mips32@save-sub.d: New test.
* testsuite/gas/mips/mips64@save-sub.d: New test.
* testsuite/gas/mips/mips16@save-sub.d: New test.
* testsuite/gas/mips/mips16e@save-sub.d: New test.
* testsuite/gas/mips/r3000@save-sub.d: New test.
* testsuite/gas/mips/r3900@save-sub.d: New test.
* testsuite/gas/mips/r4000@save-sub.d: New test.
* testsuite/gas/mips/vr5400@save-sub.d: New test.
* testsuite/gas/mips/interaptiv-mr2@save-sub.d: New test.
* testsuite/gas/mips/sb1@save-sub.d: New test.
* testsuite/gas/mips/octeon2@save-sub.d: New test.
* testsuite/gas/mips/octeon3@save-sub.d: New test.
* testsuite/gas/mips/xlr@save-sub.d: New test.
* testsuite/gas/mips/r5900@save-sub.d: New test.
* testsuite/gas/mips/mips16e2-copy.d: New test.
* testsuite/gas/mips/mips16e2-copy-err.d: New test.
* testsuite/gas/mips/save.d: Remove `MIPS16e' from the `name'
option. Adjust for trailing padding change.
* testsuite/gas/mips/mips16e2-copy-err.l: New stderr output.
* testsuite/gas/mips/save-sub.s: New test source.
* testsuite/gas/mips/mips16e2-copy.s: New test source.
* testsuite/gas/mips/mips16e2-copy-err.s: New test source.
* testsuite/gas/mips/save.s: Update description, change trailing
padding and remove trailing white space.
* testsuite/gas/mips/mips.exp: Expand `save' and `save-err'
tests across the regular MIPS interAptiv MR2 architecture. Run
the new tests.
ld/
* testsuite/ld-mips-elf/mips-elf-flags.exp: Add interAptiv MR2
tests.
Define a new regular MIPS and MIPS16 interAptiv MR2 test architecture
and adjust existing tests now run against these architectures
accordingly.
This change causes new test failures:
FAIL: MIPS jal-svr4pic (interaptiv-mr2)
FAIL: MIPS jal-svr4pic noreorder (interaptiv-mr2)
with the `mips-sgi-irix5' and `mips-sgi-irix6' targets, which are
consistent with the remaining architecture results for these cases, that
do not take into account the lack of R_MIPS_JALR relocations produced by
GAS for these targets. As a preexisting issue these failures are not
addressed with this change.
gas/
* testsuite/gas/mips/mips.exp (interaptiv-mr2): New architecture.
(mips16e2-interaptiv-mr2): Likewise.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro.d: New
test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro-t.d:
New test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro-e.d:
New test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-t.d:
New test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-e.d:
New test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-64.d: New
test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-sub.d: New
test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-sub.d: New
test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-64-sub.d:
New test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e2-mt-sub.d:
New test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-asmacro.d:
New test.
* testsuite/gas/mips/interaptiv-mr2@mcu.d: New test.
* testsuite/gas/mips/interaptiv-mr2@isa-override-1.d: New test.
* testsuite/gas/mips/interaptiv-mr2@isa-override-2.d: New test.
* testsuite/gas/mips/attr-gnu-4-5.d: Ignore any number of ASE
flag lines present rather than just one.
* testsuite/gas/mips/attr-gnu-4-6.d: Likewise.
* testsuite/gas/mips/attr-gnu-4-7.d: Likewise.
* testsuite/gas/mips/attr-none-o32-fp64-nooddspreg.d: Likewise.
* testsuite/gas/mips/attr-none-o32-fp64.d: Likewise.
* testsuite/gas/mips/attr-none-o32-fpxx.d: Likewise.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro.l: New
stderr output.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro-t.l:
New stderr output.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro-e.l:
New stderr output.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-t.l:
New stderr output.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-e.l:
New stderr output.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-sub.l: New
stderr output.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-sub.l: New
stderr output.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-64-sub.l:
New stderr output.
* testsuite/gas/mips/interaptiv-mr2@isa-override-1.l: New stderr
output.
* testsuite/gas/mips/interaptiv-mr2@isa-override-2.l: New stderr
output.
Add support for the Imagination interAptiv MR2 MIPS32r3 processor with
the MIPS16e2 ASE as per documentation, including in particular:
1. Support for implementation-specific interAptiv MR2 COPYW and UCOPYW
MIPS16e2 instructions[1], for assembly and disassembly,
2. Support for implementation-specific interAptiv MR2 SAVE and RESTORE
regular MIPS instructions[2], for assembly and disassembly,
3. ELF binary file annotation for the interAptiv MR2 MIPS architecture
extension.
4. Support for interAptiv MR2 architecture selection for assembly, in
the form of the `-march=interaptiv-mr2' command-line option and its
corresponding `arch=interaptiv-mr2' setting for the `.set' and
`.module' pseudo-ops.
5. Support for interAptiv MR2 architecture selection for disassembly,
in the form of the `mips:interaptiv-mr2' target architecture, for
use e.g. with the `-m' command-line option for `objdump'.
Parts of this change by Matthew Fortune and Andrew Bennett.
References:
[1] "MIPS32 interAptiv Multiprocessing System Software User's Manual",
Imagination Technologies Ltd., Document Number: MD00904, Revision
02.01, June 15, 2016, Section 24.3 "MIPS16e2 Implementation Specific
Instructions", pp. 878-883
[2] same, Chapter 25 "Implementation-specific Instructions", pp. 911-917
include/
* elf/mips.h (E_MIPS_MACH_IAMR2): New macro.
(AFL_EXT_INTERAPTIV_MR2): Likewise.
* opcode/mips.h: Document new operand codes defined.
(INSN_INTERAPTIV_MR2): New macro.
(INSN_CHIP_MASK): Adjust accordingly.
(CPU_INTERAPTIV_MR2): New macro.
(cpu_is_member) <CPU_INTERAPTIV_MR2>: New case.
(MIPS16_ALL_ARGS): Rename to...
(MIPS_SVRS_ALL_ARGS): ... this.
(MIPS16_ALL_STATICS): Rename to...
(MIPS_SVRS_ALL_STATICS): ... this.
bfd/
* archures.c (bfd_mach_mips_interaptiv_mr2): New macro.
* cpu-mips.c (I_interaptiv_mr2): New enum value.
(arch_info_struct): Add "mips:interaptiv-mr2" entry.
* elfxx-mips.c (_bfd_elf_mips_mach) <E_MIPS_MACH_IAMR2>: New
case.
(mips_set_isa_flags) <bfd_mach_mips_interaptiv_mr2>: Likewise.
(bfd_mips_isa_ext) <bfd_mach_mips_interaptiv_mr2>: Likewise.
(print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise.
(mips_mach_extensions): Add `bfd_mach_mipsisa32r3' and
`bfd_mach_mips_interaptiv_mr2' entries.
* bfd-in2.h: Regenerate.
opcodes/
* mips-formats.h (INT_BIAS): New macro.
(INT_ADJ): Redefine in INT_BIAS terms.
* mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
(mips_print_save_restore): New function.
(print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
(validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
call.
(print_insn_args): Handle OP_SAVE_RESTORE_LIST.
(print_mips16_insn_arg): Call `mips_print_save_restore' for
OP_SAVE_RESTORE_LIST handling, factored out from here.
* mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
(RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
(mips_builtin_opcodes): Add "restore" and "save" entries.
* mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
(IAMR2): New macro.
(mips16_opcodes): Add "copyw" and "ucopyw" entries.
binutils/
* readelf.c (get_machine_flags) <E_MIPS_MACH_IAMR2>: New case.
(print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise.
* NEWS: Mention Imagination interAptiv MR2 processor support.
gas/
* config/tc-mips.c (validate_mips_insn): Handle
OP_SAVE_RESTORE_LIST specially.
(mips_encode_save_restore, mips16_encode_save_restore): New
functions.
(match_save_restore_list_operand): Factor out SAVE/RESTORE
operand insertion into the instruction word or halfword to these
new functions.
(mips_cpu_info_table): Add "interaptiv-mr2" entry.
* doc/c-mips.texi (MIPS Options): Add `interaptiv-mr2' to the
`-march=' argument list.
The symbol address in .eh_frame may be adjusted in
_bfd_elf_discard_section_eh_frame, and the content of .eh_frame will be
adjusted in _bfd_elf_write_section_eh_frame. Therefore, we cannot insert
a relocation whose addend symbol is in .eh_frame. Othrewise, the value
may be adjusted twice.
bfd/ChangeLog
2017-06-26 Kuan-Lin Chen <rufus@andestech.com>
* elfnn-riscv.c (perform_relocation): Support the new
R_RISCV_32_PCREL relocation.
(riscv_elf_relocate_section): Likewise.
* elfxx-riscv.c (howto_table): Likewise.
(riscv_reloc_map): Likewise.
* bfd-in2.h (BFD_RELOC_RISCV_32_PCREL): New relocation.
* libbfd.h: Regenerate.
gas/ChangeLog
2017-06-26 Kuan-Lin Chen <rufus@andestech.com>
* config/tc-riscv.c (md_apply_fix) [BFD_RELOC_32]: Convert to a
R_RISCV_32_PCREL relocation.
include/ChangeLog
2017-06-26 Kuan-Lin Chen <rufus@andestech.com>
* elf/riscv.h (R_RISCV_32_PCREL): New.
The .symver directive on common symbol creates a new common symbol,
which shouldn't be allowed, similar to alias on common symbol:
$ cat y.S
.comm bar,8,8
.set bar1,bar
$ as -o y.o y.S
y.S: Assembler messages:
y.S:2: Error: `bar1' can't be equated to common symbol 'bar'
$
PR gas/21661
* config/obj-elf.c (obj_elf_symver): Don't allow .symver with
common symbol.
(elf_frob_symbol): Likewise.
* testsuite/gas/elf/elf.exp: Run pr21661.
* testsuite/gas/elf/pr21661.d: New file.
* testsuite/gas/elf/pr21661.s: Likewise.
ARC cpus do not accept any jump or instructions with long immediate
into the delay slots.
gas/
2017-06-07 Claudiu Zissulescu <claziss@synopsys.com>
* /config/tc-arc.c (is_br_jmp_insn_p): Update macro with known
instructions to be accounted as jumps.
(assemble_insn): Check for limms into the delay slots. Emit an
error if so.
* testsuite/gas/arc/asm-errors-3.d: New file.
* testsuite/gas/arc/asm-errors-3.err: Likewise.
* testsuite/gas/arc/asm-errors-3.s: Likewise.
=== Context ===
This patch is part of a patch series to add support for ARMv8-R
architecture. Its purpose is to add support for ARM Cortex-R52
processor.
=== Patch description ===
This patch adds support for Cortex-R52 as an ARMv8-R processor with CRC
extensions.
2017-06-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* NEWS: Mention support of ARM Cortex-R52 processor.
* config/tc-arm.c (arm_cpus): Add entry for ARM Cortex-R52 processor.
* doc/c-arm.texi: Mention support for -mcpu=cortex-r52.
=== Context ===
This patch is part of a patch series to add support for ARMv8-R
architecture. Its purpose is to add support for ARMv8-R in GAS:
instructions, build attributes and readelf.
=== Patch description ===
Although some differences exist for system registers, from GAS point of
view ARMv8-R supports the same instructions as ARMv8-A Aarch32 state
and a subset of its extensions. This patch therefore introduce a new
feature bit to distinguish the availability of the pan, ras and rdma
extensions between ARMv8-A and ARMv8-R and allow crypto, fp and simd
extensions to be used by ARMv8-R.
Most of the changes are then in the testsuite to (i) rename source files
and error output to be shared between ARMv8-A and ARMv8-R, (ii) rename
files with expected output for ARMv8-A build attributes and (iii) add
new files with expected output for ARMv8-R build attributes.
2017-06-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
binutils/
* readelf.c (arm_attr_tag_CPU_arch): Fill value for ARMv8-R.
gas/
* NEWS: Mention support for ARMv8-R architecture.
* config/tc-arm.c (arm_archs): Add entry for ARMv8-R.
(arm_extensions): Restrict pan, ras and rdma extension to
ARMv8-A and make crypto, fp and simd extensions available to
ARMv8-R.
(cpu_arch_ver): Add entry for ARMv8-R.
(aeabi_set_public_attributes): Update gas_assert for Tag_DIV_use
logic.
* testsuite/gas/arm/armv8-a+fp.s: Rename into ...
* testsuite/gas/arm/armv8-ar+fp.s: This. Remove .arch directive.
* testsuite/gas/arm/armv8-a+fp.d: Specify source to assemble and
architecture to assemble for.
* testsuite/gas/arm/armv8-r+fp.d: New.
* testsuite/gas/arm/armv8-a+simd.s: Rename into ...
* testsuite/gas/arm/armv8-ar+simd.s: This. Remove .arch directive.
* testsuite/gas/arm/armv8-a+simd.d: Specify source to assemble and
architecture to assemble for.
* testsuite/gas/arm/armv8-r+simd.d: New.
* testsuite/gas/arm/armv8-a-bad.s: Rename into ...
* testsuite/gas/arm/armv8-ar-bad.s: This. Remove .arch directive.
* testsuite/gas/arm/armv8-a-bad.l: Rename into ...
* testsuite/gas/arm/armv8-ar-bad.l: This. Decrement line number by 1.
* testsuite/gas/arm/armv8-a-bad.d: Specify source to assemble,
architecture to assemble for and adjust error output file.
* testsuite/gas/arm/armv8-r-bad.d: New.
* testsuite/gas/arm/armv8-a-barrier.s: Rename into ...
* testsuite/gas/arm/armv8-ar-barrier.s: This.
* testsuite/gas/arm/armv8-a-barrier-arm.d: Adjust source.
* testsuite/gas/arm/armv8-a-barrier-thumb.d: Likewise.
* testsuite/gas/arm/armv8-r-barrier-arm.d: New.
* testsuite/gas/arm/armv8-r-barrier-thumb.d: New.
* testsuite/gas/arm/armv8-a-it-bad.s: Rename into ...
* testsuite/gas/arm/armv8-ar-it-bad.s: This. Remove .arch directive.
* testsuite/gas/arm/armv8-a-it-bad.l: Rename into ...
* testsuite/gas/arm/armv8-ar-it-bad.l: This. Decrement line number
by 1.
* testsuite/gas/arm/armv8-a-it-bad.d: Specify source to assemble,
architecture to assemble for and adjust error output file.
* testsuite/gas/arm/armv8-r-it-bad.d: New.
* testsuite/gas/arm/armv8-a.s: Rename into ...
* testsuite/gas/arm/armv8-ar.s: This. Remove .arch directive.
* testsuite/gas/arm/armv8-a.d: Specify source to assemble and
architecture to assemble for.
* testsuite/gas/arm/armv8-r.d: New.
* testsuite/gas/arm/attr-march-armv8-r+crypto.d: New.
* testsuite/gas/arm/attr-march-armv8-r+fp.d: New.
* testsuite/gas/arm/attr-march-armv8-r+simd.d: New.
* testsuite/gas/arm/attr-march-armv8-r.d: New.
* testsuite/gas/arm/crc32.s: Rename into ...
* testsuite/gas/arm/crc32-armv8-ar.s: This.
* testsuite/gas/arm/crc32.d: Rename into ...
* testsuite/gas/arm/crc32-armv8-a.d: This. Specify source to assemble.
* testsuite/gas/arm/crc32-armv8-r.d: New.
* testsuite/gas/arm/crc32-bad.s: Rename into ...
* testsuite/gas/arm/crc32-armv8-ar-bad.s: This.
* testsuite/gas/arm/crc32-bad.d: Rename into ...
* testsuite/gas/arm/crc32-armv8-a-bad.d: This. Specify source to
assemble.
* testsuite/gas/arm/crc32-armv8-r-bad.d: New.
* testsuite/gas/arm/mask_1.s: Rename into ...
* testsuite/gas/arm/mask_1-armv8-ar.s: This.
* testsuite/gas/arm/mask_1.d: Rename into ...
* testsuite/gas/arm/mask_1-armv8-a.d: This. Specify source to
assemble.
* testsuite/gas/arm/mask_1-armv8-r.d: new.
include/
* elf/arm.h (TAG_CPU_ARCH_V8R): New macro.
* opcode/arm.h (ARM_EXT2_V8A): New macro.
(ARM_AEXT2_V8A): Rename into ...
(ARM_AEXT2_V8AR): This.
(ARM_AEXT2_V8A): New macro.
(ARM_AEXT_V8R): New macro.
(ARM_AEXT2_V8R): New macro.
(ARM_ARCH_V8R): New macro.
=== Context ===
This patch is part of a patch series to add support for ARMv8-R
architecture. Its purpose is to remove special casing for ARMv6S-M
autodetection.
=== Motivation ===
Currently, SWI and SVC mnemonics are enabled for ARMv4T and successor
architectures with extra checks in the handler function (do_t_swi) to
give an error message when ARMv6-M is targeted and some more special
casing in aeabi_set_public_attributes. This was made to exclude these
mnemonics for ARMv6-M unless the OS extension is in use.
However this logic is superfluous: there is already code to check
whether an instruction is available based on the feature bit it is part
of and whether the targeted architecture has that feature bit. This
patch aims at removing that unneeded complexity.
=== Patch description ===
The OS extension is already limited to the ARMv6-M architecture so all
this patch does is redefined availability of the ARM_EXT_OS feature bit
to not be present for ARM_ARCH_V6M. ARM_ARCH_V6SM does not need any
change either because it already includes ARM_EXT_OS.
The patch also make sure that the error message that was given by
do_t_swi when SWI/SVC is unavailable is still the same by detecting the
situation in md_assemble.
2017-06-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (arm_ext_v6m): Delete.
(arm_ext_v7m): Delete.
(arm_ext_m): Remove ARM_EXT_OS from the set of feature defined M
profile.
(arm_arch_v6m_only): Delete.
(do_t_swi): Remove special case for ARMv6S-M.
(md_assemble): Display error message previously in do_t_swi when
SVC is not available.
(insns): Guard swi and svc by arm_ext_os for Thumb mode.
(aeabi_set_public_attributes): Remove special case for ARMv6S-M.
include/
* opcode/arm.h (ARM_AEXT_V4TxM): Add ARM_EXT_OS bit to the set.
(ARM_AEXT_V4T): Likewise.
(ARM_AEXT_V5TxM): Likewise.
(ARM_AEXT_V5T): Likewise.
(ARM_AEXT_V6M): Mask off ARM_EXT_OS bit.
=== Context ===
This patch is part of a patch series to add support for ARMv8-R
architecture. Its purpose is to rework the Tag_CPU_arch build attribute
value selection to (i) match architecture or CPU if specified by user
without any need for hack and (ii) match an architecture with all the
features used if in autodetection mode or return an error.
=== Motivation ===
Currently, Tag_CPU_arch build attribute value selection assumes that an
architecture is always a superset of architectures released earlier. As
such, the logic is to browse architectures in chronological order of
release and selecting the Tag_CPU_arch value of the last one to
contribute a feature used[1]/requested[2] not contributed by earlier
architectures.
[1] in case of autodetection mode
[2] otherwise, ie. in case of -mcpu/-march or associated directives
This logic fails the two objectives mentionned in the Context section.
First, due to the assumption it does an architecture can be selected
while not having all the features used/requested which fails the second
objective. Second, not doing an exact match when an architecture or CPU
is selected by the user means the wrong value is chosen when a later
architecture provides a subset of the feature bits of an earlier
architecture. This is the case for the implementation of ARMv8-R (see
later patch).
An added benefit of this patch is that it is possible to easily generate
more consistent build attribute by setting the feature bits from the
architecture matched in aeabi_set_public_attributes in autodetection
mode. This is better done as a separate patch because lots of testcase'
expected results must then be updated accordingly.
=== Patch description ===
The patch changes the main logic for Tag_CPU_arch and
Tag_CPU_arch_profile
values selection to:
- look for an exact match in case an architecture or CPU was specified
on the command line or in a directive
- select the first released architecture that provides a superset of the
feature used in the autodetection case
- select the most featureful architecture in case of -march=all
The array cpu_arch_ver is updated to include all architectures in order
to make the first point work.
Note that when looking for an exact match, the architecture with
selected extension is tried first and then only the architecture. This
is because some architectures are exactly equivalent to an earlier
architecture with its extensions selected. ARMv6S-M (= ARMv6-M + OS
extension) and ARMv6KZ (ARMv6K + security extension) are two such
examples.
Other adjustments are also necessary in aeabi_set_public_attributes to
make this change work.
1) The logic to set Tag_ARM_ISA_use and Tag_THUMB_ISA_use must check the
absence of feature bit used/requested to decide whether to give the
default value for empty files (see EABI attribute defaults test). It was
previously checking that arch == 0 which would only happen if no feature
bit could be matched by any architecture, ie there is no feature bit to
match.
2) A fallback to a superset match must exist when no_cpu_selected ()
returns true. This is because aeabi_set_public_attributes is called
again after relaxation and at this point selected_cpu is set from the
previous execution of that function. There is therefore no way to check
whether the user specified an architecture or CPU.
3) Tag_CPU_arch lines are removed from expected output when the
detected architecture should be pre-ARMv4, since 0 is the Tag_CPU_arch
value for pre-ARMv4 architectures and default value for an absent entry
is 0.
2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (fpu_any): Defined from FPU_ANY.
(cpu_arch_ver): Add all architectures and sort by release date.
(have_ext_for_needed_feat_p): New.
(get_aeabi_cpu_arch_from_fset): New.
(aeabi_set_public_attributes): Call above function to determine
Tag_CPU_arch and Tag_CPU_arch_profile values. Adapt Tag_ARM_ISA_use
and Tag_THUMB_ISA_use selection logic to check absence of feature bit
accordingly.
* testsuite/gas/arm/attr-march-armv1.d: Fix expected Tag_CPU_arch build
attribute value.
* testsuite/gas/arm/attr-march-armv2.d: Likewise.
* testsuite/gas/arm/attr-march-armv2a.d: Likewise.
* testsuite/gas/arm/attr-march-armv2s.d: Likewise.
* testsuite/gas/arm/attr-march-armv3.d: Likewise.
* testsuite/gas/arm/attr-march-armv3m.d: Likewise.
* testsuite/gas/arm/pr12198-2.d: Likewise.
include/
* opcode/arm.h (FPU_ANY): New macro.
Update x86 assembler and disassembler for CET v2.0:
https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf
1. incsspd and incsspq are changed to take a register opeand with a
different opcode.
2. setssbsy is changed to take no opeand with a different opcode.
gas/
* testsuite/gas/i386/cet-intel.d: Updated.
* testsuite/gas/i386/cet.d: Likewise.
* testsuite/gas/i386/x86-64-cet-intel.d: Likewise.
* testsuite/gas/i386/x86-64-cet.d: Likewise.
* testsuite/gas/i386/cet.s: Update incsspd and setssbsy tests.
* testsuite/gas/i386/x86-64-cet.s: Likewise.
opcodes/
* i386-dis.c (RM_0FAE_REG_5): Removed.
(PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
(PREFIX_MOD_3_0F01_REG_5_RM_0): New.
(PREFIX_MOD_3_0FAE_REG_5): Likewise.
(prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
PREFIX_MOD_3_0F01_REG_5_RM_0.
(prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
PREFIX_MOD_3_0FAE_REG_5.
(mod_table): Update MOD_0FAE_REG_5.
(rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
* i386-opc.tbl: Update incsspd, incsspq and setssbsy.
* i386-tbl.h: Regenerated.
=== Context ===
This patch is part of a patch series to add support for ARMv8-R
architecture. Its purpose is to allow ARMv7 to be selected in automatic
architecture selection in presence of Thumb division instructions.
=== Motivation ===
any-idiv.d and automatic-sdiv.d testcases in GAS testsuite expect
autodetection code to select ARMv7 in presence of Thumb integer
division. However, the definition of ARM_AEXT_V7 and thus ARM_ARCH_V7 do
not contain these instructions and the idiv extension is only available
for ARMv7-A and ARMv7-R. Therefore, under the stricter automatic
detection code proposed in the subsequent patch of the series ARMv7 is
refused if a Thumb division instruction is present.
=== Patch description ===
This patch adds a new "idiv" extension after the existing one that is
available to all ARMv7 targets. This new entry is ignored by all current
code parsing arm_extensions such that it would be unavailable on the
command-line and remain a purely internal hack, easily removed in favor
of a better solution later. This is considered though by the subsequent
patch reworking automatic detection of build attributes such that ARMv7
is allowed to match in present of Thumb division instructions. For good
measure, comments are added in all instances of code browsing
arm_extensions to mention the expected behavior in case of duplicate
entries as well as a new testcase.
2017-06-20 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (arm_extensions): New duplicate idiv entry to enable
Thumb division for ARMv7 architecture.
(arm_parse_extension): Document expected behavior for duplicate
entries.
(s_arm_arch_extension): Likewise.
* testsuite/gas/arm/forbid-armv7-idiv-ext.d: New test.
* testsuite/gas/arm/forbid-armv7-idiv-ext.l: New expected output for
above test.
=== Context ===
This patch is part of a patch series to add support for ARMv8-R
architecture. Its purpose is to set the feature bits on which to decide
what the build attributes should be according to the mode
(autodetection, user specified architecture or CPU, or
-march/-mcpu=all).
=== Motivation ===
Currently, the flags variable which is used to determine the build
attribute is constructed from the instruction used (arm_arch_used and
thumb_arch_used) as well as the user specified architecture or CPU
(selected_cpu). This means when several .arch are specified the
resulting feature bits can be such that no architecture provide them
all and can thus result in incorrect Tag_CPU_arch. See for instance
what having both .arch armv8-a and .arch armv8-m.base would result in.
This is not caught by the testsuite because of further bugs in the
Tag_CPU_arch build attribute value selection logic (see next patch in
the series).
=== Patch description ===
As one would expect, this patch solves the problem by setting flags
from feature bits used if in autodetection mode [1] and from
selected_cpu otherwise. The logic to set arm_ext_v1, arm_ext_v4t and
arm_ext_os feature bits is also moved to only run in autodetection mode
since otherwise the architecture or CPU would have a consistent set of
feature bits already.
[1] No architecture or CPU was specified by the user
2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (aeabi_set_public_attributes): Populate flags from
feature bits used or selected_cpu depending on whether a CPU was
selected by the user.
=== Context ===
This patch is part of a patch series to add support for ARMv8-R
architecture. Its purpose is to simplify the logic to decide whether to
set Tag_DSP_extension.
=== Motivation ===
To decide whether to set Tag_DSP_extension, the current code was
checking whether the flags had DSP instruction but the architecture
selected for Tag_CPU_arch did not have any. This was necessary because
extension feature bit were not available separately. This is no longer
necessary and can be simplified.
=== Patch description ===
The patch change the logic to set Tag_DSP_extension to check whether any
DSP feature bit is set in the extension feature bit, as per the
definition of that build attribute. The patch also removes all
definitions of arm_arch which is now unneeded.
2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (aeabi_set_public_attributes): Test *mcpu_ext_opt to
decide whether to set Tag_DSP_extension build attribute value. Remove
now useless arm_arch variable.
=== Context ===
This patch is part of a patch series to add support for ARMv8-R
architecture. Its purpose is to keep the distinction between
architecture feature bits and extension ones after parsing has occured.
=== Motivation ===
This distinction is necessary to allow the Tag_CPU_arch build attribute
value to be exactly as per the architecture of the selected CPU. With
mixed architecture and extension feature bit, it is impossible to find
an architecture with an exact match of feature bit and the build
attribute value logic must then select the closest match which might not
be the right architecture. The previous patch in the patch series makes
the distinction possible when parsing -mcpu and .cpu directives but the
distinction gets lost after. Similarly feature bits contributed by
extensions in -march or .arch_extensions directive are mixed together
with architecture extensions.
=== Patch description ===
The patch adds new feature bit pointer for extension feature bits.
Information from the parsing regarding extensions can then be kept
separate in those. This requires adapting arm_parse_extension to deal
with two feature bits, allowing the architecture bits to be marked as
const. It also requires extra care when setting cpu_variant and
selected_cpu because the extension bits are optional since there might
not be any extension in use.
Note that contrary to cpu feature bits, the extension feature bits are
made read/write and are always dynamically allocated. This allows to
unconditionally free them in arm_md_post_relax added for this occasion,
thereby fixing a longstanding memory leak when arm_parse_extension was
invoked (XNEW of ext_fset without corresponding XDELETE).
Introduction of arm_md_post_relax is necessary to only free the
extension feature bits after aeabi_set_attribute_string has been called
for the last time.
2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (dyn_mcpu_ext_opt): New static variable.
(dyn_march_ext_opt): Likewise.
(md_begin): Copy extension feature bits alongside architecture ones.
Merge extensions feature bits in selected_cpu and cpu_variant if there
is some.
(arm_parse_extension): Pass architecture and extension feature bits in
separate parameters, with architecture bits being read only. Update
**opt_p directly rather than *ext_set and initialize it if needed.
(arm_parse_cpu): Stop merging architecture and extension feature bits
and instead use mcpu_cpu_opt and dyn_mcpu_ext_opt to memorize them
respectively. Adapt to change in parameters of arm_parse_extension.
(arm_parse_arch): Adapt to change in parameters of arm_parse_extension.
(aeabi_set_attribute_string): Make function static.
(arm_md_post_relax): New function.
(s_arm_cpu): Stop merging architecture and extension feature bits and
instead use mcpu_cpu_opt and dyn_mcpu_ext_opt to memorize them
respectively. Merge extension feature bits in cpu_variant
if there is any.
(s_arm_arch): Reset extension feature bit. Set selected_cpu from
*mcpu_cpu_opt and cpu_variant from selected_cpu and *mfpu_opt for
consistency with s_arm_cpu.
(s_arm_arch_extension): Update *dyn_mcpu_ext_opt rather than
selected_cpu, allocating it before hand if needed. Set selected_cpu
from it and then cpu_variant.
(s_arm_fpu): Merge *mcpu_ext_opt feature bits if any in cpu_variant.
* config/tc-arm.h (md_post_relax_hook): Set to arm_md_post_relax.
(aeabi_set_public_attributes): Delete external declaration.
(arm_md_post_relax): Declare externally.
=== Context ===
This patch is part of a patch series to add support for ARMv8-R
architecture. Its purpose is to distinguish for a CPU the feature bits
coming from its architecture from the feature bits coming from
extension(s) available in this CPU.
=== Motivation ===
This distinction is necessary to allow the Tag_CPU_arch build attribute
value to be exactly as per the architecture of the selected CPU. With
mixed architecture and extension feature bit, it is impossible to find
an architecture with an exact match of feature bit and the build
attribute value logic must then select the closest match which might not
be the right architecture.
=== Patch description ===
The patch creates a new field in the arm_cpus table to hold the feature
set for the extensions available in each CPU. The existing architecture
feature set is then updated to remove those feature bit. The patch also
takes advantage of all the lines being changed to reindent the whole
table.
Note: This patch *adds* a memory leak due to mcpu_cpu_opt sometimes
pointing to dynamically allocated feature bits which is never freeed.
The subsequent patch in the series solves this issue as well as a
preexisting identical issue in arm_parse_extension. The patches are kept
separate for ease of review since they are both big enough already.
2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (struct arm_cpu_option_table): New ext field.
(ARM_CPU_OPT): Add parameter to set new ext field and reorder canonical
name field just after the name field.
(arm_cpus): Move extension feature bit from value field to ext field,
reorder parameter according to changes in ARM_CPU_OPT and reindent.
(arm_parse_cpu): Point mcpu_cpu_opt to a bitfield merging the value and
ext field from the selected arm_cpus entry.
(s_arm_cpu): Likewise.
Get rid of the assumption that XCHAL_* macros are preprocessor
constants: don't use them in preprocessor conditionals or in static
variable initializers.
2017-06-14 Max Filippov <jcmvbkbc@gmail.com>
bfd/
* elf32-xtensa.c (elf_xtensa_be_plt_entry,
elf_xtensa_le_plt_entry): Add dimension for the ABI to arrays,
keep both windowed and call0 ABI PLT definitions.
(elf_xtensa_create_plt_entry): Use selected ABI to choose upper
elf_xtensa_*_plt_entry endex.
(ELF_MAXPAGESIZE): Fix at minimal supported MMU page size.
gas/
* config/tc-xtensa.c (density_supported, xtensa_fetch_width,
absolute_literals_supported): Leave definitions uninitialized.
(directive_state): Leave entries for directive_density and
directive_absolute_literals initialized to false.
(xg_init_global_config, xtensa_init): New functions.
* config/tc-xtensa.h (TARGET_BYTES_BIG_ENDIAN): Define as 0.
(HOST_SPECIAL_INIT): New definition.
(xtensa_init): New declaration.
Historically the arc abi demanded that a GOT[0] should be referencible as
[pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a GOTPC reference to
_GLOBAL_OFFSET_TABLE_.
This is no longer the case and uClibc and upcomming GNU libc don't expect this
to happen.
gas/ChangeLog:
Vineet Gupta <vgupta@synopsys.com>
Cupertino Miranda <cmiranda@synopsys.com>
* config/tc-arc.c (md_undefined_symbol): Changed.
* config/tc-arc.h (DYNAMIC_STRUCT_NAME): Removed.
* config/tc-aarch64.c (reg_entry_reg_names): Add IP0,
IP1, FP, and LR as register aliases of register 16, 17, 29
and 30 respectively.
* testsuite/gas/aarch64/diagnostic.l: Remove diagnostic
prohibiting register 'lr' which is now an alias.
* testsuite/gas/aarch64/diagnostic.s: Remove instruction
utilizing register 'lr' which is now an alias.
For Thumb mode, since ARMv8-A, REG_SP is allowed in most of the places in
Rd/Rt/Rt2 etc while it was disallowed before ARMv8-A, and was rejected through
the "reject_bad_reg" macro and several scattered checks.
This patch only rejects REG_SP in "reject_bad_reg" and several related places
for legacy architectures before ARMv8-A. I have checked those affected instructions
, all of them qualify such relaxations.
Testcases adjusted accordingly.
* ld-sp-warn.d was written without .arch and without -march options passed.
By default it assumes all architectures, so I deleted the REG_SP warning
on ldrsb as it's supported on ARMv8-A. There are actually quite a few
seperate tests on other architectures, for example ld-sp-warn-v7.l etc.,
so there the test for ldrsb on legacy architectures are still covered.
* sp-pc-validations-bad-t has been extended to armv8-a.
* strex-bad-t.d restricted on armv7-a.
* Some new tests for REG_SP used as Rd/Rt etc added in sp-usage-thumb2-relax*.
gas/
* config/tc-arm.c (reject_bad_reg): Allow REG_SP on ARMv8-A.
(parse_operands): Allow REG_SP for OP_oRRnpcsp and OP_RRnpcsp on
ARMv8-A.
(do_co_reg): Allow REG_SP for Rd on ARMv8-A.
(do_t_add_sub): Likewise.
(do_t_mov_cmp): Likewise.
(do_t_tb): Likewise.
* testsuite/gas/arm/ld-sp-warn.l: Delete the warning on REG_SP as Rt for
ldrsb.
* testsuite/gas/arm/sp-pc-validations-bad-t-v8a.d: New test.
* testsuite/gas/arm/sp-pc-validations-bad-t-v8a.l: New test.
* testsuite/gas/arm/sp-pc-validations-bad-t.d: Specifies -march=armv7-a.
* testsuite/gas/arm/sp-pc-validations-bad-t.s: Remove ".arch armv7-a".
* testsuite/gas/arm/sp-usage-thumb2-relax-on-v7.d: New test.
* testsuite/gas/arm/sp-usage-thumb2-relax-on-v7.l: New test.
* testsuite/gas/arm/sp-usage-thumb2-relax-on-v8.d: New test.
* testsuite/gas/arm/sp-usage-thumb2-relax.s: New test.
* testsuite/gas/arm/strex-bad-t.d: Specifies -march=armv7-a.
Later CPU generations added optional operands to the ipte/idte
instructions. I've added these with:
https://sourceware.org/ml/binutils/2017-05/msg00316.html ... but
supported the optional operands only with the specific hardware
levels. However, it is more useful to have the optional operands
already in the first versions. Of course they need to be zero there.
Regression-tested with on s390 and s390x. Committed to mainline.
Bye,
-Andreas-
opcodes/ChangeLog:
2017-06-01 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-opc.txt: Support the optional parameters with the first
versions of ipte/idte.
gas/ChangeLog:
2017-06-01 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* testsuite/gas/s390/esa-g5.d: Add ipte tests.
* testsuite/gas/s390/esa-g5.s: Likewise.
* testsuite/gas/s390/zarch-z196.d: Remove ipte tests.
* testsuite/gas/s390/zarch-z196.s: Likewise.
* testsuite/gas/s390/zarch-z990.d: Add idte tests.
* testsuite/gas/s390/zarch-z990.s: Likewise.
* testsuite/gas/s390/zarch-zEC12.d: Remove ipte/idte tests.
* testsuite/gas/s390/zarch-zEC12.s: Likewise.
This patch extracts ARC CPU definitions from gas/config/tc-arc.c (cpu_types)
into a separate file arc-cpu.def. This will allow reuse of CPU type definition
in multiple places where it might be needed, for example in disassembler. This
will help ensure that gas and disassembker use same option values for CPUs.
arc-cpu.def file relies on preprocessor macroses which are defined somewhere
else. This for example multiple C files to include arc-cpu.def, but define
different macroses, therefore creating different structures.
include/ChangeLog:
yyyy-mm-dd Anton Kolesov <anton.kolesov@synopsys.com>
* elf/arc-cpu.def: New file.
gas/ChangeLog:
yyyy-mm-dd Anton Kolesov <anton.kolesov@synopsys.com>
* config/tc-arc.c (cpu_types): Include arc-cpu.def
Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>
This patch adds missing variants of ipte and idte instructions added with later CPU
generations.
ipte got an optional operand with z196 and another one with zEC12.
idte got an optional operand with zEC12
opcodes/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-opc.c: Add new idte/ipte variants.
* s390-opc.txt: Likewise.
gas/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* testsuite/gas/s390/zarch-z196.d: Add new idte/ipte variants.
* testsuite/gas/s390/zarch-z196.s: Likewise.
* testsuite/gas/s390/zarch-zEC12.d: Likewise.
* testsuite/gas/s390/zarch-zEC12.s: Likewise.
So far we only had an instruction flag which made an arbitrary number
of operands optional. This limits error checking capabilities for
instructions marked that way. With this patch the optparm flag only
allows a single optional parameter and another one is added (optparm2)
allowing 2 optional arguments. Hopefully we won't need more than that
in the future. So far there will be only a single use of optparm2.
gas/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/tc-s390.c (md_gather_operands): Support new optparm2
instruction flag.
include/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* opcode/s390.h: Add new instruction flags optparm2.
opcodes/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-dis.c (s390_print_insn_with_opcode): Support new optparm2
instruction flag.
* s390-mkopc.c (main): Recognize the new instruction flag when
parsing instruction list.
The per operand optional flag hasn't been used for quite some time.
Cleanup some remains.
include/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* opcode/s390.h: Remove S390_OPERAND_OPTIONAL.
gas/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/tc-s390.c (md_gather_operands): Remove code dealing with
S390_OPERAND_OPTIONAL.
This patch allows AArch64 GAS defaulting to ILP32 if it is configured with
aarch64*-linux-gnu_ilp32.
"md_after_parse_args" is implemented to update ABI into ILP32 if DEFAULT_ARCH is
"aarch64:32".
gas/
* configure.tgt: Set "arch" to "aarch64" if ${cpu} equals "aarch64".
Recognize the new triplet name aarch64*-linux-gnu_ilp32.
* configure.ac: Output DEFAULT_ARCH macro for AArch64.
* configure: Regenerate.
* config/tc-aarch64.h (aarch64_after_parse_args): New declaration.
(md_after_parse_args): New define.
* config/tc-aarch64.c (aarch64_abi_type): New enumeration
AARCH64_ABI_NONE.
(DEFAULT_ARCH): New define.
(aarch64_abi): Set default value to AARCH64_ABI_NONE.
(aarch64_after_parse_args): New function.
Tested in targets:
sparc-aout sparc-linux sparc-vxworks sparc64-linux
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/sparc/call-relax.d: Support 32-bit targets.
* testsuite/gas/sparc/sparc.exp (gas_64_check): Use -64 to
run asi-bump-warn.
PR ld/21472
ld * emulparams/avrxmega3.sh (RODATA_PM_OFFSET): Set to 0x8000.
* scripttempl/avr.sc
(__RODATA_PM_OFFSET__) [RODATA_PM_OFFSET]: Use RODATA_PM_OFFSET
as default if not already defined.
(.data) [!RODATA_PM_OFFSET]: Don't include .rodata and friends.
(.rodata) [RODATA_PM_OFFSET]: Put at an offset of
__RODATA_PM_OFFSET__.
gas * config/tc-avr.c (mcu_types): Add entries for: attiny416,
attiny417, attiny816, attiny817.
PR gas/21458
* config/tc-arm.c (do_adr): If the ADR involves a thumb function
symbol, ensure that the T bit will be set.
(do_adrl): Likewise.
(do_t_adr): Likewise.
* testsuite/gas/arm/pr21458.s: New test.
* testsuite/gas/arm/pr21458.d: New test driver.
Verify MIPS16e2 ASE instruction assembly, disassembly and object file
flags.
binutils/
* testsuite/binutils-all/mips/mips16-undecoded.d: Add `-mips3'
to `as' flags.
* testsuite/binutils-all/mips/mips16e2-undecoded.d: New test.
* testsuite/binutils-all/mips/mips16e2-extend-insn.d: New test.
* testsuite/binutils-all/mips/mips16-undecoded.s: Remove
`.module mips3'.
* testsuite/binutils-all/mips/mips.exp: Run the new tests.
gas/
* testsuite/gas/mips/mips16e2.d: New test.
* testsuite/gas/mips/mips16e2-mt.d: New test.
* testsuite/gas/mips/mips16e2-sub.d: New test.
* testsuite/gas/mips/mips16e2@mips16e2-sub.d: New test.
* testsuite/gas/mips/mips16e2-mt-sub.d: New test.
* testsuite/gas/mips/mips16e2@mips16e2-mt-sub.d: New test.
* testsuite/gas/mips/mips16e2-hilo.d: New test.
* testsuite/gas/mips/mips16e2-hilo-n32.d: New test.
* testsuite/gas/mips/mips16e2-reloc-error.d: New test.
* testsuite/gas/mips/mips16e2-imm-error.d: New test.
* testsuite/gas/mips/elf_ase_mips16e2.d: New test.
* testsuite/gas/mips/elf_ase_mips16e2-2.d: New test.
* testsuite/gas/mips/elf-rel9-mips16e2.d: New test.
* testsuite/gas/mips/mips16e2-lui.d: New test.
* testsuite/gas/mips/mips16e2@mips32r2-sync.d: New test.
* testsuite/gas/mips/mips16e2@mips32r2-sync-1.d: New test.
* testsuite/gas/mips/mips16e2@lui-2.d: New test.
* testsuite/gas/mips/mips16e2-reloc-error.l: New stderr output.
* testsuite/gas/mips/mips16e2-imm-error.l: New stderr output.
* testsuite/gas/mips/mips16e2@lui-2.l: New stderr output.
* testsuite/gas/mips/mips16e2.s: New test source.
* testsuite/gas/mips/mips16e2-mt.s: New test source.
* testsuite/gas/mips/mips16e2-sub.s: New test source.
* testsuite/gas/mips/mips16e2-mt-sub.s: New test source.
* testsuite/gas/mips/mips16e2-hilo.s: New test source.
* testsuite/gas/mips/mips16e2-reloc-error.s: New test source.
* testsuite/gas/mips/mips16e2-imm-error.s: New test source.
* testsuite/gas/mips/elf-rel9-mips16e2.s: New test source.
* testsuite/gas/mips/mips16e2-lui.s: New test source.
* testsuite/gas/mips/mips.exp: Expand `mips32r2-sync',
`mips32r2-sync-1', `lui-1' and `lui-2' tests across MIPS16e2
architectures. Run the new tests.
Define a new 32-bit and 64-bit MIPS16e2 test architecture and adjust
existing tests now run against these architectures accordingly.
gas/
* testsuite/gas/mips/mips.exp (run_dump_test_arch): Add
`mips16e2@' prefix.
(run_list_test_arch): Likewise.
(mips16e2-32, mips16e2-64): New architectures.
* testsuite/gas/mips/mips16e2-32@mips16-macro.d: New test.
* testsuite/gas/mips/mips16e2-32@mips16-macro-t.d: New test.
* testsuite/gas/mips/mips16e2-32@mips16-macro-e.d: New test.
* testsuite/gas/mips/mips16e2-32@mips16-insn-t.d: New test.
* testsuite/gas/mips/mips16e2-32@mips16-insn-e.d: New test.
* testsuite/gas/mips/mips16e2-32@mips16e-64.d: New test.
* testsuite/gas/mips/mips16e2-32@mips16-sub.d: New test.
* testsuite/gas/mips/mips16e2-32@mips16e-64-sub.d: New test.
* testsuite/gas/mips/mips16e2@relax-swap3.d: New test.
* testsuite/gas/mips/mips16-32@mips16-asmacro.d: Remove `source'
tag. Add `-I$srcdir/$subdir' to `as' flags.
* testsuite/gas/mips/mips16-64@mips16-asmacro.d: Likewise.
* testsuite/gas/mips/mips16e2-32@mips16-macro.l: New stderr
output.
* testsuite/gas/mips/mips16e2-32@mips16-macro-t.l: New stderr
output.
* testsuite/gas/mips/mips16e2-32@mips16-macro-e.l: New stderr
output.
* testsuite/gas/mips/mips16e2-32@mips16-insn-t.l: New stderr
output.
* testsuite/gas/mips/mips16e2-32@mips16-insn-e.l: New stderr
output.
* testsuite/gas/mips/mips16-sub.s: Add `.set nomips16e2'.
* testsuite/gas/mips/mips16e-sub.s: Likewise.
* testsuite/gas/mips/mips16e-64-sub.s: Likewise.
* testsuite/gas/mips/mips16-asmacro.s: Remove `.set mips32'.
* testsuite/gas/mips/mips16-32@mips16-asmacro.s: New test
source.
* testsuite/gas/mips/mips16-64@mips16-asmacro.s: New test
source.
Add MIPS16e2 ASE support as per the architecture specification[1],
including in particular:
1. A new ELF ASE flag to mark MIPS16e2 binaries.
2. MIPS16e2 instruction assembly support, including a relaxation update
to use LUI rather than an LI/SLL instruction pair for loading the
high part of 32-bit addresses.
3. MIPS16e2 instruction disassembly support, including updated rules for
extended forms of instructions that are now subdecoded and therefore
do not alias to the original MIPS16 ISA revision instructions even
for encodings that are not valid in the MIPS16e2 instruction set.
Add `-mmips16e2' and `-mno-mips16e2' GAS command-line options and their
corresponding `mips16e2' and `no-mips16e2' settings for the `.set' and
`.module' pseudo-ops. Control the availability of the MT ASE subset of
the MIPS16e2 instruction set with a combination of these controls and
the preexisting MT ASE controls.
Parts of this change by Matthew Fortune and Andrew Bennett.
References:
[1] "MIPS32 Architecture for Programmers: MIPS16e2 Application-Specific
Extension Technical Reference Manual", Imagination Technologies
Ltd., Document Number: MD01172, Revision 01.00, April 26, 2016
include/
* elf/mips.h (AFL_ASE_MIPS16E2): New macro.
(AFL_ASE_MASK): Adjust accordingly.
* opcode/mips.h: Document new operand codes defined.
(mips_operand_type): Add OP_REG28 enum value.
(INSN2_SHORT_ONLY): Update description.
(ASE_MIPS16E2, ASE_MIPS16E2_MT): New macros.
bfd/
* elfxx-mips.c (print_mips_ases): Handle MIPS16e2 ASE.
opcodes/
* mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
(mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
(print_insn_arg) <OP_REG28>: Add handler.
(validate_insn_args) <OP_REG28>: Handle.
(print_mips16_insn_arg): Handle MIPS16 instructions that require
32-bit encoding and 9-bit immediates.
(print_insn_mips16): Handle MIPS16 instructions that require
32-bit encoding and MFC0/MTC0 operand decoding.
* mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
<'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
(RD_C0, WR_C0, E2, E2MT): New macros.
(mips16_opcodes): Add entries for MIPS16e2 instructions:
GP-relative "addiu" and its "addu" spelling, "andi", "cache",
"di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
"lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
"movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
"pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
instructions, "swl", "swr", "sync" and its "sync_acquire",
"sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
"xori", "dmt", "dvpe", "emt" and "evpe". Add split
regular/extended entries for original MIPS16 ISA revision
instructions whose extended forms are subdecoded in the MIPS16e2
ISA revision: "li", "sll" and "srl".
binutils/
* readelf.c (print_mips_ases): Handle MIPS16e2 ASE.
* NEWS: Mention MIPS16e2 ASE support.
gas/
* config/tc-mips.c (RELAX_MIPS16_ENCODE): Add `e2' flag.
(RELAX_MIPS16_E2): New macro.
(RELAX_MIPS16_PIC, RELAX_MIPS16_SYM32, RELAX_MIPS16_NOMACRO)
(RELAX_MIPS16_USER_SMALL, RELAX_MIPS16_USER_EXT)
(RELAX_MIPS16_DSLOT, RELAX_MIPS16_JAL_DSLOT)
(RELAX_MIPS16_EXTENDED, RELAX_MIPS16_MARK_EXTENDED)
(RELAX_MIPS16_CLEAR_EXTENDED, RELAX_MIPS16_ALWAYS_EXTENDED)
(RELAX_MIPS16_MARK_ALWAYS_EXTENDED)
(RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED, RELAX_MIPS16_MACRO)
(RELAX_MIPS16_MARK_MACRO, RELAX_MIPS16_CLEAR_MACRO): Shift bits.
(mips16_immed_extend): New prototype.
(options): Add OPTION_MIPS16E2 and OPTION_NO_MIPS16E2 enum
values.
(md_longopts): Add "mmips16e2" and "mno-mips16e2" options.
(mips_ases): Add "mips16e2" entry.
(mips_set_ase): Handle MIPS16e2 ASE.
(insn_insert_operand): Explicitly handle immediates with MIPS16
instructions that require 32-bit encoding.
(is_opcode_valid_16): Pass enabled ASE bitmask on to
`opcode_is_member'.
(validate_mips_insn): Explicitly handle immediates with MIPS16
instructions that require 32-bit encoding.
(operand_reg_mask) <OP_REG28>: Add handler.
(match_reg28_operand): New function.
(match_operand) <OP_REG28>: Add handler.
(append_insn): Pass ASE_MIPS16E2 setting to RELAX_MIPS16_ENCODE.
(match_mips16_insn): Handle MIPS16 instructions that require
32-bit encoding and `V' and `u' operand codes.
(mips16_ip): Allow any characters except from `.' in opcodes.
(mips16_immed_extend): Handle 9-bit immediates. Do not shuffle
immediates whose width is not one of these listed.
(md_estimate_size_before_relax): Handle MIPS16e2 relaxation.
(mips_relax_frag): Likewise.
(md_convert_frag): Likewise.
(mips_convert_ase_flags): Handle MIPS16e2 ASE.
* doc/as.texinfo (Target MIPS options): Add `-mmips16e2' and
`-mno-mips16e2' options.
(-mmips16e2, -mno-mips16e2): New options.
* doc/c-mips.texi (MIPS Options): Add `-mmips16e2' and
`-mno-mips16e2' options.
(MIPS ASE Instruction Generation Overrides): Add `.set mips16e2'
and `.set nomips16e2'.
Improve out-of-range operand error diagnostics for invalid values in the
[32768,65535] range used for a signed 16-bit immediate, making the
message consistent with that used for other invalid values, e.g.:
foo.s:1: Error: operand 2 must be an immediate expression `addiu $2,$gp,32768'
foo.s:2: Error: invalid operands `lw $2,32768($gp)'
vs:
foo.s:3: Error: operand 3 out of range `addiu $2,$gp,-32769'
foo.s:4: Error: operand 2 out of range `lw $2,-32769($gp)'
This case does not currently trigger however, for two reasons.
First, for regular MIPS and microMIPS assembly in the case of no match
caused by `match_int_operand' here, the function is always called again
from `mips_ip' via `match_insns', `match_insn' and then `match_operand'
for the same opcode table's entry with `lax_match' set to TRUE, in which
case the attempt to match succeeds and no error is issued.
Second, in the case of MIPS16 assembly no call to `match_int_operand' is
made at all for signed 16-bit immediates, because such immediates are
currently only matched with extensible instructions, and these are
handled in `match_mips16_insn' via `match_expression' directly rather
than via `match_operand'.
This will change for MIPS16 code with MIPS16e2 support introduced, where
non-extensible instructions accepting signed 16-bit immediates will be
added, so make the case work well right from the start:
foo.s:1: Error: operand 3 out of range `addiu $2,$gp,32768'
foo.s:2: Error: operand 2 out of range `lw $2,32768($gp)'
gas/
* config/tc-mips.c (match_int_operand): Call
`match_out_of_range' before returning failure for 0x8000-0xffff
values conditionally allowed.
Improve operand error diagnostics for non-constant expressions used for
a 16-bit immediate, making the message more descriptive and indicating
the offending operand, e.g.:
foo.s:1: Error: invalid operands `lui $2,foo-bar'
will show as:
foo.s:1: Error: operand 2 must be constant `lui $2,foo-bar'
This case does not currently trigger however, for two reasons.
First, for regular MIPS and microMIPS assembly in the case of no match
caused by `match_int_operand' here, the function is always called again
from `mips_ip' via `match_insns', `match_insn' and then `match_operand'
for the same opcode table's entry with `lax_match' set to TRUE, in which
case the attempt to match succeeds and no error is issued.
Second, in the case of MIPS16 assembly no call to `match_int_operand' is
made at all for 16-bit immediates, because such immediates are currently
only matched with extensible instructions, and these are handled in
`match_mips16_insn' via `match_expression' directly rather than via
`match_operand'.
This will change for MIPS16 code with MIPS16e2 support introduced, where
non-extensible instructions accepting 16-bit immediates will be added,
so make the case work well right from the start.
gas/
* config/tc-mips.c (match_int_operand): Call
`match_not_constant' before returning failure for a non-constant
16-bit immediate conditionally allowed.
Improve bignum operand error diagnostics for cases where a constant
would be accepted and report them as range errors, also indicating the
offending operand and instruction, e.g.:
$ cat bignum.s
addiu $2, 0x10000000000000000
break 0x10000000000000000
$ as -o bignum.o bignum.s
bignum.s:1: Error: bignum invalid
bignum.s:2: Error: operand 1 must be constant `break 0x10000000000000000'
$
now show as:
$ as -o bignum.o bignum.s
bignum.s:1: Error: operand 2 out of range `addiu $2,0x10000000000000000'
bignum.s:2: Error: operand 1 out of range `break 0x10000000000000000'
$
gas/
* config/tc-mips.c (match_const_int): Call `match_out_of_range'
rather than `match_not_constant' for unrelocated operands
retrieved as an `O_big' expression.
(match_int_operand): Call `match_out_of_range' for relocatable
operands retrieved as an `O_big' expression.
(match_mips16_insn): Call `match_out_of_range' for relaxable
operands retrieved as an `O_big' expression.
* testsuite/gas/mips/addiu-error.d: New test.
* testsuite/gas/mips/mips16@addiu-error.d: New test.
* testsuite/gas/mips/micromips@addiu-error.d: New test.
* testsuite/gas/mips/break-error.d: New test.
* testsuite/gas/mips/lui-1.l: Adjust error message.
* testsuite/gas/mips/addiu-error.l: New stderr output.
* testsuite/gas/mips/mips16@addiu-error.l: New stderr output.
* testsuite/gas/mips/micromips@addiu-error.l: New stderr output.
* testsuite/gas/mips/break-error.l: New stderr output.
* testsuite/gas/mips/addiu-error.s: New test source.
* testsuite/gas/mips/break-error.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Improve non-immediate operand error diagnostics for extensible MIPS16
instructions and make it match corresponding regular MIPS and microMIPS
handling, e.g:
$ cat addiu.s
addiu $4, $3, $2
$ as -o addiu.o addiu.s
addiu.s: Assembler messages:
addiu.s:1: Error: operand 3 must be an immediate expression `addiu $4,$3,$2'
$ as -mips16 -o addiu.o addiu.s
addiu.s: Assembler messages:
addiu.s:1: Error: invalid operands `addiu $4,$3,$2'
$
To do so observe that for extensible MIPS16 instructions and a non-PC
relative operand this case is handled by an explicit OT_INTEGER check in
`match_mips16_insn' returning a failure right away and consequently
preventing a call to `match_expression' from being made. As from commit
d436c1c2e8 ("Improve error reporting for register expressions"),
<https://sourceware.org/ml/binutils/2013-08/msg00134.html>, however the
check has become redundant as `match_expression' now only ever returns
success for OT_INTEGER argument tokens, and a special case of an OT_CHAR
`(' token already handled by `match_mips16_insn' just ahead of the
`match_expression' call. Previously it also returned success for OT_REG
argument tokens.
Let the call to `match_expression' always happen then, yielding the same
failure for the affected cases, however with more accurate diagnostics
provided by the call making reporting consistent:
$ as -mips16 -o addiu.o addiu.s
addiu.s: Assembler messages:
addiu.s:1: Error: operand 3 must be an immediate expression `addiu $4,$3,$2'
$
gas/
* config/tc-mips.c (match_mips16_insn): Remove the explicit
OT_INTEGER check before the `match_expression' call.
* testsuite/gas/mips/mips16-insn-e.l: Adjust messages.
* testsuite/gas/mips/mips16-32@mips16-insn-e.l: Likewise.
* testsuite/gas/mips/mips16-64@mips16-insn-e.l: Likewise.
* testsuite/gas/mips/mips16e-32@mips16-insn-e.l: Likewise.
* testsuite/gas/mips/mips16-reg-error.d: New test.
* testsuite/gas/mips/mips16-reg-error.l: New stderr output.
* testsuite/gas/mips/mips16-reg-error.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
Improve disallowed relocation operand error diagnostics for MIPS16 code
and make it match corresponding regular MIPS and microMIPS handling,
e.g:
$ cat sltu.s
sltu $2, %lo(foo)
$ as -o sltu.o sltu.s
sltu.s: Assembler messages:
sltu.s:1: Error: operand 2 must be constant `sltu $2,%lo(foo)'
$ as -mips16 -o sltu.o sltu.s
sltu.s: Assembler messages:
sltu.s:1: Error: invalid operands `sltu $2,%lo(foo)'
$
To do so call `match_not_constant' from `match_mips16_insn' whenever a
disallowed relocation operation has been noticed, like `match_const_int'
does, making reporting consistent:
$ as -mips16 -o sltu.o sltu.s
sltu.s: Assembler messages:
sltu.s:1: Error: operand 2 must be constant `sltu $2,%lo(foo)'
$
gas/
* config/tc-mips.c (match_mips16_insn): Call
`match_not_constant' for a disallowed relocation operation.
* testsuite/gas/mips/mips16-reloc-error.d: New test.
* testsuite/gas/mips/mips16-reloc-error.l: New stderr output.
* testsuite/gas/mips/mips16-reloc-error.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
gas/
* testsuite/gas/mips/lui-1.d: New test.
* testsuite/gas/mips/lui-2.d: New test.
* gas/testsuite/gas/mips/mips.exp: Fold corresponding list tests
into the new tests.
Complement commit 919731affb ("Add MIPS .module directive") and update
the GAS manual to refer to the `.module' rather than `.set' directive in
command-line option descriptions, following an observation that unlike
`.set' and like the respective command-line option the use of the
`.module' directive affects the ISA and ASE flags recorded in the object
file produced, and therefore it is `.module' rather than `.set' that
corresponds to the respective command-line option.
gas/
* doc/as.texinfo (-mips16, -no-mips16): Refer to `.module
mips16' rather than `.set mips16'.
(-mmicromips, -mno-micromips): Refer to `.module micromips' and
`.module nomicromips' rather than `.set micromips' and `.set
nomicromips'.
(-msmartmips, -mno-smartmips): Refer to `.module smartmips'
rather than `.set smartmips'.
* doc/c-mips.texi (MIPS Options): Refer to `.module mips16',
`.module micromips', `.module nomicromips' and `.module
smartmips' rather than `.set mips16', `.set micromips', `.set
nomicromips' and `.set smartmips' respectively.
For a reason that is unclear commit d6f1659387 ("Support for MIPS16
HI16/LO16 relocations"),
<https://sourceware.org/ml/binutils/2005-02/msg00332.html>, which has
added support for the R_MIPS16_GPREL relocation, has spelled its
corresponding MIPS16 percent-op as `%gprel', rather than `%gp_rel' which
is how its regular MIPS counterpart is spelled. To make assembly code
sharing easier between the regular MIPS and the MIPS16 ISA make both
percent-op spellings acceptable in both kinds of code now.
Parts of this change by Matthew Fortune.
gas/
* config/tc-mips.c (mips_percent_op): Add "%gprel".
(mips16_percent_op): Add "%gp_rel".
* testsuite/gas/mips/elf-rel8.s:: Add `%gprel' forms.
* testsuite/gas/mips/elf-rel8-mips16.s: Add `%gp_rel' forms.
* testsuite/gas/mips/elf-rel8.d: Adjust accordingly.
* testsuite/gas/mips/elf-rel8-mips16.d: Likewise.
Disassemble the MIPS16 BREAK and SDBBP instruction's immediate operand
in the hexadecimal rather than decimal numeral system and add respective
operandless variants with an implicit 0 operand, making our handling of
these instructions consistent with how we have processed their regular
MIPS and microMIPS counterparts since forever.
opcodes/
* mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
type to hexadecimal.
(mips16_opcodes): Add operandless "break" and "sdbbp" entries.
binutils/
* testsuite/binutils-all/mips/mips16-extend-insn.d: Adjust BREAK
and SDBBP disassembly.
gas/
* testsuite/gas/mips/mips16.d: Adjust BREAK disassembly.
* testsuite/gas/mips/mips16-64@mips16.d: Likewise.
* testsuite/gas/mips/mips16-64.d: Likewise.
* testsuite/gas/mips/mips16-64@mips16-64.d: Likewise.
* testsuite/gas/mips/mips16-macro.d: Likewise.
* testsuite/gas/mips/mips16-64@mips16-macro.d: Likewise.
* testsuite/gas/mips/mips16-sub.d: Likewise.
* testsuite/gas/mips/mips16-32@mips16-sub.d: Likewise.
Following the way how descriptive SYNC mnemonics have been defined in
the architecture[1][2] mark them as aliases, so that the generic SYNC
instruction can be alternatively disassembled along with its immediate
operand, as noted in the documents referred.
References:
[1] "MIPS Architecture For Programmers, Volume II-A: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00086,
Revision 5.04, December 11, 2013, Table 4.7 "Encodings of the
Bits[10:6] of the SYNC instruction; the SType Field", p. 305
[2] "MIPS Architecture for Programmers, Volume II-B: The microMIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00582,
Revision 5.04, January 15, 2014, Table 5.28 "Encodings of the
Bits[10:6] of the SYNC instruction; the SType Field", p. 481
opcodes/
* mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
"syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
"sync_rmb" and "sync_wmb" as aliases.
* micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
"sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
gas/
* testsuite/gas/mips/mips32r2-sync-1.d: New test.
* testsuite/gas/mips/micromips@mips32r2-sync-1.d: New test.
* testsuite/gas/mips/mips.exp: Run the new tests.
And remove the zillion duplicate sources. Also `mips1@isa-override-2.l'
is the same as `r3000@isa-override-2.l', so remove the latter too, now
that `r3000@isa-override-2.d' can name a file to match stderr output
against.
gas/
* testsuite/gas/mips/isa-override-2.d: New test.
* testsuite/gas/mips/mips1@isa-override-2.d: New test.
* testsuite/gas/mips/r3000@isa-override-2.d: New test.
* testsuite/gas/mips/r3900@isa-override-2.d: New test.
* testsuite/gas/mips/mips2@isa-override-2.d: New test.
* testsuite/gas/mips/mips32@isa-override-2.d: New test.
* testsuite/gas/mips/mips32r2@isa-override-2.d: New test.
* testsuite/gas/mips/mips32r3@isa-override-2.d: New test.
* testsuite/gas/mips/mips32r5@isa-override-2.d: New test.
* testsuite/gas/mips/mips32r6@isa-override-2.d: New test.
* testsuite/gas/mips/octeon3@isa-override-2.d: New test.
* testsuite/gas/mips/r3000@isa-override-2.l: Remove list test.
* testsuite/gas/mips/mips1@isa-override-2.s: Remove test source.
* testsuite/gas/mips/r3000@isa-override-2.s: Remove test source.
* testsuite/gas/mips/r3900@isa-override-2.s: Remove test source.
* testsuite/gas/mips/mips2@isa-override-2.s: Remove test source.
* testsuite/gas/mips/mips32@isa-override-2.s: Remove test
source.
* testsuite/gas/mips/mips32r2@isa-override-2.s: Remove test
source.
* testsuite/gas/mips/mips32r3@isa-override-2.s: Remove test
source.
* testsuite/gas/mips/mips32r5@isa-override-2.s: Remove test
source.
* testsuite/gas/mips/mips32r6@isa-override-2.s: Remove test
source.
* testsuite/gas/mips/octeon3@isa-override-2.s: Remove test
source.
* gas/testsuite/gas/mips/mips.exp: Fold corresponding list tests
into the new tests.
Complement commit c60aaac10f ("MIPS/GAS/testsuite: Extend MIPS16
testing over multiple ISAs") and remove a stale `mips16-macro' list test
output replaced with the `mips16-32@mips16-macro' stderr output.
gas/
* testsuite/gas/mips/mips16-macro.l: Remove list test.
Implement the relaxation of MIPS16 PC-relative synthetic LA, DLA, LW and
LD instructions to an equivalent sequence of instructions produced where
the address operand requested is out of range, absolute or requires
linker relocation, for ABIs that use 32-bit addressing and non-PIC code.
The sequence generated uses the register specified for the destination
operand as a temporary and begins with LI to load the high 16-bit part
of the address, then continues with SLL by 16 bits to move that part
into place and finally completes with a suitable operation corresponding
to the synthetic instruction used, one of: 2-argument ADDIU, 2-argument
DADDIU, absolute LW, and absolute LD respectively, providing the low
16-bit part of the address. All instructions use the extended encoding.
As a special exception accept absolute addresses for relaxation even in
PIC code.
For example:
la $2, 0x12345678
produces code as:
li $2, 0x1234
sll $2, $2, 16
addiu $2, 0x5678
would.
Where linker relocation is required emit an R_MIPS16_HI16 relocation on
the initial LI instruction and an R_MIPS16_LO16 relocation on the final
operation.
For example (where `foo' is not local):
lw $3, foo
produces code as:
li $3, %hi(foo)
sll $3, $3, 16
lw $3, %lo(foo)($3)
would.
Emit assembly warnings as appropriate where this new relaxation triggers
in the `nomacro' mode or for an instruction manually placed in a branch
delay slot in the `noreorder' mode. Refrain from relaxation where an
explicit instruction size suffix has been used and in the `noautoextend'
mode.
gas/
* config/tc-mips.c (RELAX_MIPS16_ENCODE): Add `pic', `sym32' and
`nomacro' flags.
(RELAX_MIPS16_PIC, RELAX_MIPS16_SYM32, RELAX_MIPS16_NOMACRO):
New macros.
(RELAX_MIPS16_USER_SMALL, RELAX_MIPS16_USER_EXT)
(RELAX_MIPS16_DSLOT, RELAX_MIPS16_JAL_DSLOT)
(RELAX_MIPS16_EXTENDED, RELAX_MIPS16_MARK_EXTENDED)
(RELAX_MIPS16_CLEAR_EXTENDED, RELAX_MIPS16_ALWAYS_EXTENDED)
(RELAX_MIPS16_MARK_ALWAYS_EXTENDED)
(RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED): Shift bits.
(RELAX_MIPS16_MACRO, RELAX_MIPS16_MARK_MACRO)
(RELAX_MIPS16_CLEAR_MACRO): New macros.
(append_insn): Pass `mips_pic', HAVE_32BIT_SYMBOLS and
`mips_opts.warn_about_macros' settings to RELAX_MIPS16_ENCODE.
(mips16_macro_frag): New function.
(md_estimate_size_before_relax): Handle HI16/LO16 relaxation.
(mips_relax_frag): Likewise.
(md_convert_frag): Likewise.
* testsuite/gas/mips/mips16@relax-swap3.d: Remove error output,
add dump patterns.
* testsuite/gas/mips/mips16e@relax-swap3.d: New test
subarchitecture.
* testsuite/gas/mips/micromips@relax-swap3.d: Remove trailing
NOP padding.
* testsuite/gas/mips/mips16-pcrel-reloc-2.d: Remove error
output, add dump patterns.
* testsuite/gas/mips/mips16-pcrel-reloc-3.d: Remove error
output, add dump patterns.
* testsuite/gas/mips/mips16-pcrel-reloc-6.d: Remove error
output, add dump patterns.
* testsuite/gas/mips/mips16-pcrel-reloc-7.d: Remove error
output, add dump patterns.
* testsuite/gas/mips/mips16-pcrel-addend-2.d: Remove error
output, add dump patterns.
* testsuite/gas/mips/mips16-pcrel-addend-3.d: Remove error
output, add dump patterns.
* testsuite/gas/mips/mips16-pcrel-absolute.d: Remove error
output, add dump patterns.
* testsuite/gas/mips/mips16-pcrel-absolute-1.d: Remove error
output, add dump patterns.
* testsuite/gas/mips/mips16@relax-swap3.l: Remove file.
* testsuite/gas/mips/mips16-pcrel-reloc-2.l: Remove file.
* testsuite/gas/mips/mips16-pcrel-reloc-3.l: Remove file.
* testsuite/gas/mips/mips16-pcrel-reloc-6.l: Remove file.
* testsuite/gas/mips/mips16-pcrel-reloc-7.l: Remove file.
* testsuite/gas/mips/mips16-pcrel-addend-2.l: Remove file.
* testsuite/gas/mips/mips16-pcrel-addend-3.l: Remove file.
* testsuite/gas/mips/mips16-pcrel-absolute.l: Remove file.
* testsuite/gas/mips/mips16-pcrel-absolute-1.l: Remove file.
* testsuite/gas/mips/relax-swap3.s: Adjust trailing padding.
* testsuite/gas/mips/mips16-pcrel-0.d: New test.
* testsuite/gas/mips/mips16-pcrel-1.d: New test.
* testsuite/gas/mips/mips16-pcrel-2.d: New test.
* testsuite/gas/mips/mips16-pcrel-3.d: New test.
* testsuite/gas/mips/mips16-pcrel-4.d: New test.
* testsuite/gas/mips/mips16-pcrel-5.d: New test.
* testsuite/gas/mips/mips16-pcrel-pic-0.d: New test.
* testsuite/gas/mips/mips16-pcrel-pic-1.d: New test.
* testsuite/gas/mips/mips16-pcrel-n32-0.d: New test.
* testsuite/gas/mips/mips16-pcrel-n32-1.d: New test.
* testsuite/gas/mips/mips16-pcrel-n64-sym32-0.d: New test.
* testsuite/gas/mips/mips16-pcrel-n64-sym32-1.d: New test.
* testsuite/gas/mips/mips16-pcrel-n64-0.d: New test.
* testsuite/gas/mips/mips16-pcrel-n64-1.d: New test.
* testsuite/gas/mips/mips16-pcrel-delay-0.d: New test.
* testsuite/gas/mips/mips16-pcrel-delay-1.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-4.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-5.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-6.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-7.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-8.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-9.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-pic-8.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-pic-9.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-n32-8.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-n32-9.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-n64-sym32-8.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-n64-sym32-9.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-n64-8.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-n64-9.d: New test.
* testsuite/gas/mips/mips16-pcrel-absolute-2.d: New test.
* testsuite/gas/mips/mips16-pcrel-absolute-3.d: New test.
* testsuite/gas/mips/mips16-pcrel-absolute-4.d: New test.
* testsuite/gas/mips/mips16-pcrel-absolute-5.d: New test.
* testsuite/gas/mips/mips16-pcrel-absolute-6.d: New test.
* testsuite/gas/mips/mips16-pcrel-absolute-7.d: New test.
* testsuite/gas/mips/mips16-pcrel-absolute-pic-4.d: New test.
* testsuite/gas/mips/mips16-pcrel-absolute-pic-6.d: New test.
* testsuite/gas/mips/mips16-pcrel-absolute-n32-4.d: New test.
* testsuite/gas/mips/mips16-pcrel-absolute-n32-6.d: New test.
* testsuite/gas/mips/mips16-pcrel-absolute-n64-4.d: New test.
* testsuite/gas/mips/mips16-pcrel-absolute-n64-6.d: New test.
* testsuite/gas/mips/mips16-pcrel-absolute-n64-sym32-4.d: New
test.
* testsuite/gas/mips/mips16-pcrel-absolute-n64-sym32-6.d: New
test.
* testsuite/gas/mips/mips16-pcrel-absolute-pic-n32-4.d: New
test.
* testsuite/gas/mips/mips16-pcrel-absolute-pic-n32-6.d: New
test.
* testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-4.d: New
test.
* testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-6.d: New
test.
* testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-sym32-4.d:
New test.
* testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-sym32-6.d:
New test.
* testsuite/gas/mips/mips16-pcrel-0.l: New stderr output.
* testsuite/gas/mips/mips16-pcrel-1.l: New stderr output.
* testsuite/gas/mips/mips16-pcrel-2.l: New stderr output.
* testsuite/gas/mips/mips16-pcrel-3.l: New stderr output.
* testsuite/gas/mips/mips16-pcrel-4.l: New stderr output.
* testsuite/gas/mips/mips16-pcrel-5.l: New stderr output.
* testsuite/gas/mips/mips16-pcrel-delay-0.l: New stderr output.
* testsuite/gas/mips/mips16-pcrel-delay-1.l: New stderr output.
* testsuite/gas/mips/mips16-pcrel-addend-8.l: New stderr output.
* testsuite/gas/mips/mips16-pcrel-addend-9.l: New stderr output.
* testsuite/gas/mips/mips16-pcrel-absolute-4.l: New stderr
output.
* testsuite/gas/mips/mips16-pcrel-absolute-6.l: New stderr
output.
* testsuite/gas/mips/mips16-pcrel-0.s: New test source.
* testsuite/gas/mips/mips16-pcrel-1.s: New test source.
* testsuite/gas/mips/mips16-pcrel-2.s: New test source.
* testsuite/gas/mips/mips16-pcrel-3.s: New test source.
* testsuite/gas/mips/mips16-pcrel-4.s: New test source.
* testsuite/gas/mips/mips16-pcrel-5.s: New test source.
* testsuite/gas/mips/mips16-pcrel-delay-0.s: New test source.
* testsuite/gas/mips/mips16-pcrel-delay-1.s: New test source.
* testsuite/gas/mips/mips16-pcrel-addend-4.s: New test source.
* testsuite/gas/mips/mips16-pcrel-addend-5.s: New test source.
* testsuite/gas/mips/mips16-pcrel-addend-6.s: New test source.
* testsuite/gas/mips/mips16-pcrel-addend-7.s: New test source.
* testsuite/gas/mips/mips16-pcrel-addend-8.s: New test source.
* testsuite/gas/mips/mips16-pcrel-addend-9.s: New test source.
* testsuite/gas/mips/mips16-pcrel-absolute-2.s: New test.
* testsuite/gas/mips/mips16-pcrel-absolute-3.s: New test.
* testsuite/gas/mips/mips16-pcrel-absolute-4.s: New test.
* testsuite/gas/mips/mips16-pcrel-absolute-5.s: New test.
* testsuite/gas/mips/mips16-pcrel-absolute-6.s: New test.
* testsuite/gas/mips/mips16-pcrel-absolute-7.s: New test.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* testsuite/ld-mips-elf/mips16-pcrel-0.d: New test.
* testsuite/ld-mips-elf/mips16-pcrel-1.d: New test.
* testsuite/ld-mips-elf/mips16-pcrel-addend-2.d: New test.
* testsuite/ld-mips-elf/mips16-pcrel-addend-6.d: New test.
* testsuite/ld-mips-elf/mips16-pcrel-n32-0.d: New test.
* testsuite/ld-mips-elf/mips16-pcrel-n32-1.d: New test.
* testsuite/ld-mips-elf/mips16-pcrel-n64-sym32-0.d: New test.
* testsuite/ld-mips-elf/mips16-pcrel-n64-sym32-1.d: New test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
Complement commit 88a7ef1689 ("MIPS16/GAS: Restore unsupported
relocation diagnostics") and also propagate constant expressions, either
already reduced from absolute symbol references or created from literals
in the first place, used as a PC-relative operand with the MIPS16 LA,
LW, DLA and LD synthetic instructions to relaxation, matching the way
forward absolute symbol references have been handled as from the commit
referred and letting relaxation produce any necessary relocations, if
possible, for the absolute value requested to be reproduced at the run
time.
Call `symbol_append' for any expression symbol created for the purpose
of MIPS16 relaxation as with constant expressions now propagated from
earlier on such symbols may make it through and have R_MIPS16_PC16_S1
relocations emitted against, and therefore need to appear in the symbol
table produced.
gas/
* config/tc-mips.c (append_insn): Call `symbol_append' for any
expression symbol created for MIPS16 relaxation.
(match_mips16_insn): Don't encode a constant value as an
immediate with a PC-relative operand.
* testsuite/gas/mips/mips16-pcrel-absolute-1.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-1.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-2.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-addend-1.d: New
test.
* testsuite/gas/mips/mips16-branch-absolute-n32-1.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-n32-2.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-addend-n32-1.d: New
test.
* testsuite/gas/mips/mips16-branch-absolute-n64-1.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-n64-2.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-addend-n64-1.d: New
test.
* testsuite/gas/mips/mips16-pcrel-absolute-1.l: New stderr
output.
* testsuite/gas/mips/mips16-pcrel-absolute-1.s: New test source.
* testsuite/gas/mips/mips16-branch-absolute-1.s: New test
source.
* testsuite/gas/mips/mips16-branch-absolute-2.s: New test
source.
* testsuite/gas/mips/mips16-branch-absolute-addend-1.s: New test
source.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* testsuite/ld-mips-elf/mips16-branch-absolute-1.d: New test.
* testsuite/ld-mips-elf/mips16-branch-absolute-2.d: New test.
* testsuite/ld-mips-elf/mips16-branch-absolute-addend-1.d: New
test.
* testsuite/ld-mips-elf/mips16-branch-absolute-n32-1.d: New
test.
* testsuite/ld-mips-elf/mips16-branch-absolute-n32-2.d: New
test.
* testsuite/ld-mips-elf/mips16-branch-absolute-addend-n32-1.d:
New test.
* testsuite/ld-mips-elf/mips16-branch-absolute-n64-1.d: New
test.
* testsuite/ld-mips-elf/mips16-branch-absolute-n64-2.d: New
test.
* testsuite/ld-mips-elf/mips16-branch-absolute-addend-n64-1.d:
New test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
Factor out and consolidate duplicate section-relative to PC-relative
symbol value conversion in `mips16_extended_frag' and `md_convert_frag'
used for MIPS16 relaxation, observing that the final calculation in the
latter function implies `stretch == 0'. Sanitize the formatting of code
moved.
gas/
* config/tc-mips.c (mips16_pcrel_val): New function, factored
out from...
(mips16_extended_frag): ... here.
(md_convert_frag): Use `mips16_pcrel_val' rather than repeated
code in MIPS16 relaxation, with `stretch' hardcoded to 0.
Following commit 177b4a6ad0 ("infinite loop in mips16 assembler
relaxation"), <https://sourceware.org/ml/binutils/2002-03/msg00345.html>
the LONG_BRANCH flag used in MIPS16 relaxation has lost its use for
branches. Complement commit 88a7ef1689 ("MIPS16/GAS: Restore
unsupported relocation diagnostics") then, which has removed the remains
of code deactivated by the former commit, and rename the flag to
ALWAYS_EXTENDED, more accurately reflecting its current use to select
the extended form of PC-relative ADDIU, DADDIU, LD and LW instructions.
gas/
* config/tc-mips.c (RELAX_MIPS16_LONG_BRANCH): Rename to...
(RELAX_MIPS16_ALWAYS_EXTENDED): ... this.
(RELAX_MIPS16_MARK_LONG_BRANCH): Rename to...
(RELAX_MIPS16_MARK_ALWAYS_EXTENDED): ... this.
(RELAX_MIPS16_CLEAR_LONG_BRANCH): Rename to...
(RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED): ... this.
(mips16_extended_frag): Adjust accordingly.
Separate out symbol flag reasons from section reasons to force a
reloc. Yes, this adds another section test to the local symbol case
too.
* symbols.c (S_FORCE_RELOC): Separate section and symbol tests.
Correct the handling of `.option pic0' and `.option pic2' GAS pseudo-ops
in relaxation and use the setting of `mips_pic' (which these directives
control) as at the time a relaxed frag has been created rather than the
final `mips_pic' setting at the end of the source file processed.
To do so record whether `mips_pic' is NO_PIC or not in the frag itself
and use this information throughout relaxation instead of `mips_pic' to
decide which of NO_PIC or SVR4_PIC to produce machine code for, fixing
code generation and removing a possible fatal failure reproducible with:
$ as -32 --relax-branch -o option-pic-relax-3.o option-pic-relax-3.s
option-pic-relax-3.s: Assembler messages:
option-pic-relax-3.s:7: Warning: relaxed out-of-range branch into a jump
option-pic-relax-3.s: Internal error in cvt_frag_to_fill at .../gas/write.c:490.
Please report this bug.
$
using the test source included, due to a buffer overrun in filling the
variable part of a frag.
Likewise use the `fx_tcbit2' flag of a BFD_RELOC_16_PCREL_S2 fixup to
handle the simple case of substituting an out of range unconditional
branch with an equivalent absolute jump in NO_PIC code.
Retain the current way of VXWORKS_PIC use, which commit 41a1578ed1
("MIPS/GAS: Sanitize `.option picX' pseudo-op") has forbidden the use of
`.option picX' with.
gas/
* config/tc-mips.c (RELAX_ENCODE): Add `PIC' flag.
(RELAX_PIC): New macro.
(RELAX_USE_SECOND, RELAX_SECOND_LONGER, RELAX_NOMACRO)
(RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT)
(RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND):
Shift bits.
(RELAX_BRANCH_ENCODE): Add `pic' flag.
(RELAX_BRANCH_UNCOND, RELAX_BRANCH_LIKELY, RELAX_BRANCH_LINK)
(RELAX_BRANCH_TOOFAR): Shift bits.
(RELAX_BRANCH_PIC): New macro.
(RELAX_MICROMIPS_ENCODE): Add `pic' flag.
(RELAX_MICROMIPS_PIC): New macro.
(RELAX_MICROMIPS_UNCOND, RELAX_MICROMIPS_COMPACT)
(RELAX_MICROMIPS_LINK, RELAX_MICROMIPS_NODS)
(RELAX_MICROMIPS_RELAX32): Shift bits.
(relax_close_frag): Pass `mips_pic' setting to RELAX_ENCODE.
(append_insn): Pass `mips_pic' setting to RELAX_BRANCH_ENCODE
and RELAX_MICROMIPS_ENCODE, and record it in `fx_tcbit2' of the
first fixup created.
(md_apply_fix) <BFD_RELOC_16_PCREL_S2>: Use `fx_tcbit2' of the
fixup processed rather than `mips_pic' in choosing to relax an
out of range branch to a jump.
(relaxed_branch_length): Use the `pic' flag of the relaxed frag
rather than `mips_pic'.
(relaxed_micromips_32bit_branch_length): Likewise.
(md_estimate_size_before_relax): Likewise.
(md_convert_frag): Likewise.
* testsuite/gas/mips/option-pic-relax-0.d: New test.
* testsuite/gas/mips/option-pic-relax-1.d: New test.
* testsuite/gas/mips/option-pic-relax-2.d: New test.
* testsuite/gas/mips/option-pic-relax-3.d: New test.
* testsuite/gas/mips/option-pic-relax-3a.d: New test.
* testsuite/gas/mips/option-pic-relax-4.d: New test.
* testsuite/gas/mips/option-pic-relax-5.d: New test.
* testsuite/gas/mips/option-pic-relax-2.l: New stderr output.
* testsuite/gas/mips/option-pic-relax-3.l: New stderr output.
* testsuite/gas/mips/option-pic-relax-4.l: New stderr output.
* testsuite/gas/mips/option-pic-relax-5.l: New stderr output.
* testsuite/gas/mips/option-pic-relax-0.s: New test source.
* testsuite/gas/mips/option-pic-relax-1.s: New test source.
* testsuite/gas/mips/option-pic-relax-2.s: New test source.
* testsuite/gas/mips/option-pic-relax-3.s: New test source.
* testsuite/gas/mips/option-pic-relax-4.s: New test source.
* testsuite/gas/mips/option-pic-relax-5.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
enter/leave mnemonics are enhanced to not only accept register ranges
but also single register (i.e., r13) or even no GPR register at all.
gas/
2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/leave_enter.d: Update test.
* testsuite/gas/arc/leave_enter.s: Likewise.
opcodes/
2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
* arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
* arc-opc.c (insert_r13el): New function.
(R13_EL): Define.
* arc-tbl.h: Add new enter/leave variants.
NOP and MOV 0,0 are having the same encoding. As MOV mnemonic is
located before NOP in the instruction table, the disassembler prints
MOV 0,0 for NOP. Reorder the instructions such that NOP is first.
gas/
2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/b.d: Update test.
* testsuite/gas/arc/noargs_hs.d: Likewise.
opcode/
2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
* arc-tbl.h: Reorder NOP entry to be before MOV instructions.
Correct the size of a BFD_RELOC_MIPS16_16_PCREL_S1 fixup made in
`md_convert_frag', fixing a bug introduced with commit c9775dde32
("MIPS16: Add R_MIPS16_PC16_S1 branch relocation support)". Add test
cases to verify that the overflow of this fixup's in-place addend is
still correctly detected.
gas/
* config/tc-mips.c (md_convert_frag): Correct
BFD_RELOC_MIPS16_16_PCREL_S1 fixup size.
* testsuite/gas/mips/mips16-branch-addend-4.d: New test.
* testsuite/gas/mips/mips16-branch-addend-5.d: New test.
* testsuite/gas/mips/mips16-branch-addend-5.l: New stderr
output.
* testsuite/gas/mips/mips16-branch-addend-4.s: New test source.
* testsuite/gas/mips/mips16-branch-addend-5.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
This patch avoids CALL instructions to be optimized into branches if
the symbols referred to in the CALL instruction are not fully resolved
at the time the assembler writes its output.
Tested in sparc64-linux-gnu and sparc-sun-sunos4.1.3 targets.
No regressions.
gas/ChangeLog:
2017-04-25 Jose E. Marchesi <jose.marchesi@oracle.com>
PR gas/21407
* config/tc-sparc.c (md_apply_fix): Do not transform `call'
instructions into branch instructions in fixups generating
additional relocations.
* testsuite/gas/sparc/call-relax.s: New file.
* testsuite/gas/sparc/call-relax.d: Likewise.
* testsuite/gas/sparc/call-relax-aout.d: Likewise.
* testsuite/gas/sparc/sparc.exp: Test call-relax and call-relax-aout.
The LDR rX, =cst pseudo-instruction suffers from two issues for loading
integer constants in Thumb mode:
- movs is used if the constant and register can be encoded using that
instruction which leads to unexpected behavior due to its flag-setting
behavior
- mov.w, movw and mvn are used for r13 (sp) and r15 (pc) but these
encoding are marked as UNPREDICTABLE
This patch fixes those issues and update testing accordingly.
2017-04-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (move_or_literal_pool): Remove code generating MOVS.
Forbid MOV.W and MOVW if destination is SP or PC.
* testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.s: Explain
expectation of LDR not generating a MOVS for low registers and small
constants. Add tests of MOVW generation.
* testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.d: Update
expected disassembly.
PR binutils/21380
opcodes * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
LD3R and LD4R.
gas * testsuite/gas/aarch64/illegal-3.s: New file.
* testsuite/gas/aarch64/illegal-3.d: New file.
* config/tc-xtensa.c (xtensa_maybe_create_literal_pool_frag):
Initialize lps->frag_count with auto_litpool_limit.
(xg_promote_candidate_litpool): New function.
(xtensa_move_literals): Extract candidate litpool promotion code
into separate function. Call it for all possible found
candidates.
(xtensa_switch_to_literal_fragment): Drop 'recursive' flag and
call to xtensa_mark_literal_pool_location that it guards.
Replace it with call to xtensa_maybe_create_literal_pool_frag.
Initialize pool_location with created literal pool candidate.
* testsuite/gas/xtensa/all.exp: Add new tests.
* testsuite/gas/xtensa/auto-litpools-first1.d: New test results.
* testsuite/gas/xtensa/auto-litpools-first1.s: New test.
* testsuite/gas/xtensa/auto-litpools-first2.d: New test results.
* testsuite/gas/xtensa/auto-litpools-first2.s: New test.
* testsuite/gas/xtensa/auto-litpools.d: Fix offsets changed due
to additional jump instruction.
include * dis-asm.h: Add prototypes for wasm32 disassembler.
opcodes * Makefile.am: Add wasm32-dis.c.
* configure.ac: Add wasm32-dis.c to wasm32 target.
* disassemble.c: Add wasm32 disassembler code.
* wasm32-dis.c: New file.
* Makefile.in: Regenerate.
* configure: Regenerate.
* po/POTFILES.in: Regenerate.
* po/opcodes.pot: Regenerate.
gas * testsuite/gas/wasm32/allinsn.d: Adjust test for disassembler
changes.
* testsuite/gas/wasm32/disass.d: New test.
* testsuite/gas/wasm32/disass.s: New test.
* testsuite/gas/wasm32/disass-2.d: New test.
* testsuite/gas/wasm32/disass-2.s: New test.
* testsuite/gas/wasm32/reloc.d: Adjust test for changed reloc
names.
* testsuite/gas/wasm32/reloc.s: Update test for changed assembler
syntax.
* testsuite/gas/wasm32/wasm32.exp: Run new tests. Expect allinsn
test to succeed.
Mark an ALLOC section, which should be placed in special memory area,
with SHF_GNU_MBIND. Its sh_info field indicates the special memory
type. GNU_MBIND section names start with ".mbind" so that they are
placed as orphan sections by linker. All input GNU_MBIND sections
with the same sh_type, sh_flags and sh_info are placed in one output
GNU_MBIND section. In executable and shared object, create a
GNU_MBIND segment for each GNU_MBIND section and its segment type is
PT_GNU_MBIND_LO plus the sh_info value. Each GNU_MBIND segment is
aligned at page boundary.
The assembler syntax:
.section .mbind.foo,"adx",%progbits
^ 0: Special memory type.
|
'd' for SHF_GNU_MBIND.
.section .mbind.foo,"adx",%progbits,0x1
^ 1: Special memory type.
|
'd' for SHF_GNU_MBIND.
.section .mbind.bar,"adG",%progbits,.foo_group,comdat,0x2
^ 2: Special memory type.
|
'd' for SHF_GNU_MBIND.
bfd/
* elf.c (get_program_header_size): Add a GNU_MBIND segment for
each GNU_MBIND section and align GNU_MBIND section to page size.
(_bfd_elf_map_sections_to_segments): Create a GNU_MBIND
segment for each GNU_MBIND section.
(_bfd_elf_init_private_section_data): Copy sh_info from input
for GNU_MBIND section.
binutils/
* NEWS: Mention support for ELF SHF_GNU_MBIND and
PT_GNU_MBIND_XXX.
* readelf.c (get_segment_type): Handle PT_GNU_MBIND_XXX.
(get_elf_section_flags): Handle SHF_GNU_MBIND.
(process_section_headers): Likewise.
* testsuite/binutils-all/mbind1.s: New file.
* testsuite/binutils-all/objcopy.exp: Run readelf test on
mbind1.s.
gas/
* NEWS: Mention support for ELF SHF_GNU_MBIND.
* config/obj-elf.c (section_match): New.
(get_section): Match both sh_info and group name.
(obj_elf_change_section): Add argument for sh_info. Pass both
sh_info and group name to get_section. Issue an error for
SHF_GNU_MBIND section without SHF_ALLOC. Set sh_info.
(obj_elf_parse_section_letters): Set SHF_GNU_MBIND for 'd'.
(obj_elf_section): Support SHF_GNU_MBIND section info.
* config/obj-elf.h (obj_elf_change_section): Add argument for
sh_info.
* config/tc-arm.c (start_unwind_section): Pass 0 as sh_info to
obj_elf_change_section.
* config/tc-ia64.c (obj_elf_vms_common): Likewise.
* config/tc-microblaze.c (microblaze_s_data): Likewise.
(microblaze_s_sdata): Likewise.
(microblaze_s_rdata): Likewise.
(microblaze_s_bss): Likewise.
* config/tc-mips.c (s_change_section): Likewise.
* config/tc-msp430.c (msp430_profiler): Likewise.
* config/tc-rx.c (parse_rx_section): Likewise.
* config/tc-tic6x.c (tic6x_start_unwind_section): Likewise.
* doc/as.texinfo: Document 'd' for SHF_GNU_MBIND.
* testsuite/gas/elf/elf.exp: Run section12a, section12b and
section13.
* testsuite/gas/elf/section10.d: Updated.
* testsuite/gas/elf/section10.s: Likewise.
* testsuite/gas/elf/section12.s: New file.
* testsuite/gas/elf/section12a.d: Likewise.
* testsuite/gas/elf/section12b.d: Likewise.
* testsuite/gas/elf/section13.l: Likewise.
* testsuite/gas/elf/section13.d: Likewise.
* testsuite/gas/elf/section13.s: Likewise.
include/
* elf/common.h (PT_GNU_MBIND_NUM): New.
(PT_GNU_MBIND_LO): Likewise.
(PT_GNU_MBIND_HI): Likewise.
(SHF_GNU_MBIND): Likewise.
ld/
* NEWS: Mention support for ELF SHF_GNU_MBIND and
PT_GNU_MBIND_XXX.
* emultempl/elf32.em (gld${EMULATION_NAME}_place_orphan): Place
input GNU_MBIND sections with the same type, attributes and
sh_info field into a single output GNU_MBIND section.
* testsuite/ld-elf/elf.exp: Run mbind2a and mbind2b.
* testsuite/ld-elf/mbind1.s: New file.
* testsuite/ld-elf/mbind1a.d: Likewise.
* testsuite/ld-elf/mbind1b.d: Likewise.
* testsuite/ld-elf/mbind1c.d: Likewise.
* testsuite/ld-elf/mbind2a.s: Likewise.
* testsuite/ld-elf/mbind2b.c: Likewise.
Without this patch, passing "-march=rv64ic -march=rv64i" results in
you getting a "RV64IC" toolchain, which isn't expected.
gas/ChangeLog:
2017-03-30 Palmer Dabbelt <palmer@dabbelt.com>
* config/tc-riscv.c (riscv_clear_subsets): New function.
(riscv_add_subset): Call riscv_clear_subsets and riscv_set_rvc to
clear RVC when it's been previously set.
This adds -Mraw for PowerPC objdump, a disassembler option to display
the underlying machine instruction rather than aliases. For example,
"rlwinm" always rather than "rotlwi" when the instruction is
performing a simple rotate.
binutils/
* doc/binutils.texi (objdump): Document PowerPC -M options.
gas/
* config/tc-ppc.c (md_parse_option): Reject -mraw.
include/
* opcode/ppc.h (PPC_OPCODE_RAW): Define.
(PPC_OPCODE_*): Make them all unsigned long long constants.
opcodes/
* ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
"raw" option.
(lookup_powerpc): Don't special case -1 dialect. Handle
PPC_OPCODE_RAW.
(print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
lookup_powerpc call, pass it on second.
PR 21303
opcodes/
* ppc-dis.c (struct ppc_mopt): Comment.
(ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
gas/
* testsuite/gas/ppc/pr21303.d,
* testsuite/gas/ppc/pr21303.s: New test
* testsuite/gas/ppc/ppc.exp: Run it.
When GAS is compiled with DEFAULT_CPU set and then run with a -mcpu or
-march option, selected_cpu will be set to the default CPU. This means
the -mcpu is ignored which is surprising behavior. This commit instead
sets selected_cpu from the value passed to -mcpu/-march.
2017-03-24 Thomas preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.: (md_begin): Set selected_cpu from *mcpu_cpu_opt when
CPU_DEFAULT is defined.
It looks like I missed the GAS help text when going through all the
documentation last time, so it printed some of the old-format (never
upstream) arguments. I fixed this, and when I went to check doc/ I
noticed it was missing the '-fpic'/'-fno-pic' options.
add_jump_to_trampoline assumes that jump instruction is in slot 0,
when it's in other slot that results in fixup that references NULL symbol,
which results in segfault later in xtensa_make_cached_fixup.
Search for the non-NULL symbol in the tc_frag_data.slot_symbols and check
that there's exactly one such slot.
xtensa_relax_frag for RELAX_TRAMPOLINE reassigns fixup from the original
instruction with jump to generated jump in the trampoline frag, but does not
fix its fx_r_type or fx_size. That results in "undecodable fix" or
"fixup not contained within frag" error messages during relaxation.
Fix both these fields.
gas/
2017-03-22 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (xtensa_relax_frag): Change fx_size of the
reassigned fixup to size of jump instruction (3) and fx_r_type
to BFD_RELOC_XTENSA_SLOT0_OP, as there's only one slot.
(add_jump_to_trampoline): Search
origfrag->tc_frag_data.slot_symbols for the slot with non-NULL
symbol and use that slot instead of slot 0.
This patch removes the vx2 facility flag. It will not be used by GCC
and was a misnomer anyway.
Committed to mainline and 2.28 branch.
include/ChangeLog:
2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* opcode/s390.h (S390_INSTR_FLAG_VX2): Remove.
(S390_INSTR_FLAG_FACILITY_MASK): Adjust value.
gas/ChangeLog:
2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/tc-s390.c (s390_parse_cpu): Remove S390_INSTR_FLAG_VX2
from cpu_table. Remove vx2, and novx2 from cpu_flags.
opcodes/ChangeLog:
2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-mkopc.c (main): Remove vx2 check.
* s390-opc.txt: Remove vx2 instruction flags.
Instructions for loading or storing 16/32B data from one address type to
another.
gas/ChangeLog
* testsuite/gas/arc/nps400-11.s: New file.
* testsuite/gas/arc/nps400-11.d: New file.
include/ChangeLog
* opcode/arc.h (insn_class_t): Add DMA class.
opcodes/ChangeLog
* arc-nps400-tbl.h: Add cp32/cp16 instructions format.
* arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
(insert_nps_imm_offset): New function.
(extract_nps_imm_offset): New function.
(insert_nps_imm_entry): New function.
(extract_nps_imm_entry): New function.
* doc/as.texinfo (2byte): Note that if no expressions are present
the directive does nothing. Emphasize that the output is
unaligned, and that this can have an effect on the relocations
generated.
(4byte): Simplify description. Refer back to the 2byte
description.
(8byte): Likewise.
Nick pointed out that I hadn't documented the new -mfpu option
neon-vfpv3 and mentioned that some others were missing.
Having looked through the list only one (neon-fp16) really should be
documented; the other two entries in the real table should not be
documented as they are aliases kept for legacy compatibility reasons.
This patch adds the missing entries and notes in the main table that
the other two entries should not be documented.
I've also fixed a small spelling error in the accompanying text.
* config/tc-arm.c (arm_fpus): Note entires that should not be
documented.
* doc/c-arm.texi (-mfpu): Add missing FPU entries for neon-vfpv3 and
neon-fp16. Fix spelling error.
GCC recently added neon-vfpv3 as an alias for neon in -mfpu. This patch adds a similar alias in GAS.
* config/tc-arm.c (arm_fpus): Add neon-vfpv3 as an alias for neon.
