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2169 Commits
| Author | SHA1 | Message | Date | |
|---|---|---|---|---|
Alan Modra
|
7dba9362c1 |
Rewrite __start and __stop symbol handling
This arranges for __start and __stop symbols to be defined before garbage collection, for all target formats. That should allow the COFF and PE --gc-sections to keep a singleton orphan input section, a feature lost by 2017-06-13 commit |
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Yao Qi
|
6394c60699 |
Don't use print_insn_XXX in GDB
This is a follow-up to [PATCH 0/6] Unify the disassembler selection in gdb and objdump https://sourceware.org/ml/binutils/2017-05/msg00192.html that is, opcodes is able to select the right disassembler, so gdb doesn't have to select them. Instead, gdb can just use default_print_insn. As a result, these print_insn_XXX are not used out of opcodes, so this patch also moves their declarations from include/dis-asm.h to opcodes/disassemble.h. With this change, GDB doesn't use any print_insn_XXX directly any more. gdb: 2017-06-14 Yao Qi <yao.qi@linaro.org> * aarch64-tdep.c (aarch64_gdb_print_insn): Call default_print_insn instead of print_insn_aarch64. * arm-tdep.c (gdb_print_insn_arm): Call default_print_insn instead of print_insn_big_arm and print_insn_little_arm. * i386-tdep.c (i386_print_insn): Call default_print_insn instead of print_insn_i386. * ia64-tdep.c (ia64_print_insn): Call default_print_insn instead of print_insn_ia64. * mips-tdep.c (gdb_print_insn_mips): Call default_print_insn instead of print_insn_big_mips and print_insn_little_mips. * spu-tdep.c (gdb_print_insn_spu): Call default_print_insn instead of print_insn_spu. include: 2017-06-14 Yao Qi <yao.qi@linaro.org> * dis-asm.h (print_insn_aarch64): Move it to opcodes/disassemble.h. (print_insn_big_arm, print_insn_big_mips): Likewise. (print_insn_i386, print_insn_ia64): Likewise. (print_insn_little_arm, print_insn_little_mips): Likewise. (print_insn_spu): Likewise. opcodes: 2017-06-14 Yao Qi <yao.qi@linaro.org> * aarch64-dis.c: Include disassemble.h instead of dis-asm.h. * arm-dis.c: Likewise. * ia64-dis.c: Likewise. * mips-dis.c: Likewise. * spu-dis.c: Likewise. * disassemble.h (print_insn_aarch64): New declaration, moved from include/dis-asm.h. (print_insn_big_arm, print_insn_big_mips): Likewise. (print_insn_i386, print_insn_ia64): Likewise. (print_insn_little_arm, print_insn_little_mips): Likewise. |
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Andrew Burgess
|
7bdf4127c3 |
ld: Allow section groups to be resolved as part of a relocatable link
This commit adds a new linker feature: the ability to resolve section groups as part of a relocatable link. Currently section groups are automatically resolved when performing a final link, and are carried through when performing a relocatable link. By carried through this means that one copy of each section group (from all the copies that might be found in all the input files) is placed into the output file. Sections that are part of a section group will not match input section specifiers within a linker script and are forcibly kept as separate sections. There is a slight resemblance between section groups and common section. Like section groups, common sections are carried through when performing a relocatable link, and resolved (allocated actual space) only at final link time. However, with common sections there is an ability to force the linker to allocate space for the common sections when performing a relocatable link, there's currently no such ability for section groups. This commit adds such a mechanism. This new facility can be accessed in two ways, first there's a command line switch --force-group-allocation, second, there's a new linker script command FORCE_GROUP_ALLOCATION. If one of these is used when performing a relocatable link then the linker will resolve the section groups as though it were performing a final link, the section group will be deleted, and the members of the group will be placed like normal input sections. If there are multiple copies of the group (from multiple input files) then only one copy of the group members will be placed, the duplicate copies will be discarded. Unlike common sections that have the --no-define-common command line flag, and INHIBIT_COMMON_ALLOCATION linker script command there is no way to prevent group resolution during a final link, this is because the ELF gABI specifically prohibits the presence of SHT_GROUP sections in a fully linked executable. However, the code as written should make adding such a feature trivial, setting the new resolve_section_groups flag to false during a final link should work as you'd expect. bfd/ChangeLog: * elf.c (_bfd_elf_make_section_from_shdr): Don't initially mark SEC_GROUP sections as SEC_EXCLUDE. (bfd_elf_set_group_contents): Replace use of abort with an assert. (assign_section_numbers): Use resolve_section_groups flag instead of relocatable link type. (_bfd_elf_init_private_section_data): Use resolve_section_groups flag instead of checking the final_link flag for part of the checks in here. Fix white space as a result. * elflink.c (elf_link_input_bfd): Use resolve_section_groups flag instead of relocatable link type. (bfd_elf_final_link): Likewise. include/ChangeLog: * bfdlink.h (struct bfd_link_info): Add new resolve_section_groups flag. ld/ChangeLog: * ld.h (struct args_type): Add force_group_allocation field. * ldgram.y: Add support for FORCE_GROUP_ALLOCATION. * ldlex.h: Likewise. * ldlex.l: Likewise. * lexsup.c: Likewise. * ldlang.c (unique_section_p): Check resolve_section_groups flag not the relaxable link flag. (lang_add_section): Discard section groups when we're resolving groups. Clear the SEC_LINK_ONCE flag if we're resolving section groups. * ldmain.c (main): Initialise resolve_section_groups flag in link_info based on command line flags. * testsuite/ld-elf/group11.d: New file. * testsuite/ld-elf/group12.d: New file. * testsuite/ld-elf/group12.ld: New file. * NEWS: Mention new features. * ld.texinfo (Options): Document --force-group-allocation. (Miscellaneous Commands): Document FORCE_GROUP_ALLOCATION. |
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Alan Modra
|
f378ab099d |
PPC64_OPT_LOCALENTRY
ELFv2 functions with localentry:0 are those with a single entry point, ie. global entry == local entry, and that have no requirement on r2 or r12, and guarantee r2 is unchanged on return. Such an external function can be called via the PLT without saving r2 or restoring it on return, avoiding a common load-hit-store for small functions. The optimization is attractive. The TOC pointer load-hit-store is a major reason why calls to small functions that need no register saves, or with shrink-wrap, no register saves on a fast path, are slow on powerpc64le. To be safe, this optimization needs ld.so support to check that the run-time matches link-time function implementation. If a function in a shared library with st_other localentry non-zero is called without saving and restoring r2, r2 will be trashed on return, leading to segfaults. For that reason the optimization does not happen for weak functions since a weak definition is a fairly solid hint that the function will likely be overridden. I'm also not enabling the optimization by default unless glibc-2.26 is detected, which should have the ld.so checks implemented. bfd/ * elf64-ppc.c (struct ppc_link_hash_table): Add has_plt_localentry0. (ppc64_elf_merge_symbol_attribute): Merge localentry bits from dynamic objects. (is_elfv2_localentry0): New function. (ppc64_elf_tls_setup): Default params->plt_localentry0. (plt_stub_size): Adjust size for tls_get_addr_opt stub. (build_tls_get_addr_stub): Use a simpler stub when r2 is not saved. (ppc64_elf_size_stubs): Leave stub_type as ppc_stub_plt_call for optimized localentry:0 stubs. (ppc64_elf_build_stubs): Save r2 in ELFv2 __glink_PLTresolve. (ppc64_elf_relocate_section): Leave nop unchanged for optimized localentry:0 stubs. (ppc64_elf_finish_dynamic_sections): Set PPC64_OPT_LOCALENTRY in DT_PPC64_OPT. * elf64-ppc.h (struct ppc64_elf_params): Add plt_localentry0. include/ * elf/ppc64.h (PPC64_OPT_LOCALENTRY): Define. ld/ * emultempl/ppc64elf.em (params): Init plt_localentry0 field. (enum ppc64_opt): New, replacing OPTION_* defines. Add OPTION_PLT_LOCALENTRY, and OPTION_NO_PLT_LOCALENTRY. (PARSE_AND_LIST_*): Support --plt-localentry and --no-plt-localentry. * testsuite/ld-powerpc/elfv2so.d: Update. * testsuite/ld-powerpc/powerpc.exp (TLS opt 5): Use --no-plt-localentry. * testsuite/ld-powerpc/tlsopt5.d: Update. |
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Eli Zaretskii
|
b9c6833008 |
Fix MinGW compilation warnings due to environ.h
include/ChangeLog: 2017-05-31 Eli Zaretskii <eliz@gnu.org> * environ.h: Add #ifndef guard. |
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Anton Kolesov
|
940171d086 |
[ARC] Add arc-cpu.def with processor definitions
This patch extracts ARC CPU definitions from gas/config/tc-arc.c (cpu_types) into a separate file arc-cpu.def. This will allow reuse of CPU type definition in multiple places where it might be needed, for example in disassembler. This will help ensure that gas and disassembker use same option values for CPUs. arc-cpu.def file relies on preprocessor macroses which are defined somewhere else. This for example multiple C files to include arc-cpu.def, but define different macroses, therefore creating different structures. include/ChangeLog: yyyy-mm-dd Anton Kolesov <anton.kolesov@synopsys.com> * elf/arc-cpu.def: New file. gas/ChangeLog: yyyy-mm-dd Anton Kolesov <anton.kolesov@synopsys.com> * config/tc-arc.c (cpu_types): Include arc-cpu.def Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com> |
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Andreas Krebbel
|
a09f258601 |
S/390: Improve error checking for optional operands
So far we only had an instruction flag which made an arbitrary number of operands optional. This limits error checking capabilities for instructions marked that way. With this patch the optparm flag only allows a single optional parameter and another one is added (optparm2) allowing 2 optional arguments. Hopefully we won't need more than that in the future. So far there will be only a single use of optparm2. gas/ChangeLog: 2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config/tc-s390.c (md_gather_operands): Support new optparm2 instruction flag. include/ChangeLog: 2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * opcode/s390.h: Add new instruction flags optparm2. opcodes/ChangeLog: 2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * s390-dis.c (s390_print_insn_with_opcode): Support new optparm2 instruction flag. * s390-mkopc.c (main): Recognize the new instruction flag when parsing instruction list. |
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Andreas Krebbel
|
bfcfbe611b |
S/390: Remove optional operand flag.
The per operand optional flag hasn't been used for quite some time. Cleanup some remains. include/ChangeLog: 2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * opcode/s390.h: Remove S390_OPERAND_OPTIONAL. gas/ChangeLog: 2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config/tc-s390.c (md_gather_operands): Remove code dealing with S390_OPERAND_OPTIONAL. |
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Yao Qi
|
88c1242dc0 |
Move print_insn_XXX to an opcodes internal header
With the changes done in previous patches, print_insn_XXX functions don't have to be external visible out of opcodes, because both gdb and objdump select disassemblers through a single interface. This patch moves these print_insn_XXX declarations from include/dis-asm.h to opcodes/disassemble.h, which is a new header added by this patch. include: 2017-05-24 Yao Qi <yao.qi@linaro.org> * dis-asm.h: Move some function declarations to opcodes/disassemble.h. opcodes: 2017-05-24 Yao Qi <yao.qi@linaro.org> * alpha-dis.c: Include disassemble.h, don't include dis-asm.h. * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise. * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise. * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise. * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise. * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise. * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise. * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise. * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise. * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise. * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise. * moxie-dis.c, msp430-dis.c, mt-dis.c: * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise. * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise. * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise. * rl78-dis.c, s390-dis.c, score-dis.c: Likewise. * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise. * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise. * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise. * v850-dis.c, vax-dis.c, visium-dis.c: Likewise. * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise. * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise. * z80-dis.c, z8k-dis.c: Likewise. * disassemble.h: New file. |
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Yao Qi
|
003ca0fd22 |
Refactor disassembler selection
Nowadays, opcodes/disassemble.c:disassembler selects the proper disassembler according to ABFD only. However, it actually selects disassemblers according to arch, mach, endianess, and abfd. This patch adds them to the parameters of disassembler, so that its caller can still select disassemblers in case that abfd is NULL (a typical case in GDB). There isn't any functionality change. binutils: 2017-05-24 Yao Qi <yao.qi@linaro.org> * objdump.c (disassemble_data): Caller update. include: 2017-05-24 Yao Qi <yao.qi@linaro.org> * dis-asm.h (disassembler): Update declaration. opcodes: 2017-05-24 Yao Qi <yao.qi@linaro.org> * disassemble.c (disassembler): Add arguments a, big and mach. Use them. sim/common: 2017-05-24 Yao Qi <yao.qi@linaro.org> * sim-trace.c (trace_disasm): Caller update. |
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claziss
|
575dcd27f8 |
[ARC] Update MAX_INSN_FLGS.
It is required to parse instructions like ldb.x.a.di. include/ 2017-05-23 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (MAX_INSN_FLGS): Update to 4. |
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H.J. Lu
|
04ef582ace |
x86: Add NOTRACK prefix support
For register indirect branches, NOTRACK prefix (0x3e), which is also the DS segment register prefix, can be used to ignore the CET indirect branch track. gas/ * config/tc-i386.c (REX_PREFIX): Changed to 7. (NOTRACK_PREFIX): New. (MAX_PREFIXES): Changed to 8. (_i386_insn): Add notrack_prefix. (PREFIX_GROUP): Add PREFIX_DS. (add_prefix): Return PREFIX_DS for DS_PREFIX_OPCODE. (md_assemble): Check if NOTRACK prefix is supported. (parse_insn): Set notrack_prefix and issue an error for other prefixes after NOTRACK prefix. * testsuite/gas/i386/i386.exp: Run tests for NOTRACK prefix. * testsuite/gas/i386/notrack-intel.d: New file. * testsuite/gas/i386/notrack.d: Likewise. * testsuite/gas/i386/notrack.s: Likewise. * testsuite/gas/i386/notrackbad.l: Likewise. * testsuite/gas/i386/notrackbad.s: Likewise. * testsuite/gas/i386/x86-64-notrack-intel.d: Likewise. * testsuite/gas/i386/x86-64-notrack.d: Likewise. * testsuite/gas/i386/x86-64-notrack.s: Likewise. * testsuite/gas/i386/x86-64-notrackbad.l: Likewise. * testsuite/gas/i386/x86-64-notrackbad.s: Likewise. include/ * include/opcode/i386.h (NOTRACK_PREFIX_OPCODE): New. opcodes/ * i386-dis.c (NOTRACK_Fixup): New. (NOTRACK): Likewise. (NOTRACK_PREFIX): Likewise. (last_active_prefix): Likewise. (reg_table): Use NOTRACK on indirect call and jmp. (ckprefix): Set last_active_prefix. (prefix_name): Return "notrack" for NOTRACK_PREFIX. * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk. * i386-opc.h (NoTrackPrefixOk): New. (i386_opcode_modifier): Add notrackprefixok. * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp. Add notrack. * i386-tbl.h: Regenerated. |
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Jose E. Marchesi
|
6451799480 |
binutils: support for the SPARC M8 processor
This patch adds support for the new SPARC M8 processor (implementing OSA
2017) to binutils.
New instructions:
- Dictionary Unpack
+ dictunpack
- Partitioned Compare with shifted result
+ Signed variants: fpcmp{le,gt,eq,ne}{8,16,32}shl
+ Unsigned variants: fpcmpu{le,gt}{8,16,32}shl
- Partitioned Dual-Equal compared, with shifted result
+ fpcmpde{8,16,32}shl
- Partitioned Unsigned Range Compare, with shifted result
+ fpcmpur{8,16,32}shl
- 64-bit shifts on Floating-Point registers
+ fps{ll,ra,rl}64x
- Misaligned loads and stores
+ ldm{sh,uh,sw,uw,x,ux}
+ ldm{sh,uh,sw,uw,x,ux}a
+ ldmf{s,d}
+ ldmf{s,d}a
+ stm{h,w,x}
+ stm{h,w,x}a
+ stmf{s,d}
+ stmf{s,d}a
- Oracle Numbers
+ on{add,sub,mul,div}
- Reverse Bytes/Bits
+ revbitsb
+ revbytes{h,w,x}
- Run-Length instructions
+ rle_burst
+ rle_length
- New crypto instructions
+ sha3
- Instruction to read the new register %entropy
+ rd %entropy
New Alternate Address Identifiers:
- 0x24, #ASI_CORE_COMMIT_COUNT
- 0x24, #ASI_CORE_SELECT_COUNT
- 0x48, #ASI_ARF_ECC_REG
- 0x53, #ASI_ITLB_PROBE
- 0x58, #ASI_DSFAR
- 0x5a, #ASI_DTLB_PROBE_PRIMARY
- 0x5b, #ASI_DTLB_PROBE_REAL
- 0x64, #ASI_CORE_SELECT_COMMIT_NHT
The new assembler command-line options for selecting the M8 architecture
are:
-Av9m8 or -Asparc6 for 64-bit binaries.
-Av8plusm8 for 32-bit (v8+) binaries.
The corresponding disassembler command-line options are:
-msparc:v9m8 for 64-bit binaries.
-msparc:v8plusm8 for 32-bit (v8+) binaries.
Tested for regressions in the following targets:
sparc-aout sparc-linux sparc-vxworks sparc64-linux
bfd/ChangeLog:
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* archures.c (bfd_mach_sparc_v9m8): Define.
(bfd_mach_sparc_v8plusm8): Likewise.
(bfd_mach_sparc_v9_p): Adjust to M8.
(bfd_mach_sparc_64bit_p): Likewise.
* aoutx.h (machine_type): Handle bfd_mach_sparc_v9m8 and
bfd_mach_sparc_v8plusm8.
* bfd-in2.h: Regenerated.
* cpu-sparc.c (arch_info_struct): Entries for sparc:v9m8 and
sparc:v8plusm8.
* elfxx-sparc.c (_bfd_sparc_elf_object_p): Handle
bfd_mach_sparc_v8plusm8 and bfd_mach_sparc_v9m8 using the new hw
capabilities ONADDSUB, ONMUL, ONDIV, DICTUNP, FPCPSHL, RLE and
SHA3.
* elf32-sparc.c (elf32_sparc_final_write_processing): Handle
bfd_mach_sparc_v8plusm8.
binutils/ChangeLog:
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* NEWS: Mention the SPARC M8 support.
gas/ChangeLog:
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_arch_table): Entries for `sparc6',
`v9m8' and `v8plusm8'.
(sparc_md_end): Handle SPARC_OPCODE_ARCH_M8.
(get_hwcap_name): Support the M8 hardware capabilities.
(sparc_ip): Handle new operand types.
* doc/c-sparc.texi (Sparc-Opts): Document -Av9m8, -Av8plusm8 and
-Asparc6, and the corresponding -xarch aliases.
* testsuite/gas/sparc/sparc6.s: New file.
* testsuite/gas/sparc/sparc6.d: Likewise.
* testsuite/gas/sparc/sparc6-diag.s: Likewise.
* testsuite/gas/sparc/sparc6-diag.l: Likewise.
* testsuite/gas/sparc/fpcmpshl.s: Likewise.
* testsuite/gas/sparc/fpcmpshl.d: Likewise.
* testsuite/gas/sparc/fpcmpshl-diag.s: Likewise.
* testsuite/gas/sparc/fpcmpshl-diag.l: Likewise.
* testsuite/gas/sparc/ldm-stm.s: Likewise.
* testsuite/gas/sparc/ldm-stm.d: Likewise.
* testsuite/gas/sparc/ldm-stm-diag.s: Likewise.
* testsuite/gas/sparc/ldm-stm-diag.l: Likewise.
* testsuite/gas/sparc/ldmf-stmf.s: Likewise.
* testsuite/gas/sparc/ldmf-stmf.d: Likewise.
* testsuite/gas/sparc/ldmf-stmf-diag.s: Likewise.
* testsuite/gas/sparc/ldmf-stmf-diag.l: Likewise.
* testsuite/gas/sparc/on.s: Likewise.
* testsuite/gas/sparc/on.d: Likewise.
* testsuite/gas/sparc/on-diag.s: Likewise.
* testsuite/gas/sparc/on-diag.l: Likewise.
* testsuite/gas/sparc/rle.s: Likewise.
* testsuite/gas/sparc/rle.d: Likewise.
* testsuite/gas/sparc/sparc.exp (gas_64_check): Run new tests.
* testsuite/gas/sparc/rdasr.s: Add test for RDENTROPY.
* testsuite/gas/sparc/rdasr.d: Likewise.
include/ChangeLog:
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* elf/sparc.h (ELF_SPARC_HWCAP2_SPARC6): Define.
(ELF_SPARC_HWCAP2_ONADDSUB): Likewise.
(ELF_SPARC_HWCAP2_ONMUL): Likewise.
(ELF_SPARC_HWCAP2_ONDIV): Likewise.
(ELF_SPARC_HWCAP2_DICTUNP): Likewise.
(ELF_SPARC_HWCAP2_FPCMPSHL): Likewise.
(ELF_SPARC_HWCAP2_RLE): Likewise.
(ELF_SPARC_HWCAP2_SHA3): Likewise.
* opcode/sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_M8
and adjust SPARC_OPCODE_ARCH_MAX.
(HWCAP2_SPARC6): Define.
(HWCAP2_ONADDSUB): Likewise.
(HWCAP2_ONMUL): Likewise.
(HWCAP2_ONDIV): Likewise.
(HWCAP2_DICTUNP): Likewise.
(HWCAP2_FPCMPSHL): Likewise.
(HWCAP2_RLE): Likewise.
(HWCAP2_SHA3): Likewise.
(OPM): Likewise.
(OPMI): Likewise.
(ONFCN): Likewise.
(REVFCN): Likewise.
(SIMM10): Likewise.
opcodes/ChangeLog:
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
(X_IMM2): Define.
(compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
bfd_mach_sparc_v9m8.
(print_insn_sparc): Handle new operand types.
* sparc-opc.c (MASK_M8): Define.
(v6): Add MASK_M8.
(v6notlet): Likewise.
(v7): Likewise.
(v8): Likewise.
(v9): Likewise.
(v9a): Likewise.
(v9b): Likewise.
(v9c): Likewise.
(v9d): Likewise.
(v9e): Likewise.
(v9v): Likewise.
(v9m): Likewise.
(v9andleon): Likewise.
(m8): Define.
(HWS_VM8): Define.
(HWS2_VM8): Likewise.
(sparc_opcode_archs): Add entry for "m8".
(sparc_opcodes): Add OSA2017 and M8 instructions
dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
fpx{ll,ra,rl}64x,
ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
(asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
ASI_CORE_SELECT_COMMIT_NHT.
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Alan Modra
|
bc4e12ded1 |
Rename non_ir_ref to non_ir_ref_regular
Since the flag is now set only for regular object refs. include/ * bfdlink.h (struct bfd_link_hash_entry <non_ir_ref>): Rename to non_ir_ref_regular. bfd/ * elf-m10300.c: Rename occurrences of non_ir_ref. * elf32-arm.c: Likewise. * elf32-bfin.c: Likewise. * elf32-cr16.c: Likewise. * elf32-cris.c: Likewise. * elf32-d10v.c: Likewise. * elf32-dlx.c: Likewise. * elf32-fr30.c: Likewise. * elf32-frv.c: Likewise. * elf32-hppa.c: Likewise. * elf32-i370.c: Likewise. * elf32-i386.c: Likewise. * elf32-iq2000.c: Likewise. * elf32-lm32.c: Likewise. * elf32-m32c.c: Likewise. * elf32-m32r.c: Likewise. * elf32-m68hc1x.c: Likewise. * elf32-m68k.c: Likewise. * elf32-mcore.c: Likewise. * elf32-metag.c: Likewise. * elf32-microblaze.c: Likewise. * elf32-moxie.c: Likewise. * elf32-msp430.c: Likewise. * elf32-mt.c: Likewise. * elf32-nios2.c: Likewise. * elf32-or1k.c: Likewise. * elf32-ppc.c: Likewise. * elf32-rl78.c: Likewise. * elf32-s390.c: Likewise. * elf32-score.c: Likewise. * elf32-score7.c: Likewise. * elf32-sh.c: Likewise. * elf32-tic6x.c: Likewise. * elf32-tilepro.c: Likewise. * elf32-v850.c: Likewise. * elf32-vax.c: Likewise. * elf32-xstormy16.c: Likewise. * elf32-xtensa.c: Likewise. * elf64-alpha.c: Likewise. * elf64-hppa.c: Likewise. * elf64-ia64-vms.c: Likewise. * elf64-mmix.c: Likewise. * elf64-ppc.c: Likewise. * elf64-s390.c: Likewise. * elf64-sh64.c: Likewise. * elf64-x86-64.c: Likewise. * elflink.c: Likewise. * elfnn-aarch64.c: Likewise. * elfnn-ia64.c: Likewise. * elfnn-riscv.c: Likewise. * elfxx-mips.c: Likewise. * elfxx-sparc.c: Likewise. * elfxx-tilegx.c: Likewise. * linker.c: Likewise. ld/ * plugin.c: Rename occurrences of non_ir_ref. |
||
|
Alan Modra
|
4070765b1a |
non_ir_ref_dynamic
dynamic_ref_after_ir_def is a little odd compared to other symbol flags in that as the name suggests, it is set only for certain references after a definition. It turns out that setting a flag for any non-ir reference from a dynamic object can be used to solve the problem for which this flag was invented, which I think is a cleaner. This patch does that, and sets non_ir_ref only for regular object references. include/ * bfdlink.h (struct bfd_link_hash_entry): Update non_ir_ref comment. Rename dynamic_ref_after_ir_def to non_ir_ref_dynamic. ld/ * plugin.c (is_visible_from_outside): Use non_ir_ref_dynamic. (plugin_notice): Set non_ir_ref for references from regular objects, non_ir_ref_dynamic for references from dynamic objects. bfd/ * elf64-ppc.c (add_symbol_adjust): Transfer non_ir_ref_dynamic. * elflink.c (elf_link_add_object_symbols): Update to use non_ir_ref_dynamic. (elf_link_input_bfd): Test non_ir_ref_dynamic in addition to non_ir_ref. * linker.c (_bfd_generic_link_add_one_symbol): Likewise. |
||
Maciej W. Rozycki
|
25499ac7ee |
MIPS16e2: Add MIPS16e2 ASE support
Add MIPS16e2 ASE support as per the architecture specification[1],
including in particular:
1. A new ELF ASE flag to mark MIPS16e2 binaries.
2. MIPS16e2 instruction assembly support, including a relaxation update
to use LUI rather than an LI/SLL instruction pair for loading the
high part of 32-bit addresses.
3. MIPS16e2 instruction disassembly support, including updated rules for
extended forms of instructions that are now subdecoded and therefore
do not alias to the original MIPS16 ISA revision instructions even
for encodings that are not valid in the MIPS16e2 instruction set.
Add `-mmips16e2' and `-mno-mips16e2' GAS command-line options and their
corresponding `mips16e2' and `no-mips16e2' settings for the `.set' and
`.module' pseudo-ops. Control the availability of the MT ASE subset of
the MIPS16e2 instruction set with a combination of these controls and
the preexisting MT ASE controls.
Parts of this change by Matthew Fortune and Andrew Bennett.
References:
[1] "MIPS32 Architecture for Programmers: MIPS16e2 Application-Specific
Extension Technical Reference Manual", Imagination Technologies
Ltd., Document Number: MD01172, Revision 01.00, April 26, 2016
include/
* elf/mips.h (AFL_ASE_MIPS16E2): New macro.
(AFL_ASE_MASK): Adjust accordingly.
* opcode/mips.h: Document new operand codes defined.
(mips_operand_type): Add OP_REG28 enum value.
(INSN2_SHORT_ONLY): Update description.
(ASE_MIPS16E2, ASE_MIPS16E2_MT): New macros.
bfd/
* elfxx-mips.c (print_mips_ases): Handle MIPS16e2 ASE.
opcodes/
* mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
(mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
(print_insn_arg) <OP_REG28>: Add handler.
(validate_insn_args) <OP_REG28>: Handle.
(print_mips16_insn_arg): Handle MIPS16 instructions that require
32-bit encoding and 9-bit immediates.
(print_insn_mips16): Handle MIPS16 instructions that require
32-bit encoding and MFC0/MTC0 operand decoding.
* mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
<'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
(RD_C0, WR_C0, E2, E2MT): New macros.
(mips16_opcodes): Add entries for MIPS16e2 instructions:
GP-relative "addiu" and its "addu" spelling, "andi", "cache",
"di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
"lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
"movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
"pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
instructions, "swl", "swr", "sync" and its "sync_acquire",
"sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
"xori", "dmt", "dvpe", "emt" and "evpe". Add split
regular/extended entries for original MIPS16 ISA revision
instructions whose extended forms are subdecoded in the MIPS16e2
ISA revision: "li", "sll" and "srl".
binutils/
* readelf.c (print_mips_ases): Handle MIPS16e2 ASE.
* NEWS: Mention MIPS16e2 ASE support.
gas/
* config/tc-mips.c (RELAX_MIPS16_ENCODE): Add `e2' flag.
(RELAX_MIPS16_E2): New macro.
(RELAX_MIPS16_PIC, RELAX_MIPS16_SYM32, RELAX_MIPS16_NOMACRO)
(RELAX_MIPS16_USER_SMALL, RELAX_MIPS16_USER_EXT)
(RELAX_MIPS16_DSLOT, RELAX_MIPS16_JAL_DSLOT)
(RELAX_MIPS16_EXTENDED, RELAX_MIPS16_MARK_EXTENDED)
(RELAX_MIPS16_CLEAR_EXTENDED, RELAX_MIPS16_ALWAYS_EXTENDED)
(RELAX_MIPS16_MARK_ALWAYS_EXTENDED)
(RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED, RELAX_MIPS16_MACRO)
(RELAX_MIPS16_MARK_MACRO, RELAX_MIPS16_CLEAR_MACRO): Shift bits.
(mips16_immed_extend): New prototype.
(options): Add OPTION_MIPS16E2 and OPTION_NO_MIPS16E2 enum
values.
(md_longopts): Add "mmips16e2" and "mno-mips16e2" options.
(mips_ases): Add "mips16e2" entry.
(mips_set_ase): Handle MIPS16e2 ASE.
(insn_insert_operand): Explicitly handle immediates with MIPS16
instructions that require 32-bit encoding.
(is_opcode_valid_16): Pass enabled ASE bitmask on to
`opcode_is_member'.
(validate_mips_insn): Explicitly handle immediates with MIPS16
instructions that require 32-bit encoding.
(operand_reg_mask) <OP_REG28>: Add handler.
(match_reg28_operand): New function.
(match_operand) <OP_REG28>: Add handler.
(append_insn): Pass ASE_MIPS16E2 setting to RELAX_MIPS16_ENCODE.
(match_mips16_insn): Handle MIPS16 instructions that require
32-bit encoding and `V' and `u' operand codes.
(mips16_ip): Allow any characters except from `.' in opcodes.
(mips16_immed_extend): Handle 9-bit immediates. Do not shuffle
immediates whose width is not one of these listed.
(md_estimate_size_before_relax): Handle MIPS16e2 relaxation.
(mips_relax_frag): Likewise.
(md_convert_frag): Likewise.
(mips_convert_ase_flags): Handle MIPS16e2 ASE.
* doc/as.texinfo (Target MIPS options): Add `-mmips16e2' and
`-mno-mips16e2' options.
(-mmips16e2, -mno-mips16e2): New options.
* doc/c-mips.texi (MIPS Options): Add `-mmips16e2' and
`-mno-mips16e2' options.
(MIPS ASE Instruction Generation Overrides): Add `.set mips16e2'
and `.set nomips16e2'.
|
||
John David Anglin
|
cd85e51ad3 | Fix match and mask for 64-bit bb opcode. | ||
|
Claudiu Zissulescu
|
53a346d823 |
[ARC] Object attributes.
gas/ 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/attr-arc600.d: New file. * testsuite/gas/arc/attr-arc600_mul32x16.d: Likewise. * testsuite/gas/arc/attr-arc600_norm.d: Likewise. * testsuite/gas/arc/attr-arc601.d: Likewise. * testsuite/gas/arc/attr-arc601_mul32x16.d: Likewise. * testsuite/gas/arc/attr-arc601_mul64.d: Likewise. * testsuite/gas/arc/attr-arc601_norm.d: Likewise. * testsuite/gas/arc/attr-arc700.d: Likewise. * testsuite/gas/arc/attr-arcem.d: Likewise. * testsuite/gas/arc/attr-archs.d: Likewise. * testsuite/gas/arc/attr-autodetect-1.d: Likewise. * testsuite/gas/arc/attr-autodetect-1.s: Likewise. * testsuite/gas/arc/attr-cpu-a601.d: Likewise. * testsuite/gas/arc/attr-cpu-a601.s: Likewise. * testsuite/gas/arc/attr-cpu-a700.d: Likewise. * testsuite/gas/arc/attr-cpu-a700.s: Likewise. * testsuite/gas/arc/attr-cpu-em.d: Likewise. * testsuite/gas/arc/attr-cpu-em.s: Likewise. * testsuite/gas/arc/attr-cpu-hs.d: Likewise. * testsuite/gas/arc/attr-cpu-hs.s: Likewise. * testsuite/gas/arc/attr-em.d: Likewise. * testsuite/gas/arc/attr-em4.d: Likewise. * testsuite/gas/arc/attr-em4_dmips.d: Likewise. * testsuite/gas/arc/attr-em4_fpuda.d: Likewise. * testsuite/gas/arc/attr-em4_fpus.d: Likewise. * testsuite/gas/arc/attr-hs.d: Likewise. * testsuite/gas/arc/attr-hs34.d: Likewise. * testsuite/gas/arc/attr-hs38.d: Likewise. * testsuite/gas/arc/attr-hs38_linux.d: Likewise. * testsuite/gas/arc/attr-mul64.d: Likewise. * testsuite/gas/arc/attr-name.d: Likewise. * testsuite/gas/arc/attr-name.s: Likewise. * testsuite/gas/arc/attr-nps400.d: Likewise. * testsuite/gas/arc/attr-override-mcpu.d: Likewise. * testsuite/gas/arc/attr-override-mcpu.s * testsuite/gas/arc/attr-quarkse_em.d: Likewise. * testsuite/gas/arc/blank.s: Likewise. * testsuite/gas/elf/section2.e-arc: Likewise. * testsuite/gas/arc/cpu-pseudop-1.d: Update test. * testsuite/gas/arc/cpu-pseudop-2.d: Likewise. * testsuite/gas/arc/nps400-0.d: Likewise. * testsuite/gas/elf/elf.exp: Set target_machine for ARC. * config/tc-arc.c (opcode/arc-attrs.h): Include. (ARC_GET_FLAG, ARC_SET_FLAG, streq): Define. (arc_attribute): Declare new function. (md_pseudo_table): Add arc_attribute. (cpu_types): Rename default cpu features. (selected_cpu): Set the default OSABI flag. (mpy_option): New variable. (pic_option): Likewise. (sda_option): Likewise. (tls_option): Likewise. (feature_type, feature_list): Remove. (arc_initial_eflag): Likewise. (attributes_set_explicitly): New variable. (arc_check_feature): Check also for the conflicting features. (arc_select_cpu): Refactor assignment of selected_cpu.eflags. (arc_option): Remove setting of private flags and architecture. (check_cpu_feature): Refactor feature names. (autodetect_attributes): New function. (assemble_tokens): Use above function. (md_parse_option): Refactor feature names. (arc_attribute): New function. (arc_set_attribute_int): Likewise. (arc_set_attribute_string): Likewise. (arc_stralloc): Likewise. (arc_set_public_attributes): Likewise. (arc_md_end): Likewise. (arc_copy_symbol_attributes): Likewise. (rc_convert_symbolic_attribute): Likewise. * config/tc-arc.h (md_end): Define. (CONVERT_SYMBOLIC_ATTRIBUTE): Likewise. (TC_COPY_SYMBOL_ATTRIBUTES): Likewise. * doc/c-arc.texi: Document ARC object attributes. binutils/ 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> * readelf.c (decode_ARC_machine_flags): Recognize OSABI v4. (get_arc_section_type_name): New function. (get_section_type_name): Use the above function. (display_arc_attribute): New function. (process_arc_specific): Likewise. (process_arch_specific): Handle ARC specific information. * testsuite/binutils-all/strip-3.d: Consider ARC.attributes section. include/ 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> * elf/arc.h (SHT_ARC_ATTRIBUTES): Define. (Tag_ARC_*): Define. (E_ARC_OSABI_V4): Define. (E_ARC_OSABI_CURRENT): Reassign it. (TAG_CPU_*): Define. * opcode/arc-attrs.h: New file. * opcode/arc.h (insn_subclass_t): Assign enum values. (insn_subclass_t): Update enum with QUARKSE1, QUARKSE2, and LL64. (ARC_EA, ARC_CD, ARC_LLOCK, ARC_ATOMIC, ARC_MPY, ARC_MULT) (ARC_NPS400, ARC_DPFP, ARC_SPFP, ARC_FPU, ARC_FPUDA, ARC_SWAP) (ARC_NORM, ARC_BSCAN, ARC_UIX, ARC_TSTAMP, ARC_VBFDW) (ARC_BARREL, ARC_DSPA, ARC_SHIFT, ARC_INTR, ARC_DIV, ARC_XMAC) (ARC_CRC): Delete. bfd/ 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> * elf32-arc.c (FEATURE_LIST_NAME): Define. (CONFLICT_LIST): Likewise. (opcode/arc-attrs.h): Include. (arc_elf_print_private_bfd_data): Print OSABI v4 flag. (arc_extract_features): New file. (arc_stralloc): Likewise. (arc_elf_merge_attributes): Likewise. (arc_elf_merge_private_bfd_data): Use object attributes. (bfd_arc_get_mach_from_attributes): New function. (arc_elf_object_p): Use object attributes. (arc_elf_final_write_processing): Likewise. (elf32_arc_obj_attrs_arg_type): New function. (elf32_arc_obj_attrs_handle_unknown): Likewise. (elf32_arc_section_from_shdr): Likewise. (elf_backend_obj_attrs_vendor): Define. (elf_backend_obj_attrs_section): Likewise. (elf_backend_obj_attrs_arg_type): Likewise. (elf_backend_obj_attrs_section_type): Likewise. (elf_backend_obj_attrs_handle_unknown): Likewise. (elf_backend_section_from_shdr): Likewise. ld/ 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/ld-arc/attr-merge-0.d: New file. * testsuite/ld-arc/attr-merge-0.s: Likewise. * testsuite/ld-arc/attr-merge-0e.s: Likewise. * testsuite/ld-arc/attr-merge-1.d: Likewise. * testsuite/ld-arc/attr-merge-1.s: Likewise. * testsuite/ld-arc/attr-merge-1e.s: Likewise. * testsuite/ld-arc/attr-merge-2.d: Likewise. * testsuite/ld-arc/attr-merge-2.s: Likewise. * testsuite/ld-arc/attr-merge-3.d: Likewise. * testsuite/ld-arc/attr-merge-3.s: Likewise. * testsuite/ld-arc/attr-merge-3e.s: Likewise. * testsuite/ld-arc/attr-merge-4.s: Likewise. * testsuite/ld-arc/attr-merge-5.d: Likewise. * testsuite/ld-arc/attr-merge-5a.s: Likewise. * testsuite/ld-arc/attr-merge-5b.s: Likewise. * testsuite/ld-arc/attr-merge-conflict-isa.d: Likewise. * testsuite/ld-arc/attr-merge-err-isa.d: Likewise. * testsuite/ld-arc/attr-merge-incompatible-cpu.d: Likewise. * testsuite/ld-arc/got-01.d: Update test. * testsuite/ld-arc/attr-merge-err-quarkse.d: New file. * testsuite/ld-arc/attr-quarkse.s: Likewise. * testsuite/ld-arc/attr-quarkse2.s: Likewise. opcodes/ 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> * arc-dis.c (parse_option): Update quarkse_em option.. * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to QUARKSE1. (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2. |
||
|
H.J. Lu
|
59fa66c538 |
Handle symbol defined in IR and referenced in DSO
We need to make an IR symbol visible if it is defined in an IR object and referenced in a dynamic object. When --as-needed is used, since linker removes the IR symbol reference of the dynamic object if the dynamic object isn't needed in the first pass, the IR definition isn't visible to the dynamic object even if the dynamic object becomes needed in the second pass. Add dynamic_ref_after_ir_def to bfd_link_hash_entry to track IR symbol which is defined in an IR object and later referenced in a dynamic object. dynamic_ref_after_ir_def is preserved when restoring the symbol table for unneeded dynamic object. bfd/ PR ld/21382 * elflink.c (elf_link_add_object_symbols): Preserve dynamic_ref_after_ir_def when restoring the symbol table for unneeded dynamic object. include/ PR ld/21382 * bfdlink.h (bfd_link_hash_entry): Add dynamic_ref_after_ir_def. ld/ PR ld/21382 * plugin.c (is_visible_from_outside): Symbol may be visible from outside if dynamic_ref_after_ir_def is set. (plugin_notice): Set dynamic_ref_after_ir_def if the symbol is defined in an IR object and referenced in a dynamic object. * testsuite/ld-plugin/lto.exp: Run PR ld/21382 tests. * testsuite/ld-plugin/pr21382a.c: New file. * testsuite/ld-plugin/pr21382b.c: Likewise. |
||
|
Alan Modra
|
954b63d4c8 |
Implement -z dynamic-undefined-weak
-z nodynamic-undefined-weak is only implemented for x86. (The sparc backend has some support code but doesn't enable the option by including ld/emulparams/dynamic_undefined_weak.sh, and since the support looks like it may be broken I haven't enabled it.) This patch adds the complementary -z dynamic-undefined-weak, extends both options to affect building of shared libraries as well as executables, and adds support for the option on powerpc. include/ * bfdlink.h (struct bfd_link_info <dynamic_undefined_weak>): Revise comment. bfd/ * elflink.c (_bfd_elf_adjust_dynamic_symbol): Hide undefweak or make dynamic for info->dynamic_undefined_weak 0 and 1. * elf32-ppc.c:Formatting. (ensure_undefweak_dynamic): Don't make dynamic when info->dynamic_undefined_weak is zero. (allocate_dynrelocs): Discard undefweak dyn_relocs for info->dynamic_undefined_weak. Discard undef dyn_relocs when not default visibility. Discard undef and undefweak dyn_relocs earlier. (ppc_elf_relocate_section): Adjust to suit. * elf64-ppc.c: Formatting. (ensure_undefweak_dynamic): Don't make dynamic when info->dynamic_undefined_weak is zero. (allocate_dynrelocs): Discard undefweak dyn_relocs for info->dynamic_undefined_weak. Discard them earlier. ld/ * ld.texinfo (dynamic-undefined-weak): Document. (nodynamic-undefined-weak): Document that this option now can be used with shared libs. * emulparams/dynamic_undefined_weak.sh: Support -z dynamic-undefined-weak. * emulparams/elf32ppccommon.sh: Include dynamic_undefined_weak.sh. * testsuite/ld-undefined/weak-undef.exp (undef_weak_so), (undef_weak_exe): New. Use them. Add -z dynamic-undefined-weak and -z nodynamic-undefined-weak tests. * Makefile.am: Update powerpc dependencies. * Makefile.in: Regenerate. |
||
|
Alan Modra
|
c03dc33b60 |
Reorder PPC_OPCODE_* and set PPC_OPCODE_TMR for e6500
PPC_OPCODE_* renumbered to fill the gaps left by previous patches, and reordered chronologically just because. I kept PPC_OPCODE_TMR because presumably it might be used in future APUinfo for e6500. include/ * opcode/ppc.h (PPC_OPCODE_*): Renumber and order chronologically. (PPC_OPCODE_SPE): Comment on this and other bits used for APUinfo. opcodes/ * ppc-dis.c (ppc_opts): Formatting. Set PPC_OPCODE_TMR for e6500. * ppc-opc.c (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500. |
||
|
Alan Modra
|
ef85eab0ec |
Bye bye PPC_OPCODE_HTM and -mhtm
The -mhtm option is fairly useless too. include/ * opcode/ppc.h (PPC_OPCODE_HTM): Delete. gas/ * config/tc-ppc.c (md_show_usage): Delete mention of -mhtm. * testsuite/gas/ppc/htm.d: Pass -mpower8 and -Mpower8. opcodes/ * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_HTM and "htm". * ppc-opc.c (PPCHTM): Define as PPC_OPCODE_POWER8. |
||
|
Alan Modra
|
9570835e55 |
Bye Bye PPC_OPCODE_VSX3
This bit is also useless as it can be replaced with PPC_OPCODE_POWER9. Defining the VSX2 and VSX3 selection based on cpu bits also lets the assembler/disassembler distinguish between the power7 VSX opcodes and the power8 ones. Note that this change means -mvsx now reverts back to just adding the power7 VSX insns. include/ * opcode/ppc.h (PPC_OPCODE_VSX3): Delete. opcodes/ * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_VSX3. * ppc-opc.c (PPCVSX2): Define as PPC_OPCODE_POWER8. (PPCVSX3): Define as PPC_OPCODE_POWER9. |
||
|
Alan Modra
|
9a85b496ac |
Bye bye PPC_OPCODE_ALTIVEC2
This bit is worse than useless. Using it prevents the assembler and disassembler distinguishing between opcodes added for power8 and those added for power9. include/ * opcode/ppc.h (PPC_OPCODE_ALTIVEC2): Delete. opcodes/ * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2. * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500. (PPCVEC3): Define as PPC_OPCODE_POWER9. |
||
Pip Cet
|
62ecb94c4a |
Add support for disassembling WebAssembly opcodes.
include * dis-asm.h: Add prototypes for wasm32 disassembler. opcodes * Makefile.am: Add wasm32-dis.c. * configure.ac: Add wasm32-dis.c to wasm32 target. * disassemble.c: Add wasm32 disassembler code. * wasm32-dis.c: New file. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate. * po/opcodes.pot: Regenerate. gas * testsuite/gas/wasm32/allinsn.d: Adjust test for disassembler changes. * testsuite/gas/wasm32/disass.d: New test. * testsuite/gas/wasm32/disass.s: New test. * testsuite/gas/wasm32/disass-2.d: New test. * testsuite/gas/wasm32/disass-2.s: New test. * testsuite/gas/wasm32/reloc.d: Adjust test for changed reloc names. * testsuite/gas/wasm32/reloc.s: Update test for changed assembler syntax. * testsuite/gas/wasm32/wasm32.exp: Run new tests. Expect allinsn test to succeed. |
||
Pedro Alves
|
f995bbe8e6 |
-Wwrite-strings: Constify struct disassemble_info's disassembler_options field
The memory disassemble_info::disassembler_options points to is always owned by the client. I.e., that field is an non-owning, observing pointer. Thus const makes sense. Are the include/ and opcodes/ bits OK? Tested on x86_64 Fedora 23, built with --enable-targets=all. include/ChangeLog: 2017-04-05 Pedro Alves <palves@redhat.com> * dis-asm.h (disassemble_info) <disassembler_options>: Now a "const char *". (next_disassembler_option): Constify. opcodes/ChangeLog: 2017-04-05 Pedro Alves <palves@redhat.com> * arc-dis.c (parse_option, parse_disassembler_options): Constify. * arm-dis.c (parse_arm_disassembler_options): Constify. * ppc-dis.c (powerpc_init_dialect): Constify local. * vax-dis.c (parse_disassembler_options): Constify. gdb/ChangeLog: 2017-04-05 Pedro Alves <palves@redhat.com> * arm-tdep.c (show_disassembly_style_sfunc): Constify local. * disasm.c (set_disassembler_options): Constify local. * i386-tdep.c (i386_print_insn): Remove cast and FIXME comment. |
||
|
H.J. Lu
|
a91e1603af |
Support ELF SHF_GNU_MBIND and PT_GNU_MBIND_XXX
Mark an ALLOC section, which should be placed in special memory area,
with SHF_GNU_MBIND. Its sh_info field indicates the special memory
type. GNU_MBIND section names start with ".mbind" so that they are
placed as orphan sections by linker. All input GNU_MBIND sections
with the same sh_type, sh_flags and sh_info are placed in one output
GNU_MBIND section. In executable and shared object, create a
GNU_MBIND segment for each GNU_MBIND section and its segment type is
PT_GNU_MBIND_LO plus the sh_info value. Each GNU_MBIND segment is
aligned at page boundary.
The assembler syntax:
.section .mbind.foo,"adx",%progbits
^ 0: Special memory type.
|
'd' for SHF_GNU_MBIND.
.section .mbind.foo,"adx",%progbits,0x1
^ 1: Special memory type.
|
'd' for SHF_GNU_MBIND.
.section .mbind.bar,"adG",%progbits,.foo_group,comdat,0x2
^ 2: Special memory type.
|
'd' for SHF_GNU_MBIND.
bfd/
* elf.c (get_program_header_size): Add a GNU_MBIND segment for
each GNU_MBIND section and align GNU_MBIND section to page size.
(_bfd_elf_map_sections_to_segments): Create a GNU_MBIND
segment for each GNU_MBIND section.
(_bfd_elf_init_private_section_data): Copy sh_info from input
for GNU_MBIND section.
binutils/
* NEWS: Mention support for ELF SHF_GNU_MBIND and
PT_GNU_MBIND_XXX.
* readelf.c (get_segment_type): Handle PT_GNU_MBIND_XXX.
(get_elf_section_flags): Handle SHF_GNU_MBIND.
(process_section_headers): Likewise.
* testsuite/binutils-all/mbind1.s: New file.
* testsuite/binutils-all/objcopy.exp: Run readelf test on
mbind1.s.
gas/
* NEWS: Mention support for ELF SHF_GNU_MBIND.
* config/obj-elf.c (section_match): New.
(get_section): Match both sh_info and group name.
(obj_elf_change_section): Add argument for sh_info. Pass both
sh_info and group name to get_section. Issue an error for
SHF_GNU_MBIND section without SHF_ALLOC. Set sh_info.
(obj_elf_parse_section_letters): Set SHF_GNU_MBIND for 'd'.
(obj_elf_section): Support SHF_GNU_MBIND section info.
* config/obj-elf.h (obj_elf_change_section): Add argument for
sh_info.
* config/tc-arm.c (start_unwind_section): Pass 0 as sh_info to
obj_elf_change_section.
* config/tc-ia64.c (obj_elf_vms_common): Likewise.
* config/tc-microblaze.c (microblaze_s_data): Likewise.
(microblaze_s_sdata): Likewise.
(microblaze_s_rdata): Likewise.
(microblaze_s_bss): Likewise.
* config/tc-mips.c (s_change_section): Likewise.
* config/tc-msp430.c (msp430_profiler): Likewise.
* config/tc-rx.c (parse_rx_section): Likewise.
* config/tc-tic6x.c (tic6x_start_unwind_section): Likewise.
* doc/as.texinfo: Document 'd' for SHF_GNU_MBIND.
* testsuite/gas/elf/elf.exp: Run section12a, section12b and
section13.
* testsuite/gas/elf/section10.d: Updated.
* testsuite/gas/elf/section10.s: Likewise.
* testsuite/gas/elf/section12.s: New file.
* testsuite/gas/elf/section12a.d: Likewise.
* testsuite/gas/elf/section12b.d: Likewise.
* testsuite/gas/elf/section13.l: Likewise.
* testsuite/gas/elf/section13.d: Likewise.
* testsuite/gas/elf/section13.s: Likewise.
include/
* elf/common.h (PT_GNU_MBIND_NUM): New.
(PT_GNU_MBIND_LO): Likewise.
(PT_GNU_MBIND_HI): Likewise.
(SHF_GNU_MBIND): Likewise.
ld/
* NEWS: Mention support for ELF SHF_GNU_MBIND and
PT_GNU_MBIND_XXX.
* emultempl/elf32.em (gld${EMULATION_NAME}_place_orphan): Place
input GNU_MBIND sections with the same type, attributes and
sh_info field into a single output GNU_MBIND section.
* testsuite/ld-elf/elf.exp: Run mbind2a and mbind2b.
* testsuite/ld-elf/mbind1.s: New file.
* testsuite/ld-elf/mbind1a.d: Likewise.
* testsuite/ld-elf/mbind1b.d: Likewise.
* testsuite/ld-elf/mbind1c.d: Likewise.
* testsuite/ld-elf/mbind2a.s: Likewise.
* testsuite/ld-elf/mbind2b.c: Likewise.
|
||
Palmer Dabbelt
|
b52920324f |
RISC-V: Resurrect GP-relative disassembly hints
We missed a "_gp" when changing the GP symbol. To make sure that
doesn't happen again, we now use the same definition everywhere (thanks,
Nick).
include/ChangeLog:
2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
* elf/riscv.h (RISCV_GP_SYMBOL): New define.
bfd/ChangeLog:
2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
* elfnn-riscv.c (GP_NAME): Delete.
(riscv_global_pointer_value): Change GP_NAME to RISCV_GP_SYMBOL.
(_bfd_riscv_relax_lui): Likewise.
opcodes/ChangeLog:
2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
* riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
RISCV_GP_SYMBOL.
|
||
Andrew Waterman
|
858f82bf7e |
RISC-V: Add physical memory protection CSRs
2017-03-27 Andrew Waterman <andrew@sifive.com>
* opcode/riscv-opc.h (CSR_PMPCFG0): New define.
(CSR_PMPCFG1): Likewise.
(CSR_PMPCFG2): Likewise.
(CSR_PMPCFG3): Likewise.
(CSR_PMPADDR0): Likewise.
(CSR_PMPADDR1): Likewise.
(CSR_PMPADDR2): Likewise.
(CSR_PMPADDR3): Likewise.
(CSR_PMPADDR4): Likewise.
(CSR_PMPADDR5): Likewise.
(CSR_PMPADDR6): Likewise.
(CSR_PMPADDR7): Likewise.
(CSR_PMPADDR8): Likewise.
(CSR_PMPADDR9): Likewise.
(CSR_PMPADDR10): Likewise.
(CSR_PMPADDR11): Likewise.
(CSR_PMPADDR12): Likewise.
(CSR_PMPADDR13): Likewise.
(CSR_PMPADDR14): Likewise.
(CSR_PMPADDR15): Likewise.
(pmpcfg0): Declare register.
(pmpcfg1): Likewise.
(pmpcfg2): Likewise.
(pmpcfg3): Likewise.
(pmpaddr0): Likewise.
(pmpaddr1): Likewise.
(pmpaddr2): Likewise.
(pmpaddr3): Likewise.
(pmpaddr4): Likewise.
(pmpaddr5): Likewise.
(pmpaddr6): Likewise.
(pmpaddr7): Likewise.
(pmpaddr8): Likewise.
(pmpaddr9): Likewise.
(pmpaddr10): Likewise.
(pmpaddr11): Likewise.
(pmpaddr12): Likewise.
(pmpaddr13): Likewise.
(pmpaddr14): Likewise.
(pmpaddr15): Likewise.
|
||
|
Pip Cet
|
f96bd6c2d7 |
Add support for the WebAssembly file format and the wasm32 ELF conversion to gas and the binutils.
binutils * readelf.c: Add support for wasm32 ELF format WebAssembly files. (guess_is_rela): Likewise. (dump_relocations): Likewise. (is_32bit_abs_reloc): Likewise. (is_none_reloc_): Likewise. * NEWS: Mention the new support. * testsuite/lib/binutils-common.exp (is_elf_format): Mark wasm32 as ELF target. (supports_gnu_unique): Mark wasm32 as supporting STB_GNU_UNIQUE. * testsuite/binutils-all/nm.exp: Mark wasm32 as requiring .size annotations. * testsuite/binutils-all/wasm32: New directory. * testsuite/binutils-all/wasm32/create-wasm.d: New file. * testsuite/binutils-all/wasm32/create-wasm.s: Likewise. * testsuite/binutils-all/wasm32/custom-section.d: Likewise. * testsuite/binutils-all/wasm32/custom-section.s: Likewise. * testsuite/binutils-all/wasm32/invalid-wasm-1.d: Likewise. * testsuite/binutils-all/wasm32/invalid-wasm-1.s: Likewise. * testsuite/binutils-all/wasm32/long-sections.d: Likewise. * testsuite/binutils-all/wasm32/long-sections.s: Likewise. * testsuite/binutils-all/wasm32/parse-wasm.d: Likewise. * testsuite/binutils-all/wasm32/parse-wasm.s: Likewise. * testsuite/binutils-all/wasm32/parse-wasm-2.d: Likewise. * testsuite/binutils-all/wasm32/parse-wasm-2.s: Likewise. * testsuite/binutils-all/wasm32/prepared-section.d: Likewise. * testsuite/binutils-all/wasm32/prepared-section.s: Likewise. * testsuite/binutils-all/wasm32/wasm32.exp: New file, run tests. gas * config/tc-wasm32.h: New file: Add WebAssembly assembler target. * config/tc-wasm32.c: New file: Add WebAssembly assembler target. * Makefile.am: Add WebAssembly assembler target. * configure.tgt: Add WebAssembly assembler target. * doc/c-wasm32.texi: New file: Start documenting WebAssembly assembler. * doc/all.texi: Define WASM32. * doc/as.texinfo: Add WebAssembly entries. * NEWS: Mention the new support. * Makefile.in: Regenerate. * po/gas.pot: Regenerate. * po/POTFILES.in: Regenerate. * testsuite/gas/wasm32: New directory. * testsuite/gas/wasm32/allinsn.d: New file. * testsuite/gas/wasm32/allinsn.s: New file. * testsuite/gas/wasm32/illegal.l: New file. * testsuite/gas/wasm32/illegal.s: New file. * testsuite/gas/wasm32/illegal-2.l: New file. * testsuite/gas/wasm32/illegal-2.s: New file. * testsuite/gas/wasm32/illegal-3.l: New file. * testsuite/gas/wasm32/illegal-3.s: New file. * testsuite/gas/wasm32/illegal-4.l: New file. * testsuite/gas/wasm32/illegal-4.s: New file. * testsuite/gas/wasm32/illegal-5.l: New file. * testsuite/gas/wasm32/illegal-5.s: New file. * testsuite/gas/wasm32/illegal-6.l: New file. * testsuite/gas/wasm32/illegal-6.s: New file. * testsuite/gas/wasm32/illegal-7.l: New file. * testsuite/gas/wasm32/illegal-7.s: New file. * testsuite/gas/wasm32/illegal-8.l: New file. * testsuite/gas/wasm32/illegal-8.s: New file. * testsuite/gas/wasm32/illegal-9.l: New file. * testsuite/gas/wasm32/illegal-9.s: New file. * testsuite/gas/wasm32/illegal-10.l: New file. * testsuite/gas/wasm32/illegal-10.s: New file. * testsuite/gas/wasm32/illegal-11.l: New file. * testsuite/gas/wasm32/illegal-11.s: New file. * testsuite/gas/wasm32/illegal-12.l: New file. * testsuite/gas/wasm32/illegal-12.s: New file. * testsuite/gas/wasm32/illegal-13.l: New file. * testsuite/gas/wasm32/illegal-13.s: New file. * testsuite/gas/wasm32/illegal-14.l: New file. * testsuite/gas/wasm32/illegal-14.s: New file. * testsuite/gas/wasm32/illegal-15.l: New file. * testsuite/gas/wasm32/illegal-15.s: New file. * testsuite/gas/wasm32/illegal-16.l: New file. * testsuite/gas/wasm32/illegal-16.s: New file. * testsuite/gas/wasm32/illegal-17.l: New file. * testsuite/gas/wasm32/illegal-17.s: New file. * testsuite/gas/wasm32/illegal-18.l: New file. * testsuite/gas/wasm32/illegal-18.s: New file. * testsuite/gas/wasm32/illegal-19.l: New file. * testsuite/gas/wasm32/illegal-19.s: New file. * testsuite/gas/wasm32/illegal-20.l: New file. * testsuite/gas/wasm32/illegal-20.s: New file. * testsuite/gas/wasm32/illegal-21.l: New file. * testsuite/gas/wasm32/illegal-21.s: New file. * testsuite/gas/wasm32/illegal-22.l: New file. * testsuite/gas/wasm32/illegal-22.s: New file. * testsuite/gas/wasm32/illegal-24.l: New file. * testsuite/gas/wasm32/illegal-24.s: New file. * testsuite/gas/wasm32/illegal-25.l: New file. * testsuite/gas/wasm32/illegal-25.s: New file. * testsuite/gas/wasm32/reloc.d: New file. * testsuite/gas/wasm32/reloc.s: New file. * testsuite/gas/wasm32/wasm32.exp: New tests for WebAssembly architecture. opcodes * configure.ac: Add (empty) bfd_wasm32_arch target. * configure: Regenerate * po/opcodes.pot: Regenerate. include * opcode/wasm.h: New file to support wasm32 architecture. * elf/wasm32.h: Add R_WASM32_32 relocation. bfd * elf32-wasm32.c: Add relocation code, two relocs. * reloc.c: Add wasm32 relocations. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate. * bfd/po/bfd.pot: Regenerate. |
||
|
Alan Modra
|
52be03fd13 |
PowerPC -Mraw disassembly
This adds -Mraw for PowerPC objdump, a disassembler option to display the underlying machine instruction rather than aliases. For example, "rlwinm" always rather than "rotlwi" when the instruction is performing a simple rotate. binutils/ * doc/binutils.texi (objdump): Document PowerPC -M options. gas/ * config/tc-ppc.c (md_parse_option): Reject -mraw. include/ * opcode/ppc.h (PPC_OPCODE_RAW): Define. (PPC_OPCODE_*): Make them all unsigned long long constants. opcodes/ * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add "raw" option. (lookup_powerpc): Don't special case -1 dialect. Handle PPC_OPCODE_RAW. (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first lookup_powerpc call, pass it on second. |
||
|
Pip Cet
|
8fb740dd30 |
Add minimal support for WebAssembly backend to the BFD library.
include * elf/wasm32.h: New file to support wasm32 architecture.
bfd * cpu-wasm32.c: New file to support wasm32 architecture.
* elf32-wasm32.c: New file to support wasm32 architecture.
* Makefile.am: Add wasm32 architecture.
* archures.c: Likewise.
* config.bfd: Likewise.
* configure.ac: Likewise.
* targets.c: Likewise.
|
||
Rinat Zelig
|
c0c31e91ad |
Implement ARC NPS-400 Ultra Ip and Miscellaneous instructions.
opcodes * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
* arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR, F_NPS_M, F_NPS_CORE, F_NPS_ALL.
(insert_nps_misc_imm_offset): New function.
(extract_nps_misc imm_offset): New function.
(arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
(arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
include * opcode/arc.h (insn_class_t): Add ULTRAIP and MISC class.
gas * testsuite/gas/arc/nps400-12.s: New file.
* testsuite/gas/arc/nps400-12.d: New file.
|
||
|
Andreas Krebbel
|
2253c8f089 |
S/390: Remove vx2 facility flag
This patch removes the vx2 facility flag. It will not be used by GCC and was a misnomer anyway. Committed to mainline and 2.28 branch. include/ChangeLog: 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * opcode/s390.h (S390_INSTR_FLAG_VX2): Remove. (S390_INSTR_FLAG_FACILITY_MASK): Adjust value. gas/ChangeLog: 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config/tc-s390.c (s390_parse_cpu): Remove S390_INSTR_FLAG_VX2 from cpu_table. Remove vx2, and novx2 from cpu_flags. opcodes/ChangeLog: 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * s390-mkopc.c (main): Remove vx2 check. * s390-opc.txt: Remove vx2 instruction flags. |
||
|
Rinat Zelig
|
645d3342ba |
arc/nps400: Add cp16/cp32 instructions to opcodes library
Instructions for loading or storing 16/32B data from one address type to another. gas/ChangeLog * testsuite/gas/arc/nps400-11.s: New file. * testsuite/gas/arc/nps400-11.d: New file. include/ChangeLog * opcode/arc.h (insn_class_t): Add DMA class. opcodes/ChangeLog * arc-nps400-tbl.h: Add cp32/cp16 instructions format. * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET. (insert_nps_imm_offset): New function. (extract_nps_imm_offset): New function. (insert_nps_imm_entry): New function. (extract_nps_imm_entry): New function. |
||
Nick Clifton
|
a8be5506b6 |
Add support for a GNU BUILD note type to record the enum size.
include * elf/common.h (GNU_BUILD_ATTRIBUTE_SHORT_ENUM): New GNU BUILD note type. binutils * readelf.c (print_gnu_build_attribute_name): Add support for GNU_BUILD_ATTRIBUTE_SHORT_ENUM. |
||
|
H.J. Lu
|
c98763221a |
Add DW_OP_GNU_variable_value
Sync GCC dwarf.def change 2017-03-14 Jakub Jelinek <jakub@redhat.com> PR debug/77589 * dwarf2.def (DW_OP_GNU_variable_value): New opcode. |
||
|
Nick Clifton
|
c793cac124 |
Sync libiberty sources with GCC.
PR demangler/70909 PR demangler/67264 * cp-demangle.c: Fix endless recursion. Pass struct demangle_component as non const. (d_make_empty): Initialize variable. (d_print_comp_inner): Limit recursion. (d_print_comp): Decrement variable. * cp-demint.c (cplus_demangle_fill_component): Initialize variable. (cplus_demangle_fill_builtin_type): Likewise. (cplus_demangle_fill_operator): Likewise. * testsuite/demangle-expected: Add tests. |
||
|
Nick Clifton
|
f955cccff3 |
Rename R_AARCH64_TLSDESC_LD64_LO12_NC to R_AARCH64_TLSDESC_LD64_LO12 and R_AARCH64_TLSDESC_ADD_LO12_NC to R_AARCH64_TLSDESC_ADD_LO12.
PR binutils/21202 include * elf/aarch64.h (R_AARCH64_TLSDESC_LD64_LO12_NC): Rename to R_AARCH64_TLSDESC_LD64_LO12. (R_AARCH64_TLSDESC_ADD_LO12_NC): Rename to R_AARCH64_TLSDESC_ADD_LO12_NC. bfd * reloc.c (BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC): Rename to BFD_RELOC_AARCH64_TLSDESC_LD64_LO12. (BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC): Rename to BFD_RELOC_AARCH64_TLSDESC_ADD_LO12. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elfnn-aarch64.c (IS_AARCH64_TLS_RELAX_RELOC): Update reloc names. (IS_AARCH64_TLSDESC_RELOC): Likewise. (elfNN_aarch64_howto_table): Likewise. (aarch64_tls_transition_without_check): Likewise. (aarch64_reloc_got_type): Likewise. (elfNN_aarch64_final_link_relocate): Likewise. (elfNN_aarch64_tls_relax): Likewise. (elfNN_aarch64_relocate_section): Likewise. (elfNN_aarch64_gc_sweep_hook): Likewise. (elfNN_aarch64_check_relocs): Likewise. * elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Likewise. (_bfd_aarch64_elf_resolve_relocation): Likewise. gas * config/tc-aarch64.c (reloc_table): Rename BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC to BFD_RELOC_AARCH64_TLSDESC_LD64_LO12. Rname BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC to BFD_RELOC_AARCH64_TLSDESC_ADD_LO12. (md_apply_fix): Likewise. (aarch64_force_relocation): Likewise. * testsuite/gas/aarch64/tls.d: Update regexp. ld * testsuite/ld-aarch64/ifunc-5r-local.d: Update regexp. |
||
|
Nick Clifton
|
55e22ca83a |
Add basic recognition of new EM_ ELF machine numbers.
include * elf/common.h (EM_LANAI): New machine number. (EM_BPF): Likewise. (EM_WEBASSEMBLY): Likewise. Move low value, deprecated, numbers to their numerical equivalents. binutils * readelf.c (get_machine_name): Rearrange switch table in order of increasing machine number. Add missing entries. |
||
|
H.J. Lu
|
1fc87489b4 |
Properly dump NT_GNU_PROPERTY_TYPE_0
Property type and datasz are always 4 bytes for both 32-bit and 64-bit objects. Property values for GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_ISA_1_NEEDED are 4 bytes for both i386 and x86-64 objects. We should also check GNU_PROPERTY_LOPROC and GNU_PROPERTY_LOUSER. binutils/ PR binutils/21231 * readelf.c (decode_x86_isa): Change argument to unsigned int. (print_gnu_property_note): Retrieve property type and datasz as 4-byte integer. Consolidate property datasz check. Check GNU_PROPERTY_LOPROC and GNU_PROPERTY_LOUSER. * testsuite/binutils-all/i386/pr21231a.d: New file. * testsuite/binutils-all/i386/pr21231a.s: Likewise. * testsuite/binutils-all/i386/pr21231b.d: Likewise. * testsuite/binutils-all/i386/pr21231b.s: Likewise. * testsuite/binutils-all/x86-64/pr21231a.d: Likewise. * testsuite/binutils-all/x86-64/pr21231a.s: Likewise. * testsuite/binutils-all/x86-64/pr21231b.d: Likewise. * testsuite/binutils-all/x86-64/pr21231b.s: Likewise. include/ PR binutils/21231 * elf/common.h (GNU_PROPERTY_LOPROC): New. (GNU_PROPERTY_HIPROC): Likewise. (GNU_PROPERTY_LOUSER): Likewise. (GNU_PROPERTY_HIUSER): Likewise. |
||
|
Nick Clifton
|
9ef920e933 |
Add support for displaying and merging GNU_BUILD_NOTEs.
include * elf/common.h (SHF_GNU_BUILD_NOTE): Define. (NT_GNU_PROPERTY_TYPE_0): Define. (NT_GNU_BUILD_ATTRIBUTE_OPEN): Define. (NT_GNU_BUILD_ATTRIBUTE_FUN): Define. (GNU_BUILD_ATTRIBUTE_TYPE_NUMERIC): Define. (GNU_BUILD_ATTRIBUTE_TYPE_STRING): Define. (GNU_BUILD_ATTRIBUTE_TYPE_BOOL_TRUE): Define. (GNU_BUILD_ATTRIBUTE_TYPE_BOOL_FALSE): Define. (GNU_BUILD_ATTRIBUTE_VERSION): Define. (GNU_BUILD_ATTRIBUTE_STACK_PROT): Define. (GNU_BUILD_ATTRIBUTE_RELRO): Define. (GNU_BUILD_ATTRIBUTE_STACK_SIZE): Define. (GNU_BUILD_ATTRIBUTE_TOOL): Define. (GNU_BUILD_ATTRIBUTE_ABI): Define. (GNU_BUILD_ATTRIBUTE_PIC): Define. (NOTE_GNU_PROPERTY_SECTION_NAME): Define. (GNU_BUILD_ATTRS_SECTION_NAME): Define. (GNU_PROPERTY_STACK_SIZE): Define. (GNU_PROPERTY_NO_COPY_ON_PROTECTED): Define. (GNU_PROPERTY_X86_ISA_1_USED): Define. (GNU_PROPERTY_X86_ISA_1_NEEDED): Define. (GNU_PROPERTY_X86_ISA_1_486): Define. (GNU_PROPERTY_X86_ISA_1_586): Define. (GNU_PROPERTY_X86_ISA_1_686): Define. (GNU_PROPERTY_X86_ISA_1_SSE): Define. (GNU_PROPERTY_X86_ISA_1_SSE2): Define. (GNU_PROPERTY_X86_ISA_1_SSE3): Define. (GNU_PROPERTY_X86_ISA_1_SSSE3): Define. (GNU_PROPERTY_X86_ISA_1_SSE4_1): Define. (GNU_PROPERTY_X86_ISA_1_SSE4_2): Define. (GNU_PROPERTY_X86_ISA_1_AVX): Define. (GNU_PROPERTY_X86_ISA_1_AVX2): Define. (GNU_PROPERTY_X86_ISA_1_AVX512F): Define. (GNU_PROPERTY_X86_ISA_1_AVX512CD): Define. (GNU_PROPERTY_X86_ISA_1_AVX512ER): Define. (GNU_PROPERTY_X86_ISA_1_AVX512PF): Define. (GNU_PROPERTY_X86_ISA_1_AVX512VL): Define. (GNU_PROPERTY_X86_ISA_1_AVX512DQ): Define. (GNU_PROPERTY_X86_ISA_1_AVX512BW): Define. binutils* readelf.c (get_note_type): Add support for GNU_BUILD_NOTEs. (get_gnu_elf_note_type): Add support for GNU_PROPERTY_NOTEs. (decode_x86_isa): New function. (print_gnu_property_note): New function. (print_gnu_note): Handle GNU_PROPERTY_NOTEs. (print_gnu_build_attribute_description): New function. (print_gnu_build_attribute_name): New function. (process_note): Add support for GNU_BUILD_NOTEs. * objcopy.c (--merge-notes): New command line option. (copy_options): Add merge-notes. (copy_usage): Likewise. (is_merge_note_section): New function. (merge_gnu_build_notes): New function. (copy_object): Merge note sections if asked to do so. (skip_section): Add skip_copy parameter. Add support for skipping merged note sections. (copy_relocations_in_section): Update call to skip_section. (copy_section): Likewise. (copy_main): Add support for merge-notes option. * doc/binutils.texi: Document the new option to objcopy. * NEWS: Mention the new feature. * testsuite/binutils-all/note-2-32.d: New test. Checks note merging on 32-bit targets. * testsuite/binutils-all/note-2-32.s: New test source file. * testsuite/binutils-all/note-2-64.d: New test. Like note-2-32.d but for 64-bit targets. * testsuite/binutils-all/note-2-64.s: New test source file. * testsuite/binutils-all/objcopy.exp: Run the new test. |
||
Peter Bergner
|
65b48a8140 |
GDB: Add support for the new set/show disassembler-options commands.
This commit adds support to GDB so that it can modify the disassembler-options value that is passed to the disassembler, similar to objdump's -M option. Currently, the only supported targets are ARM, PowerPC and S/390, but adding support for a new target(s) is not difficult. include/ * dis-asm.h (disasm_options_t): New typedef. (parse_arm_disassembler_option): Remove prototype. (set_arm_regname_option): Likewise. (get_arm_regnames): Likewise. (get_arm_regname_num_options): Likewise. (disassemble_init_s390): New prototype. (disassembler_options_powerpc): Likewise. (disassembler_options_arm): Likewise. (disassembler_options_s390): Likewise. (remove_whitespace_and_extra_commas): Likewise. (disassembler_options_cmp): Likewise. (next_disassembler_option): New inline function. (FOR_EACH_DISASSEMBLER_OPTION): New macro. opcodes/ * disassemble.c Include "safe-ctype.h". (disassemble_init_for_target): Handle s390 init. (remove_whitespace_and_extra_commas): New function. (disassembler_options_cmp): Likewise. * arm-dis.c: Include "libiberty.h". (NUM_ELEM): Delete. (regnames): Use long disassembler style names. Add force-thumb and no-force-thumb options. (NUM_ARM_REGNAMES): Rename from this... (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE. (get_arm_regname_num_options): Delete. (set_arm_regname_option): Likewise. (get_arm_regnames): Likewise. (parse_disassembler_options): Likewise. (parse_arm_disassembler_option): Rename from this... (parse_arm_disassembler_options): ...to this. Make static. Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options. (print_insn): Use parse_arm_disassembler_options. (disassembler_options_arm): New function. (print_arm_disassembler_options): Handle updated regnames. * ppc-dis.c: Include "libiberty.h". (ppc_opts): Add "32" and "64" entries. (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp. (powerpc_init_dialect): Add break to switch statement. Use new FOR_EACH_DISASSEMBLER_OPTION macro. (disassembler_options_powerpc): New function. (print_ppc_disassembler_options): Use ARRAY_SIZE. Remove printing of "32" and "64". * s390-dis.c: Include "libiberty.h". (init_flag): Remove unneeded variable. (struct s390_options_t): New structure type. (options): New structure. (init_disasm): Rename from this... (disassemble_init_s390): ...to this. Add initializations for current_arch_mask and option_use_insn_len_bits_p. Remove init_flag. (print_insn_s390): Delete call to init_disasm. (disassembler_options_s390): New function. (print_s390_disassembler_options): Print using information from struct 'options'. * po/opcodes.pot: Regenerate. binutils/ * objdump.c (main): Use remove_whitespace_and_extra_commas. gdb/ * NEWS: Mention new set/show disassembler-options commands. * doc/gdb.texinfo: Document new set/show disassembler-options commands. * disasm.c: Include "arch-utils.h", "gdbcmd.h" and "safe-ctype.h". (prospective_options): New static variable. (gdb_disassembler::gdb_disassembler): Initialize m_di.disassembler_options. (gdb_buffered_insn_length_init_dis): Initilize di->disassembler_options. (get_disassembler_options): New function. (set_disassembler_options): Likewise. (set_disassembler_options_sfunc): Likewise. (show_disassembler_options_sfunc): Likewise. (disassembler_options_completer): Likewise. (_initialize_disasm): Likewise. * disasm.h (get_disassembler_options): New prototype. (set_disassembler_options): Likewise. * gdbarch.sh (gdbarch_disassembler_options): New variable. (gdbarch_verify_disassembler_options): Likewise. * gdbarch.c: Regenerate. * gdbarch.h: Likewise. * arm-tdep.c (num_disassembly_options): Delete. (set_disassembly_style): Likewise. (arm_disassembler_options): New static variable. (set_disassembly_style_sfunc): Convert short style name into long option name. Call set_disassembler_options. (show_disassembly_style_sfunc): New function. (arm_gdbarch_init): Call set_gdbarch_disassembler_options and set_gdbarch_verify_disassembler_options. (_initialize_arm_tdep): Delete regnames variable and update callers. (arm_disassembler_options): Initialize. (disasm_options): New variable. (num_disassembly_options): Rename from this... (num_disassembly_styles): ...to this. Compute by scanning through disasm_options. (valid_disassembly_styles): Initialize using disasm_options. Remove calls to parse_arm_disassembler_option, get_arm_regnames and set_arm_regname_option. Pass show_disassembly_style_sfunc to the "disassembler" setshow command. * rs6000-tdep.c (powerpc_disassembler_options): New static variable. (rs6000_gdbarch_init): Call set_gdbarch_disassembler_options and set_gdbarch_verify_disassembler_options. * s390-tdep.c (s390_disassembler_options): New static variable. (s390_gdbarch_init):all set_gdbarch_disassembler_options and set_gdbarch_verify_disassembler_options. gdb/testsuite/ * gdb.arch/powerpc-power.exp: Delete test. * gdb.arch/powerpc-power.s: Likewise. * gdb.disasm/disassembler-options.exp: New test. * gdb.arch/powerpc-altivec.exp: Likewise. * gdb.arch/powerpc-altivec.s: Likewise. * gdb.arch/powerpc-altivec2.exp: Likewise. * gdb.arch/powerpc-altivec2.s: Likewise. * gdb.arch/powerpc-altivec3.exp: Likewise. * gdb.arch/powerpc-altivec3.s: Likewise. * gdb.arch/powerpc-power7.exp: Likewise. * gdb.arch/powerpc-power7.s: Likewise. * gdb.arch/powerpc-power8.exp: Likewise. * gdb.arch/powerpc-power8.s: Likewise. * gdb.arch/powerpc-power9.exp: Likewise. * gdb.arch/powerpc-power9.s: Likewise. * gdb.arch/powerpc-vsx.exp: Likewise. * gdb.arch/powerpc-vsx.s: Likewise. * gdb.arch/powerpc-vsx2.exp: Likewise. * gdb.arch/powerpc-vsx2.s: Likewise. * gdb.arch/powerpc-vsx3.exp: Likewise. * gdb.arch/powerpc-vsx3.s: Likewise. * gdb.arch/arm-disassembler-options.exp: Likewise. * gdb.arch/powerpc-disassembler-options.exp: Likewise. * gdb.arch/s390-disassembler-options.exp: Likewise. |
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Alan Modra
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7ba71655a4 |
PowerPC addpcis fix
This came up because I was looking at ld/tmpdir/addpcis.o and noticed the odd addends on REL16DX_HA. They ought to both be -4. The error crept in due REL16DX_HA howto being pc-relative (as indeed it should be), and code at gas/write.c:1001 after this comment /* Make it pc-relative. If the back-end code has not selected a pc-relative reloc, cancel the adjustment we do later on all pc-relative relocs. */ *not* cancelling the pc-relative adjustment. So I've made a dummy non-relative split reloc so that the generic code handles this, rather than attempting to add hacks later in md_apply_fix which would not be very robust. Having the new internal reloc also makes it easy to support addpcis rx,sym@ha as an equivalent to addpcis rx,(sym-0f)@ha 0: The patch also fixes overflow checking, which must test whether the addi will overflow too since @l relocs don't have any overflow check. Lastly, since I was poking at md_apply_fix, I arranged to have the generic gas/write.c code emit errors for subtraction expressions where we lack reloc support. include/ * elf/ppc64.h (R_PPC64_16DX_HA): New. Expand fake reloc comment. * elf/ppc.h (R_PPC_16DX_HA): Likewise. bfd/ * reloc.c (BFD_RELOC_PPC_16DX_HA): New. * elf64-ppc.c (ppc64_elf_howto_raw <R_PPC64_16DX_HA>): New howto. (ppc64_elf_reloc_type_lookup): Translate new bfd reloc. (ppc64_elf_ha_reloc): Correct overflow test on REL16DX_HA. (ppc64_elf_relocate_section): Likewise. * elf32-ppc.c (ppc_elf_howto_raw <R_PPC_16DX_HA>): New howto. (ppc_elf_reloc_type_lookup): Translate new bfd reloc. (ppc_elf_check_relocs): Handle R_PPC_16DX_HA to pacify gcc. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate. gas/ * config/tc-ppc.c (md_assemble): Use BFD_RELOC_PPC_16DX_HA for addpcis. (md_apply_fix): Remove fx_subsy check. Move code converting to pcrel reloc earlier and handle BFD_RELOC_PPC_16DX_HA. Remove code emiiting errors on seeing fx_pcrel set on unexpected relocs, as that is done now by the generic code via.. * config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): ..this. Define. (TC_VALIDATE_FIX_SUB): Define. ld/ * testsuite/ld-powerpc/addpcis.d: Define ext1 and ext2 at limits of addpcis range. |
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Richard Sandiford
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582e12bf76 |
[AArch64] Additional SVE instructions
This patch supports some additions to the SVE architecture prior to
its public release.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16)
(AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2)
(AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX)
(AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
(OP_SVE_V_HSD): New macros.
(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
(aarch64_opcode_table): Add new SVE instructions.
(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
for rotation operands. Add new SVE operands.
* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
(ins_sve_quad_index): Likewise.
(ins_imm_rotate): Split into...
(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
functions.
(aarch64_ins_sve_addr_ri_s4): New function.
(aarch64_ins_sve_quad_index): Likewise.
(do_misc_encoding): Handle "MOV Zn.Q, Qm".
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
(ext_sve_quad_index): Likewise.
(ext_imm_rotate): Split into...
(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
functions.
(aarch64_ext_sve_addr_ri_s4): New function.
(aarch64_ext_sve_quad_index): Likewise.
(aarch64_ext_sve_index): Allow quad indices.
(do_misc_decoding): Likewise.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
aarch64_field_kinds.
(OPD_F_OD_MASK): Widen by one bit.
(OPD_F_NO_ZR): Bump accordingly.
(get_operand_field_width): New function.
* aarch64-opc.c (fields): Add new SVE fields.
(operand_general_constraint_met_p): Handle new SVE operands.
(aarch64_print_operand): Likewise.
* aarch64-opc-2.c: Regenerate.
gas/
* doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum.
* config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q
to be used with SVE registers.
(parse_operands): Handle new SVE operands.
(aarch64_features): Make "sve" require F16 rather than FP. Also
require COMPNUM.
* testsuite/gas/aarch64/sve.s: Add tests for new instructions.
Include compnum tests.
* testsuite/gas/aarch64/sve.d: Update accordingly.
* testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions.
* testsuite/gas/aarch64/sve-invalid.l: Update accordingly. Also
update expected output for new FMOV and MOV alternatives.
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Richard Sandiford
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f482d30447 |
[AArch64] Add a "compnum" feature
This patch adds a named "compnum" feature for the ARMv8.3-A FCADD and FCMLA extensions. include/ * opcode/aarch64.h (AARCH64_FEATURE_COMPNUM): New macro. (AARCH64_ARCH_V8_3): Include AARCH64_FEATURE_COMPNUM. opcodes/ * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with... (aarch64_feature_compnum): ...this. (SIMD_V8_3): Replace with... (COMPNUM): ...this. (CNUM_INSN): New macro. (aarch64_opcode_table): Use it for the complex number instructions. gas/ * doc/c-aarch64.texi: Add a "compnum" entry. * config/tc-aarch64.c (aarch64_features): Likewise, * testsuite/gas/aarch64/advsimd-compnum.s: New test. * testsuite/gas/aarch64/advsimd-compnum.d: Likewise. |
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Andrew Waterman
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742d14b39b |
Add new counter-enable CSRs
include/ChangeLog:
2017-02-22 Andrew Waterman <andrew@sifive.com>
* opcode/riscv-opc.h (CSR_SCOUNTEREN): New define.
(CSR_MCOUNTEREN): Likewise.
(scounteren): Declare register.
(mcounteren): Likewise.
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Andreas Krebbel
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64025b4ec9 |
S/390: Add support for new cpu architecture - arch12.
This adds support of new instructions to the S/390 specific parts. The important feature of the new instruction set is the support of single and extended precision floating point vector operations. Note: arch12 is NOT the official name of the new CPU. It just continues the series of archXX options supported as alternate names. The archXX terminology refers to the edition number of the Principle of Operations manual. The official CPU name will be added later while keeping support of the arch12 for backwards compatibility. No testsuite regressions. Committed to mainline. Bye, -Andreas- opcodes/ChangeLog: 2017-02-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * s390-mkopc.c (main): Accept arch12 as cpu string and vx2 as facility. * s390-opc.c: Add new operand description macros, new instruction types, instruction masks, and new .insn instruction types. * s390-opc.txt: Add new arch12 instructions. include/ChangeLog: 2017-02-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * opcode/s390.h (enum s390_opcode_cpu_val): New value S390_OPCODE_ARCH12. (S390_INSTR_FLAG_VX2): New macro definition. gas/ChangeLog: 2017-02-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config/tc-s390.c (s390_parse_cpu): New entry for arch12. * doc/as.texinfo: Document arch12 as cpu type. * doc/c-s390.texi: Likewise. * testsuite/gas/s390/s390.exp: Run arch12 specific tests. * testsuite/gas/s390/zarch-arch12.d: New test. * testsuite/gas/s390/zarch-arch12.s: New test. * testsuite/gas/s390/zarch-z13.d: Rename some mnemonics in the output patterns. |
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Sheldon Lobo
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1e9d41d49f |
opcodes,gas: associate SPARC ASIs with an architecture level.
With this change an architecture level bump due to assembly ASIs will show up as a warning/error depending on options passed to gas. Tested with sparc64-linux-gnu, and it does not introduce any regressions. gas/ChangeLog: Add support for associating SPARC ASIs with an architecture level. * config/tc-sparc.c (parse_sparc_asi): New encode SPARC ASIs. opcodes/ChangeLog: Add support for associating SPARC ASIs with an architecture level. * include/opcode/sparc.h (sparc_asi): New sparc_asi struct. * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/ decoding of SPARC ASIs. |
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Andrew Waterman
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f98d33be3a |
Add SFENCE.VMA instruction
include/ChangeLog:
2017-02-14 Andrew Waterman <andrew@sifive.com>
* opcode/riscv-opc.h (MATCH_SFENCE_VMA): New define.
(MASK_SFENCE_VMA): Likewise.
(sfence_vma): Declare instruction.
opcodes/ChangeLog:
2017-02-14 Andrew Waterman <andrew@sifive.com>
* riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
pseudoinstructions.
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