xrefautomaticsectiontitle appears to be available from texinfo 5.0 or
greater. As such, it is not worthwhile to add requirement for a minimum
necessary makeinfo version. So remove the usage of it.
Also align node name with section title where possible.
ChangeLog:
* libsframe/doc/sframe-spec.texi: Remove usage of
xrefautomaticsectiontitle.
Move all the remaining tests to a single test_break proc. It's a bit
big, but all of these are kind of tied together. The procs starts by
setting breakpoints, checks that we can see them in "info breakpoints",
and tries stopping on them.
Move all the "set bp_locationX" calls together at the top.
Change-Id: Id05f98957e1a3462532d2dbd577cd0a7c7263900
Approved-By: Kevin Buettner <kevinb@redhat.com>
Leave setting bp_location11 in the global scope, so that it's accessible
to other procs.
Change-Id: I8928f01640d3a1e993649b2168b9eda0724ee1d9
Approved-By: Kevin Buettner <kevinb@redhat.com>
One special thing here is that the part just above this one, that sets
catchpoints and verifies they are not hit, requires that we resume
execution to verify that the catchpoints are indeed not hit. I guess
it was previously achieved by the until command, but it doesn't happen
now that the until is moved into test_break_default. Add a
gdb_continue_to_end after setting the catchpoints. If any catchpoint
were to be hit, it would catch the problem.
Change-Id: I5d4b43da91886b1beda9f6e56b05aa04331a9c05
Approved-By: Kevin Buettner <kevinb@redhat.com>
This one is a bit tricky. The clear tests seem to depend on the various
breakpoints that have been set before, starting with the "silent"
breakpoints. So, move all this in a single chunk, it can always be
split later if needed.
Change-Id: I7ba61a5b130ade63eda0c4790534840339f8a72f
Approved-By: Kevin Buettner <kevinb@redhat.com>
This one is already in a proc, just make the proc use proc_with_prefix,
for consistency.
Change-Id: I313ecf5097ff04526c29396529baeba84e37df5a
Approved-By: Kevin Buettner <kevinb@redhat.com>
First of all make operand_type_register_match() apply to all sized
operands, i.e. in Intel Syntax also to respective memory ones. This
addresses gas wrongly accepting certain SIMD insns where register and
memory operand sizes should match but don't. This apparently has
affected all templates with one memory-only operand and one or more
register ones, both permitting at least two sizes, due to CheckRegSize
not taking effect.
Then also add CheckRegSize to a couple of non-SIMD templates matching
that same pattern of memory-only vs register operands. This replaces
bogus (for Intel Syntax) diagnostics referring to a wrong suffix (when
none was used at all) by "type mismatch" ones, just like already emitted
for insns where the template allows a register operand alongside a
memory one at any particular position.
This also is a prereq to limiting (ideally eliminating in the long run)
suffix "derivation" in Intel Syntax mode.
While making the code adjustment also flip order of checks to do the
cheaper one first in both cases.
To properly and predictably determine operand size encoding (operand
size or REX.W prefixes), consistent operand sizes need to be specified.
Add CheckRegSize where this was previously missing.
Both uniformly only ever take 16-bit memory operands while at the same
time requiring matching (in size) register operands, which then also
should disassemble that way. This in particular requires splitting each
of the templates for the assembler and separating decode of the
register and memory forms in the disassembler.
Mode/reg bits for these insns are 000 Dy, 001 Ay, and 111 100 for the
move immediate.
* m68k-opc.c (m68k_opcodes): Only accept 000 and 001 as mode
for move reg to macsr/mask insns.
For v8m, the EXC_RETURN pattern, without security extension, consists of
FType, Mode and SPSEL. These are the same bits that are used in v7m.
This patch extends the list of patterns to include also the FType bit
and not just Mode and SPSEL bits for v8m targets without security
extension.
Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
This extends the commit 4581a1c7d3 fix to more targets, which
hardens BFD a little. I think the real underlying problem was the
bfd_canonicalize_reloc call in load_specific_debug_section which
passed a NULL for "symbols". Fix that too.
PR 22509
bfd/
* aoutx.h (swap_ext_reloc_out): Gracefully handle NULL symbols.
* i386lynx.c (swap_ext_reloc_out): Likewise.
* pdp11.c (pdp11_aout_swap_reloc_out): Likewise.
* coff-tic30.c (reloc_processing): Likewise.
* coff-tic4x.c (tic4x_reloc_processing): Likewise.
* coff-tic54x.c (tic54x_reloc_processing): Likewise.
* coff-z80.c (reloc_processing): Likewise.
* coff-z8k.c (reloc_processing): Likewise.
* ecoff.c (ecoff_slurp_reloc_table): Likewise.
* som.c (som_set_reloc_info): Likewise.
binutils/
* objdump.c (load_specific_debug_section): Pass syms to
bfd_canonicalize_reloc.
If tdata->symbols is NULL, make tdata->symcount zero too. This makes
wasm_get_symtab_upper_bound return the proper result and stops
cascading errors.
* wasm-module.c (wasm_scan_name_function_section): Clear
tdata->symcount on error.
On powerpc64le-linux I ran into this FAIL:
...
(gdb) p exceptions.throw_function()^M
terminate called after throwing an instance of 'int'^M
^M
Program received signal SIGABRT, Aborted.^M
0x00007ffff7979838 in raise () from /lib64/libc.so.6^M
The program being debugged was signaled while in a function called from GDB.^M
GDB remains in the frame where the signal was received.^M
To change this behavior use "set unwindonsignal on".^M
Evaluation of the expression containing the function^M
(SimpleException::throw_function()) will be abandoned.^M
When the function is done executing, GDB will silently stop.^M
(gdb) FAIL: gdb.cp/gdb2495.exp: call a function that raises an exception \
without a handler.
...
The following happens:
- we start an inferior call
- an internal breakpoint is set on the global entry point of std::terminate
- the inferior call uses the local entry point
- the breakpoint is not triggered
- we run into std::terminate
We can fix this by simply adding the missing gdbarch_skip_entrypoint call in
create_std_terminate_master_breakpoint, but we try to do this a bit more
generic, by:
- adding a variant of function create_internal_breakpoint which takes a
minimal symbol instead of an address as argument
- in the new function:
- using both gdbarch_convert_from_func_ptr_addr and gdbarch_skip_entrypoint
- documenting why we don't need to use gdbarch_addr_bits_remove
- adding a note about possibly
needing gdbarch_deprecated_function_start_offset.
- using the new function in:
- create_std_terminate_master_breakpoint
- create_exception_master_breakpoint_hook, which currently uses only
gdbarch_convert_from_func_ptr_addr.
Note: we could use the new function in more locations in breakpoint.c, but
as we're not aware of any related failures, we declare this out of scope for
this patch.
Tested on x86_64-linux, powerpc64le-linux.
Co-Authored-By: Ulrich Weigand <uweigand@de.ibm.com>
Tested-by: Carl Love <cel@us.ibm.com>
PR tdep/29793
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=29793
According to the riscv psabi, R_RISCV_SUB6 only allows 6 least significant
bits are valid, but since binutils implementation, we usually get 8 bits
field for it. That means, the high 2 bits could be other field and have
different purpose. Therefore, we should filter the 8 bits to 6 bits before
calculate, and then only encode the valid 6 bits back. By the way, we also
need the out-of-range check for R_RISCV_SUB6, and the overflow checks for
all R_RISCV_ADD/SUB/SET relocations, but we can add them in the future patches.
Passing riscv-gnu-toolchain regressions.
bfd/ChangeLog:
* elfnn-riscv.c (riscv_elf_relocate_section): Take the R_RISCV_SUB6
lower 6 bits as the significant bit.
* elfxx-riscv.c (riscv_elf_add_sub_reloc): Likewise.
This uses custom collect/supply regset handlers which pass the TLS
register number from the gdbarch_tdep as the base register number.
Approved-By: Simon Marchi <simon.marchi@efficios.com>
This uses custom collect/supply regset handlers which pass the TLS
register number from the gdbarch_tdep as the base register number.
Approved-By: Simon Marchi <simon.marchi@efficios.com>
This is needed to permit using the helpers for register sets with a
variable base. In particular regnum needs to be converted into a
relative register number before passed to regcache_map_supplies.
Approved-By: Simon Marchi <simon.marchi@efficios.com>
fbsd-nat includes various helper routines for fetching and storing
register sets via ptrace where the register set is described by a
regset. These helper routines directly invoke the
supply/collect_regset regcache methods which doesn't permit a regset
to provide custom logic when fetching or storing a register set.
Instead, just use the function pointers from the struct regset
directly.
Approved-By: Simon Marchi <simon.marchi@efficios.com>
Some register sets described by an array of regcache_map_entry
structures do not have fixed register numbers in their associated
architecture but do describe a block of registers whose numbers are at
fixed offsets relative to some base register value. An example of
this are the TLS register sets for the ARM and AArch64 architectures.
Currently OS-specific architectures create register maps and register
sets dynamically using the register base number. However, this
requires duplicating the code to create the register map and register
set. To reduce duplication, add variants of the collect_regset and
supply_regset regcache methods which accept a base register number.
For valid register map entries (i.e. not REGCACHE_MAP_SKIP), add this
base register number to the value from the map entry to determine the
final register number.
Approved-By: Simon Marchi <simon.marchi@efficios.com>
The aim here is to improve readelf handling of large 64-bit object
files on LLP64 hosts (Windows) where long is only 32 bits. The patch
changes more than just file offsets. Addresses and sizes are also
changed to avoid "long". Most places get to use uint64_t even where
size_t may be more appropriate, because that allows some overflow
checks to be implemented easily (*alloc changes).
* dwarf.c (cmalloc, xcmalloc, xcrealloc, xcalloc2): Make nmemb
parameter uint64_t.
* dwarf.h: Update prototypes.
(struct dwarf_section): Make num_relocs uint64_t.
* elfcomm.c (setup_archive): Update error format.
* elfcomm.h (struct archive_info): Make sym_size, longnames_size,
nested_member_origin, next_arhdr_offset uint64_t.
* readelf.c (struct filedata): Make archive_file_offset,
archive_file_size, string_table_length, dynamic_addr,
dynamic_nent, dynamic_strings_length, num_dynamic_syms,
dynamic_syminfo_offset uint64_t.
(many functions): Replace uses of "unsigned long" with
"uint64_t" or "size_t".
Replace the macros with a small wrapper function that verifies the fseek
offset arg isn't overlarge.
* readelf.c (FSEEK_FUNC): Delete, replace uses with..
(fseek64): ..this new function.
(process_program_headers): Don't cast p_offset to long.
As part of the rebase of the patch, I managed to loose the local
changes I had for the comments from Tomas in
https://sourceware.org/pipermail/gdb-patches/2022-November/193413.html
This patch corrects the obvious two typos.
Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
Integrate back checks for fseeko{,64} into configure.ac, so
that regeneration works.
binutils/
* configure.ac: Add fseeko, fseeko64 checks.
* configure: Regenerate.
This patch changes the address for "isa_config" auxiliary register
from 0xC2 to the correct value 0xC1. Moreover, it only exists in
arc700+ and not all ARCs.
opcodes/ChangeLog:
* arc-regs.h: Change isa_config address to 0xc1.
isa_config exists for ARC700 and ARCV2 and not ARCALL.
With the recent changes to the dwarf assembler, there is no longer a
need to test for gcc in gdb.dwarf2/clang-cli-macro.exp and mark it as
untested. This commit removes that logic.
Once again: Old enough glibc has an (unguarded) declaration of index()
in string.h, which triggers a "shadows a global declaration" warning
with our choice of wanring level and with at least some gcc versions.
