The destination registers with vector add/sub insns must be different,
so make sure gas rejects attempt to write these.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
If the MAC1 part of the insn is disabled, then the (M) flag is ignored.
Rather than include it in the decode, move the MM clearing to the MAC0
portion of the code.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The current 16bit insn test doesn't actually cover all illegal insns
since it stops at 0xa000 instead of 0xc000. But rather than address
that, replace it with a test that covers all 16bit insns.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
While we were catching a few mismatches in vectorized dsp mult insns,
the error we displayed was misleading. Once we fix that up, we can
convert previously dead code into proper checking for destination
dreg matching.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The destination registers for SEARCH cannot be the same. Same rule
for the source registers for BITMUX.
Signed-off-by: Mike Frsyinger <vapier@gentoo.org>
When I originally wrote the w1c helper funcs, I used it in a few places.
Then I forgot how it worked and when I later documented it, I described
the 3rd arg in the exact opposite way it is actually used. This error
propagated to a bunch of devices registers that were not explicitly
tested (a bunch of the devices are stubs which merely exist to say "no
device is connected" to make device drivers happy).
So once the documentation is unscrewed, fix all of the broken call sites.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
We'll need these bits in an upcoming patch, so map out the whole
LSR MMR now.
Fix up indentation style while we're here.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The Blackfin PRM says that the top 8 bits of the accumulator must be
cleared when using the VIT_MAX insn, so the sim has followed this spec.
Matching the hardware behavior though when the high bits are not cleared
is easy to do and doesn't break existing behavior, so go for it.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The Blackfin PRM does not cover this case, but the hardware is clear: even
if the search criteria is not met (and thus a new 16bit value is loaded up
into the accumulator), the accumulator undergoes 16bit sign extension. So
simply reload the low signed 16bits in that case.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The Acc=-Acc insn can overflow or carry with edge values, so make sure
we update the ASTAT bits accordingly to match the hardware. Also fix
a thinko where we always updated AC0 even when working with A1 regs.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
When encoding the SIC/pin info into unique input port ids, I used bases
of 100 when I meant to use 0x100. Rather than simply fix the decoding
math in the different functions, create a few helper macros to simplify
the SIC/pin encoding and decoding steps. This makes the resulting tables
nice & clear.
And now that pins are clear, the 533 and 537 port_event handlers may
easily be merged into one.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The hardware allows the byteop[123]p insns to use the same src reg pair,
so remove the combination check in the sim.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The bus addresses have to be valid numbers, so 'g' and 'h' won't work.
Oddly, the common code silently ignored this which is why I didn't notice
in the first place.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
* archures.c: Add AVR XMEGA architecture information.
* cpu-avr.c (arch_info_struct): Likewise.
* elf32-avr.c (bfd_elf_avr_final_write_processing): Likewise.
(elf32_avr_object_p): Likewise.
/gas:
2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
* config/tc-avr.c (struct avr_opcodes_s): Add opcode field.
(AVR_INSN): Change definition to match.
(avr_opcodes): Likewise, change to match.
(mcu_types): Add XMEGA architecture names and new XMEGA device names.
(md_show_usage): Add XMEGA architecture names.
(avr_operand): Add 'E' constraint for DES instruction of XMEGA devices.
Add support for SPM Z+ instruction.
* doc/c-avr.texi: Add documentation for XMEGA architectures and
devices.
/include/opcode:
2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
* avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
New instruction set flags.
(AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
/ld:
2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
* Makefile.am (ALL_EMULATION_SOURCES): Add AVR XMEGA architectures.
(eavrxmega?.c): Likewise.
* configure.tgt (targ_extra_emuls): Likewise.
* emulparams/avrxmega1.sh: New file.
* emulparams/avrxmega2.sh: Likewise.
* emulparams/avrxmega3.sh: Likewise.
* emulparams/avrxmega4.sh: Likewise.
* emulparams/avrxmega5.sh: Likewise.
* emulparams/avrxmega6.sh: Likewise.
* emulparams/avrxmega7.sh: Likewise.
* emultempl/avrelf.em (avr_elf_${EMULATION_NAME}_before_allocation):
Add avrxmega6, avrxmega7 to list of architectures for no stubs.
/opcodes:
2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
* avr-dis.c (avr_operand): Add opcode_str parameter. Check for
post-increment to support LPM Z+ instruction. Add support for 'E'
constraint for DES instruction.
(print_insn_avr): Adjust calls to avr_operand. Rename variable.
Code cleanup.
* c-typeprint.c (c_type_print_args): Change parameter show_artificial
to linkage_name. Invert its value. Update the function comment.
(c_type_print_varspec_suffix): Invert it at the caller.
* dwarf2read.c (dwarf2_compute_name): Invert it at the caller.
Revert:
2011-03-21 Jan Kratochvil <jan.kratochvil@redhat.com>
* dwarf2read.c (producer_is_gxx_lt_4_6): New function.
(dwarf2_add_field): Fix new_field->accessibility for
cu->header.version >= 3 while verifying also producer_is_gxx_lt_4_6.
