']' characters into the output stream.
* v850-opc.c (v850_opcodes: Remove size field from all opcodes.
Add "memop" field to all opcodes (for the disassembler).
Reorder opcodes so that "nop" comes before "mov" and "jr"
comes before "jarl".
Should give us a functional disassembler.
(v850_sreg_names, v850_cc_names): Likewise.
(disassemble): Very rough cut at printing operands (unformatted).
One step at a time.
* v850-opc.c (BOP_MASK): Fix.
(v850_opcodes): Fix mask for jarl and jr.
Bugs exposed by disassembler testing.
* Makefile.in Remove v850 references, they're not needed here
and they weren't being sanitized away.
* configure.in: Add v850-dis.o when building v850 toolchains.
* configure: Rebuilt.
* disassemble.c (disassembler): Call v850 disassembler.
* Makefile.in Remove v850 references, they're not needed here
and they weren't being sanitized away.
* configure.in: Add v850-dis.o when building v850 toolchains.
* configure: Rebuilt.
* disassemble.c (disassembler): Call v850 disassembler.
Skeleton support for V850 disassembler.
(insert_d8_6, extract_d8_6): New functions.
(v850_operands): Rename D7S to D7; operand for D7 is unsigned.
Rename D8 to D8_7, use {insert,extract}_d8_7 routines.
Add D8_6.
(IF4A, IF4B): Use "D7" instead of "D7S".
(IF4C, IF4D): Use "D8_7" instead of "D8".
(IF4E, IF4F): New. Use "D8_6".
(v850_opcodes): Use IF4A/IF4B for sld.b/sst.b. Use IF4C/IF4D for
sld.h/sst.h. Use IF4E/IF4F for sld.w/sst.w.
So we can assemble sst/sld instructions correctly.
(v850_operands): Change D16 to D16_15, use special insert/extract
routines. New new D16 that uses the generic insert/extract code.
(IF7A, IF7B): Use D16_15.
(IF7C, IF7D): New. Use D16.
(v850_opcodes): Use IF7C and IF7D for ld.b and st.b.
(elf_v850_howto_table): Add support for R_V850_{32,16,8}.
(v850_reloc_map): Add translation from BFD_RELOC_{32,16,8}
to R_V850_{32,16,8}.
So we don't get "reloc XXX not supported" messages anymore.
routines to fetch/store the updated instruction from/to memory.
(v850_insert_operand): If the operand has a specialized insert
routine, call it.
Getting fixups closer. At least br <target> works now.
be like identical function found in tc-ppc.c.
(get_reloc): Removed.
(v850_reloc_prefix): New function, parse lo(), hi() and hi0().
(md_assemble): emit fixups.
(md_pcrel_from): renamed from md_pcrel_from_section, emit proper
displacement.
(md_apply_fix3): handle fixups/relocs.
* config/tc-v850.h (MD_PCREL_FROM_SECTION): Removed definition.
* emulparams/shelf.sh: New file.
* emulparams/shlelf.sh: New file.
* Makefile.in (ALL_EMULATIONS): Add eshelf.o and eshlelf.o.
(eshelf.c, eshlelf.c): New targets.
* scripttempl/elf.sc: If EMBEDDED is defined, then don't add
SIZEOF_HEADERS to TEXT_START_ADDR. Expand CTOR_START and CTOR_END
around .ctors, and DTOR_START and DTOR_END around .dtors. Expand
OTHER_RELOCATING_SECTIONS if RELOCATING.
* configure.in (sh-*-elf*): New target.
* config/tc-sh.h (TARGET_ARCH): Define.
(WORKING_DOT_WORD): Define.
(TC_COFF_FIX2RTYPE): Only define if OBJ_COFF.
(BFD_ARCH, COFF_MAGIC, TC_COUNT_RELOC): Likewise.
(TC_RELOC_MANGLE, tc_coff_symbol_emit_hook): Likewise.
(DO_NOT_STRIP, NEED_FX_R_TYPE, TC_KEEP_FX_OFFSET): Likewise.
(TC_COFF_SIZEMACHDEP, tc_frob_file): Likewise.
(SUB_SEGMENT_ALIGN): Likewise.
(RELOC_32): Don't define.
(tc_frob_file_before_adjust): Define if BFD_ASSEMBLER.
(target_big_endian): Declare if OBJ_ELF.
(TARGET_FORMAT): Define if OBJ_ELF.
* config/tc-sh.c: Use BFD reloc codes instead of SH COFF reloc
numbers throughout.
(tc_crawl_symbol_chain): Only define if OBJ_COFF.
(tc_headers_hook, tc_coff_sizemachdep): Likewise.
(struct sh_count_relocs): Define.
(sh_count_relocs): New static function, broken out of
sh_frob_file. Add BFD_ASSEMBLER code.
(sh_frob_section): Likewise.
(sh_frob_file): Call sh_frob_section.
(md_convert_frag): If BFD_ASSEMBLER, change type of headers, and
call section_symbol rather than seg_info (seg)->dot.
(md_section_align): Add OBJ_ELF version.
(SWITCH_TABLE_CONS): Define.
(SWITCH_TABLE): Use SWITCH_TABLE_CONS.
(md_apply_fix): Change parameter types if BFD_ASSEMBLER. Only
handle fx_r_type == 0 if not BFD_ASSEMBLER. Return 0 if
BFD_ASSEMBLER.
(struct reloc_map): Define if not BFD_ASSEMBLER.
(coff_reloc_map): Likewise.
(sh_coff_reloc_mangle): Use coff_reloc_map to convert fx_r_type.
(tc_gen_reloc): New function if BFD_ASSEMBLER.
* write.c (write_relocs): Ifdef out fx_where test which triggers
inappropriately for SH ELF.
(write_object_file): Call tc_frob_file_before_adjust and
obj_frob_file_before_adjust if they are defined.
* write.c (write_object_file): Use BFD_RELOC_16, not
BFD_RELOC_NONE, when calling fix_new_exp for a broken word.
* remote-mips.c: Provide support for CAIRO target board.
(cairo_open, cairo_ops): Added.
(mips_monitor_type): MON_CAIRO Added.
(mips_enter_debug, mips_exit_debug, mips_initialize,
mips_fetch_registers, common_breakpoint, mips_load,
_initialize_remote_mips): Updated.
Add simple support for NEC CAIRO Vr4300 development board.
"sregs" field.
(PSW): Remove bogus definition.
* simops.c: Change condition code handling to use the psw
register within the sregs array. Handle "ldsr" and "stsr".
(lookup_hash): Call hash rather than computing the hash
code here.
(do_format_1_2): Handle format 1 and format 2 instructions.
Get operands correctly and call the target function.
(do_format_6): Get operands correctly and call the target
function.
(do_formats_9_10): Rough cut so shift ops will work.
(sim_resume): Tweak to deal with format 1 and format 2
handling in a single funtion. Don't update the PC
for format 3 insns. Fix typos.
* simops.c: Slightly reorganize. Add condition code handling
to "add", "addi", "and", "andi", "or", "ori", "xor", "xori"
and "not" instructions.
* v850_sim.h (reg_t): Registers are 32bits.
(_state): The V850 has 32 general registers. Add a 32bit
psw and pc register too. Add accessor macros
Fixing lots of stuff. Starting to add condition code support. Basically
check pointing the work to date.
