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b8ac4fa43d
320 Commits
| Author | SHA1 | Message | Date | |
|---|---|---|---|---|
Pip Cet
|
f96bd6c2d7 |
Add support for the WebAssembly file format and the wasm32 ELF conversion to gas and the binutils.
binutils * readelf.c: Add support for wasm32 ELF format WebAssembly files. (guess_is_rela): Likewise. (dump_relocations): Likewise. (is_32bit_abs_reloc): Likewise. (is_none_reloc_): Likewise. * NEWS: Mention the new support. * testsuite/lib/binutils-common.exp (is_elf_format): Mark wasm32 as ELF target. (supports_gnu_unique): Mark wasm32 as supporting STB_GNU_UNIQUE. * testsuite/binutils-all/nm.exp: Mark wasm32 as requiring .size annotations. * testsuite/binutils-all/wasm32: New directory. * testsuite/binutils-all/wasm32/create-wasm.d: New file. * testsuite/binutils-all/wasm32/create-wasm.s: Likewise. * testsuite/binutils-all/wasm32/custom-section.d: Likewise. * testsuite/binutils-all/wasm32/custom-section.s: Likewise. * testsuite/binutils-all/wasm32/invalid-wasm-1.d: Likewise. * testsuite/binutils-all/wasm32/invalid-wasm-1.s: Likewise. * testsuite/binutils-all/wasm32/long-sections.d: Likewise. * testsuite/binutils-all/wasm32/long-sections.s: Likewise. * testsuite/binutils-all/wasm32/parse-wasm.d: Likewise. * testsuite/binutils-all/wasm32/parse-wasm.s: Likewise. * testsuite/binutils-all/wasm32/parse-wasm-2.d: Likewise. * testsuite/binutils-all/wasm32/parse-wasm-2.s: Likewise. * testsuite/binutils-all/wasm32/prepared-section.d: Likewise. * testsuite/binutils-all/wasm32/prepared-section.s: Likewise. * testsuite/binutils-all/wasm32/wasm32.exp: New file, run tests. gas * config/tc-wasm32.h: New file: Add WebAssembly assembler target. * config/tc-wasm32.c: New file: Add WebAssembly assembler target. * Makefile.am: Add WebAssembly assembler target. * configure.tgt: Add WebAssembly assembler target. * doc/c-wasm32.texi: New file: Start documenting WebAssembly assembler. * doc/all.texi: Define WASM32. * doc/as.texinfo: Add WebAssembly entries. * NEWS: Mention the new support. * Makefile.in: Regenerate. * po/gas.pot: Regenerate. * po/POTFILES.in: Regenerate. * testsuite/gas/wasm32: New directory. * testsuite/gas/wasm32/allinsn.d: New file. * testsuite/gas/wasm32/allinsn.s: New file. * testsuite/gas/wasm32/illegal.l: New file. * testsuite/gas/wasm32/illegal.s: New file. * testsuite/gas/wasm32/illegal-2.l: New file. * testsuite/gas/wasm32/illegal-2.s: New file. * testsuite/gas/wasm32/illegal-3.l: New file. * testsuite/gas/wasm32/illegal-3.s: New file. * testsuite/gas/wasm32/illegal-4.l: New file. * testsuite/gas/wasm32/illegal-4.s: New file. * testsuite/gas/wasm32/illegal-5.l: New file. * testsuite/gas/wasm32/illegal-5.s: New file. * testsuite/gas/wasm32/illegal-6.l: New file. * testsuite/gas/wasm32/illegal-6.s: New file. * testsuite/gas/wasm32/illegal-7.l: New file. * testsuite/gas/wasm32/illegal-7.s: New file. * testsuite/gas/wasm32/illegal-8.l: New file. * testsuite/gas/wasm32/illegal-8.s: New file. * testsuite/gas/wasm32/illegal-9.l: New file. * testsuite/gas/wasm32/illegal-9.s: New file. * testsuite/gas/wasm32/illegal-10.l: New file. * testsuite/gas/wasm32/illegal-10.s: New file. * testsuite/gas/wasm32/illegal-11.l: New file. * testsuite/gas/wasm32/illegal-11.s: New file. * testsuite/gas/wasm32/illegal-12.l: New file. * testsuite/gas/wasm32/illegal-12.s: New file. * testsuite/gas/wasm32/illegal-13.l: New file. * testsuite/gas/wasm32/illegal-13.s: New file. * testsuite/gas/wasm32/illegal-14.l: New file. * testsuite/gas/wasm32/illegal-14.s: New file. * testsuite/gas/wasm32/illegal-15.l: New file. * testsuite/gas/wasm32/illegal-15.s: New file. * testsuite/gas/wasm32/illegal-16.l: New file. * testsuite/gas/wasm32/illegal-16.s: New file. * testsuite/gas/wasm32/illegal-17.l: New file. * testsuite/gas/wasm32/illegal-17.s: New file. * testsuite/gas/wasm32/illegal-18.l: New file. * testsuite/gas/wasm32/illegal-18.s: New file. * testsuite/gas/wasm32/illegal-19.l: New file. * testsuite/gas/wasm32/illegal-19.s: New file. * testsuite/gas/wasm32/illegal-20.l: New file. * testsuite/gas/wasm32/illegal-20.s: New file. * testsuite/gas/wasm32/illegal-21.l: New file. * testsuite/gas/wasm32/illegal-21.s: New file. * testsuite/gas/wasm32/illegal-22.l: New file. * testsuite/gas/wasm32/illegal-22.s: New file. * testsuite/gas/wasm32/illegal-24.l: New file. * testsuite/gas/wasm32/illegal-24.s: New file. * testsuite/gas/wasm32/illegal-25.l: New file. * testsuite/gas/wasm32/illegal-25.s: New file. * testsuite/gas/wasm32/reloc.d: New file. * testsuite/gas/wasm32/reloc.s: New file. * testsuite/gas/wasm32/wasm32.exp: New tests for WebAssembly architecture. opcodes * configure.ac: Add (empty) bfd_wasm32_arch target. * configure: Regenerate * po/opcodes.pot: Regenerate. include * opcode/wasm.h: New file to support wasm32 architecture. * elf/wasm32.h: Add R_WASM32_32 relocation. bfd * elf32-wasm32.c: Add relocation code, two relocs. * reloc.c: Add wasm32 relocations. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate. * bfd/po/bfd.pot: Regenerate. |
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Nick Clifton
|
f955cccff3 |
Rename R_AARCH64_TLSDESC_LD64_LO12_NC to R_AARCH64_TLSDESC_LD64_LO12 and R_AARCH64_TLSDESC_ADD_LO12_NC to R_AARCH64_TLSDESC_ADD_LO12.
PR binutils/21202 include * elf/aarch64.h (R_AARCH64_TLSDESC_LD64_LO12_NC): Rename to R_AARCH64_TLSDESC_LD64_LO12. (R_AARCH64_TLSDESC_ADD_LO12_NC): Rename to R_AARCH64_TLSDESC_ADD_LO12_NC. bfd * reloc.c (BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC): Rename to BFD_RELOC_AARCH64_TLSDESC_LD64_LO12. (BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC): Rename to BFD_RELOC_AARCH64_TLSDESC_ADD_LO12. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elfnn-aarch64.c (IS_AARCH64_TLS_RELAX_RELOC): Update reloc names. (IS_AARCH64_TLSDESC_RELOC): Likewise. (elfNN_aarch64_howto_table): Likewise. (aarch64_tls_transition_without_check): Likewise. (aarch64_reloc_got_type): Likewise. (elfNN_aarch64_final_link_relocate): Likewise. (elfNN_aarch64_tls_relax): Likewise. (elfNN_aarch64_relocate_section): Likewise. (elfNN_aarch64_gc_sweep_hook): Likewise. (elfNN_aarch64_check_relocs): Likewise. * elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Likewise. (_bfd_aarch64_elf_resolve_relocation): Likewise. gas * config/tc-aarch64.c (reloc_table): Rename BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC to BFD_RELOC_AARCH64_TLSDESC_LD64_LO12. Rname BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC to BFD_RELOC_AARCH64_TLSDESC_ADD_LO12. (md_apply_fix): Likewise. (aarch64_force_relocation): Likewise. * testsuite/gas/aarch64/tls.d: Update regexp. ld * testsuite/ld-aarch64/ifunc-5r-local.d: Update regexp. |
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Alan Modra
|
7ba71655a4 |
PowerPC addpcis fix
This came up because I was looking at ld/tmpdir/addpcis.o and noticed the odd addends on REL16DX_HA. They ought to both be -4. The error crept in due REL16DX_HA howto being pc-relative (as indeed it should be), and code at gas/write.c:1001 after this comment /* Make it pc-relative. If the back-end code has not selected a pc-relative reloc, cancel the adjustment we do later on all pc-relative relocs. */ *not* cancelling the pc-relative adjustment. So I've made a dummy non-relative split reloc so that the generic code handles this, rather than attempting to add hacks later in md_apply_fix which would not be very robust. Having the new internal reloc also makes it easy to support addpcis rx,sym@ha as an equivalent to addpcis rx,(sym-0f)@ha 0: The patch also fixes overflow checking, which must test whether the addi will overflow too since @l relocs don't have any overflow check. Lastly, since I was poking at md_apply_fix, I arranged to have the generic gas/write.c code emit errors for subtraction expressions where we lack reloc support. include/ * elf/ppc64.h (R_PPC64_16DX_HA): New. Expand fake reloc comment. * elf/ppc.h (R_PPC_16DX_HA): Likewise. bfd/ * reloc.c (BFD_RELOC_PPC_16DX_HA): New. * elf64-ppc.c (ppc64_elf_howto_raw <R_PPC64_16DX_HA>): New howto. (ppc64_elf_reloc_type_lookup): Translate new bfd reloc. (ppc64_elf_ha_reloc): Correct overflow test on REL16DX_HA. (ppc64_elf_relocate_section): Likewise. * elf32-ppc.c (ppc_elf_howto_raw <R_PPC_16DX_HA>): New howto. (ppc_elf_reloc_type_lookup): Translate new bfd reloc. (ppc_elf_check_relocs): Handle R_PPC_16DX_HA to pacify gcc. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate. gas/ * config/tc-ppc.c (md_assemble): Use BFD_RELOC_PPC_16DX_HA for addpcis. (md_apply_fix): Remove fx_subsy check. Move code converting to pcrel reloc earlier and handle BFD_RELOC_PPC_16DX_HA. Remove code emiiting errors on seeing fx_pcrel set on unexpected relocs, as that is done now by the generic code via.. * config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): ..this. Define. (TC_VALIDATE_FIX_SUB): Define. ld/ * testsuite/ld-powerpc/addpcis.d: Define ext1 and ext2 at limits of addpcis range. |
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|
Alan Modra
|
2571583aed | Update year range in copyright notice of all files. | ||
Dimitar Dimitrov
|
889294f6ff |
PRU BFD support
include/ * elf/common.h: Add PRU ELF. * elf/pru.h: New file. * opcode/pru.h: New file. * dis-asm.h (print_insn_pru): Declare. bfd/ * archures.c: Add bfd_arch_pru. * Makefile.am: Add PRU target. * config.bfd: Ditto. * configure.ac: Ditto. * elf-bfd.h (enum elf_target_id): Add PRU_ELF_DATA. * targets.c: Add pru_elf32_vec. * reloc.c: Add PRU relocations. * cpu-pru.c: New file. * elf32-pru.c: New file. * Makefile.in: Regenerate. * configure: Regenerate. * po/SRC-POTFILES.in: Regenerate. * bfd-in2.h: Regenerate * libbfd.h: Regenerate. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu> |
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Andrew Waterman
|
45f764234a |
Rework RISC-V relocations
Before this commit we didn't cleanly support CFI directives because the internal offsets used to get relaxed which broke them. This patch significantly reworks how we handle linker relaxations: * DWARF is now properly supported * There is a ".option norelax" to disable relaxations, for when users write assembly that can't be relaxed (if it's to be later patched up, for example). * There is an additional _RELAX relocation that specifies when previous relocations can be relaxed. We're in the process of documenting the RISC-V ELF ABI, which will include documentation of our relocations https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md but we expect that this relocation set will remain ABI compatible in the future (ie, it's safe to release). Thanks to Kuan-Lin Chen for figuring out how to correctly relax the debug info! include/ * elf/riscv.h: Add R_RISCV_TPREL_I through R_RISCV_SET32. bfd/ * reloc.c (BFD_RELOC_RISCV_TPREL_I): New relocation. (BFD_RELOC_RISCV_TPREL_S): Likewise. (BFD_RELOC_RISCV_RELAX): Likewise. (BFD_RELOC_RISCV_CFA): Likewise. (BFD_RELOC_RISCV_SUB6): Likewise. (BFD_RELOC_RISCV_SET8): Likewise. (BFD_RELOC_RISCV_SET8): Likewise. (BFD_RELOC_RISCV_SET16): Likewise. (BFD_RELOC_RISCV_SET32): Likewise. * elfnn-riscv.c (perform_relocation): Handle the new relocations. (_bfd_riscv_relax_tls_le): Likewise. (_bfd_riscv_relax_align): Likewise. (_bfd_riscv_relax_section): Likewise. (howto_table): Likewise. (riscv_reloc_map): Likewise. (relax_func_t): New type. (_bfd_riscv_relax_call): Add reserve_size argument, which controls the maximal offset pessimism. Correct type of max_alignment. (_bfd_riscv_relax_lui): Likewise. (_bfd_riscv_relax_tls_le): Likewise. (_bfd_riscv_relax_align): Likewise. (_bfd_riscv_relax_section): Compute the required reserve size when relocating and use it to when calling relax_func. * bfd-in2.h: Regenerate. * libbfd.h: Likewise. gas/ * config/tc-riscv.c (riscv_set_options): Add relax. (riscv_opts): Likewise. (s_riscv_option): Add relax and norelax. (riscv_apply_const_reloc): New function. (append_insn): Move constant relocation handling to riscv_apply_const_reloc. (md_pcrel_from): Likewise. (parse_relocation): Skip BFD_RELOC_UNUSED. (md_pcrel_from): Handle BFD_RELOC_RISCV_SUB6, BFD_RELOC_RISCV_RELAX, BFD_RELOC_RISCV_CFA. (md_apply_fix): Likewise. (riscv_pre_output_hook): New function. * config/tc-riscv.h (md_pre_output_hook): Define. (riscv_pre_output_hook): Declare. (DWARF_CIE_DATA_ALIGNMENT): Always -4. |
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Maciej W. Rozycki
|
af955fe696 |
BFD: Fix double BFD_FAIL calls in `bfd_default_reloc_type_lookup'
Break out of the outer switch statement once the inner switch for the
BFD_RELOC_CTOR relocation has been processed, preventing double BFD_FAIL
calls from being made, once from the inner switch and then again from
the default case of the outer switch.
Noticed with a `-Wimplicit-fallthrough' build error reported by a recent
GCC version:
In file included from .../bfd/reloc.c:52:0:
.../bfd/reloc.c: In function 'bfd_default_reloc_type_lookup':
.../bfd/libbfd.h:779:8: error: this statement may fall through [-Werror=implicit-fallthrough=]
do { bfd_assert(__FILE__,__LINE__); } while (0)
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.../bfd/reloc.c:7780:4: note: in expansion of macro 'BFD_FAIL'
BFD_FAIL ();
^~~~~~~~
.../bfd/reloc.c:7782:5: note: here
default:
^~~~~~~
cc1: all warnings being treated as errors
make[4]: *** [reloc.lo] Error 1
bfd/
* reloc.c (bfd_default_reloc_type_lookup) <BFD_RELOC_CTOR>: Do
not fall through to the default case.
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Nick Clifton
|
e23eba971d |
Add support for RISC-V architecture.
bfd * Makefile.am: Add entries for riscv32-elf and riscv64-elf. * config.bdf: Likewise. * configure.ac: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * archures.c: Add bfd_riscv_arch. * reloc.c: Add riscv relocs. * targets.c: Add riscv_elf32_vec and riscv_elf64_vec. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elf-bfd.h: Add RISCV_ELF_DATA to enum elf_target_id. * elfnn-riscv.c: New file. * elfxx-riscv.c: New file. * elfxx-riscv.h: New file. binutils* readelf.c (guess_is_rela): Add EM_RISCV. (get_machine_name): Likewise. (dump_relocations): Add support for riscv relocations. (get_machine_flags): Add support for riscv flags. (is_32bit_abs_reloc): Add R_RISCV_32. (is_64bit_abs_reloc): Add R_RISCV_64. (is_none_reloc): Add R_RISCV_NONE. * testsuite/binutils-all/objdump.exp (cpus_expected): Add riscv. Expect the debug_ranges test to fail. gas * Makefile.am: Add riscv files. * Makefile.in: Regenerate. * NEWS: Mention the support for this architecture. * configure.in: Define a default architecture. * configure: Regenerate. * configure.tgt: Add entries for riscv. * doc/as.texinfo: Likewise. * testsuite/gas/all/gas.exp: Expect the redef tests to fail. * testsuite/gas/elf/elf.exp: Expect the groupauto tests to fail. * config/tc-riscv.c: New file. * config/tc-riscv.h: New file. * doc/c-riscv.texi: New file. * testsuite/gas/riscv: New directory. * testsuite/gas/riscv/riscv.exp: New file. * testsuite/gas/riscv/t_insns.d: New file. * testsuite/gas/riscv/t_insns.s: New file. ld * Makefile.am: Add riscv files. * Makefile.in: Regenerate. * NEWS: Mention the support for this target. * configure.tgt: Add riscv entries. * emulparams/elf32lriscv-defs.sh: New file. * emulparams/elf32lriscv.sh: New file. * emulparams/elf64lriscv-defs.sh: New file. * emulparams/elf64lriscv.sh: New file. * emultempl/riscvelf.em: New file. opcodes * configure.ac: Add entry for bfd_riscv_arch. * configure: Regenerate. * disassemble.c (disassembler): Add support for riscv. (disassembler_usage): Likewise. * riscv-dis.c: New file. * riscv-opc.c: New file. include * dis-asm.h: Add prototypes for print_insn_riscv and print_riscv_disassembler_options. * elf/riscv.h: New file. * opcode/riscv-opc.h: New file. * opcode/riscv.h: New file. |
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Nick Clifton
|
695344c018 |
Add c-format tags to translatable strings with more than one argument-using formatting token.
* aout-adobe.c: Add missing c-format tags for translatable strings. * aout-cris.c: Likewise. * aoutx.h: Likewise. * bfd.c: Likewise. * binary.c: Likewise. * cache.c: Likewise. * coff-alpha.c: Likewise. * coff-arm.c: Likewise. * coff-i860.c: Likewise. * coff-mcore.c: Likewise. * coff-ppc.c: Likewise. * coff-rs6000.c: Likewise. * coff-sh.c: Likewise. * coff-tic4x.c: Likewise. * coff-tic54x.c: Likewise. * coff-tic80.c: Likewise. * coff64-rs6000.c: Likewise. * coffcode.h: Likewise. * coffgen.c: Likewise. * cofflink.c: Likewise. * coffswap.h: Likewise. * cpu-arm.c: Likewise. * dwarf2.c: Likewise. * ecoff.c: Likewise. * elf-attrs.c: Likewise. * elf-eh-frame.c: Likewise. * elf-ifunc.c: Likewise. * elf-m10300.c: Likewise. * elf-s390-common.c: Likewise. * elf.c: Likewise. * elf32-arc.c: Likewise. * elf32-arm.c: Likewise. * elf32-avr.c: Likewise. * elf32-bfin.c: Likewise. * elf32-cr16.c: Likewise. * elf32-cr16c.c: Likewise. * elf32-cris.c: Likewise. * elf32-crx.c: Likewise. * elf32-d10v.c: Likewise. * elf32-d30v.c: Likewise. * elf32-epiphany.c: Likewise. * elf32-fr30.c: Likewise. * elf32-frv.c: Likewise. * elf32-gen.c: Likewise. * elf32-hppa.c: Likewise. * elf32-i370.c: Likewise. * elf32-i386.c: Likewise. * elf32-i960.c: Likewise. * elf32-ip2k.c: Likewise. * elf32-iq2000.c: Likewise. * elf32-lm32.c: Likewise. * elf32-m32c.c: Likewise. * elf32-m32r.c: Likewise. * elf32-m68hc11.c: Likewise. * elf32-m68hc12.c: Likewise. * elf32-m68hc1x.c: Likewise. * elf32-m68k.c: Likewise. * elf32-mcore.c: Likewise. * elf32-mep.c: Likewise. * elf32-metag.c: Likewise. * elf32-microblaze.c: Likewise. * elf32-moxie.c: Likewise. * elf32-msp430.c: Likewise. * elf32-mt.c: Likewise. * elf32-nds32.c: Likewise. * elf32-nios2.c: Likewise. * elf32-or1k.c: Likewise. * elf32-pj.c: Likewise. * elf32-ppc.c: Likewise. * elf32-rl78.c: Likewise. * elf32-rx.c: Likewise. * elf32-s390.c: Likewise. * elf32-score.c: Likewise. * elf32-score7.c: Likewise. * elf32-sh-symbian.c: Likewise. * elf32-sh.c: Likewise. * elf32-sh64.c: Likewise. * elf32-spu.c: Likewise. * elf32-tic6x.c: Likewise. * elf32-tilepro.c: Likewise. * elf32-v850.c: Likewise. * elf32-vax.c: Likewise. * elf32-visium.c: Likewise. * elf32-xgate.c: Likewise. * elf32-xtensa.c: Likewise. * elf64-alpha.c: Likewise. * elf64-gen.c: Likewise. * elf64-hppa.c: Likewise. * elf64-ia64-vms.c: Likewise. * elf64-mmix.c: Likewise. * elf64-ppc.c: Likewise. * elf64-s390.c: Likewise. * elf64-sh64.c: Likewise. * elf64-sparc.c: Likewise. * elf64-x86-64.c: Likewise. * elfcode.h: Likewise. * elfcore.h: Likewise. * elflink.c: Likewise. * elfnn-aarch64.c: Likewise. * elfnn-ia64.c: Likewise. * elfxx-mips.c: Likewise. * elfxx-sparc.c: Likewise. * elfxx-tilegx.c: Likewise. * ieee.c: Likewise. * ihex.c: Likewise. * libbfd.c: Likewise. * linker.c: Likewise. * m68klinux.c: Likewise. * mach-o.c: Likewise. * merge.c: Likewise. * mmo.c: Likewise. * oasys.c: Likewise. * pdp11.c: Likewise. * pe-mips.c: Likewise. * peXXigen.c: Likewise. * pei-x86_64.c: Likewise. * peicode.h: Likewise. * ppcboot.c: Likewise. * reloc.c: Likewise. * sparclinux.c: Likewise. * srec.c: Likewise. * stabs.c: Likewise. * vms-alpha.c: Likewise. * vms-lib.c: Likewise. * xcofflink.c: Likewise. |
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Alan Modra
|
2b80414579 |
-Wimplicit-fallthrough error fixes
Well, not all are errors, but a little more substantive than just fiddling with comments. bfd/ * coffcode.h (coff_slurp_symbol_table): Revert accidental commit made 2015-01-08. * elf32-nds32.c (nds32_elf_grok_psinfo): Add missing break. * reloc.c (bfd_default_reloc_type_lookup): Add missing breaks. opcodes/ * arc-ext.c (create_map): Add missing break. * msp430-decode.opc (encode_as): Likewise. * msp430-decode.c: Regenerate. binutils/ * coffdump.c (dump_coff_where): Add missing break. * stabs.c (stab_xcoff_builtin_type): Likewise. gas/ * config/tc-arc.c (find_opcode_match): Add missing break. * config/tc-i960.c (get_cdisp): Likewise. * config/tc-metag.c (parse_swap, md_apply_fix): Likewise. * config/tc-mt.c (md_parse_option): Likewise. * config/tc-nds32.c (nds32_apply_fix): Likewise. * config/tc-hppa.c (pa_ip): Assert rather than testing last condition of multiple if statements. * config/tc-s390.c (s390_exp_compare): Return 0 on error. * config/tc-tic4x.c (tic4x_operand_parse): Add as_bad and break out of case rather than falling into next case. Formatting. ld/ * plugin.c (asymbol_from_plugin_symbol): Avoid compiler warning by adding return. |
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Alan Modra
|
4eca02287c |
Remove syntactic sugar
Now that _bfd_error_handler is not a function pointer. * aout-adobe.c: Replace (*_bfd_error_handler) (...) with _bfd_error_handler (...) throughout. * aout-cris.c, * aoutx.h, * archive.c, * bfd.c, * binary.c, * cache.c, * coff-alpha.c, * coff-arm.c, * coff-h8300.c, * coff-i860.c, * coff-mcore.c, * coff-ppc.c, * coff-rs6000.c, * coff-sh.c, * coff-tic4x.c, * coff-tic54x.c, * coff-tic80.c, * coff64-rs6000.c, * coffcode.h, * coffgen.c, * cofflink.c, * coffswap.h, * cpu-arm.c, * cpu-m68k.c, * cpu-sh.c, * dwarf2.c, * ecoff.c, * elf-eh-frame.c, * elf-m10300.c, * elf.c, * elf32-arc.c, * elf32-arm.c, * elf32-avr.c, * elf32-bfin.c, * elf32-cr16.c, * elf32-cris.c, * elf32-crx.c, * elf32-dlx.c, * elf32-frv.c, * elf32-hppa.c, * elf32-i370.c, * elf32-i386.c, * elf32-lm32.c, * elf32-m32c.c, * elf32-m32r.c, * elf32-m68hc1x.c, * elf32-m68k.c, * elf32-mcore.c, * elf32-mep.c, * elf32-metag.c, * elf32-microblaze.c, * elf32-mips.c, * elf32-nds32.c, * elf32-nios2.c, * elf32-or1k.c, * elf32-pj.c, * elf32-ppc.c, * elf32-rl78.c, * elf32-s390.c, * elf32-score.c, * elf32-score7.c, * elf32-sh.c, * elf32-sh64.c, * elf32-sparc.c, * elf32-spu.c, * elf32-tic6x.c, * elf32-tilepro.c, * elf32-v850.c, * elf32-vax.c, * elf32-xtensa.c, * elf64-alpha.c, * elf64-hppa.c, * elf64-ia64-vms.c, * elf64-mips.c, * elf64-mmix.c, * elf64-ppc.c, * elf64-s390.c, * elf64-sh64.c, * elf64-sparc.c, * elf64-x86-64.c, * elfcode.h, * elfcore.h, * elflink.c, * elfn32-mips.c, * elfnn-aarch64.c, * elfnn-ia64.c, * elfxx-mips.c, * elfxx-sparc.c, * elfxx-tilegx.c, * hpux-core.c, * i386linux.c, * ieee.c, * ihex.c, * libbfd.c, * linker.c, * m68klinux.c, * mach-o.c, * merge.c, * mmo.c, * oasys.c, * osf-core.c, * pdp11.c, * pe-mips.c, * peXXigen.c, * pef.c, * plugin.c, * reloc.c, * rs6000-core.c, * sco5-core.c, * som.c, * sparclinux.c, * srec.c, * stabs.c, * syms.c, * vms-alpha.c, * vms-lib.c, * vms-misc.c, * xcofflink.c: Likewise. |
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Cupertino Miranda
|
a87aa054a6 |
Fixes to legacy ARC relocations.
Added support for ARC_SDA_12 reloc. Fixed ARC_N32_ME. Added ME (middle-endian) to ARC_SDA_12 reloc. bfd/ChangeLog: Cupertino Miranda <cmiranda@synopsys.com> * reloc.c: Fixed type in ARC_SECTOFF relocations. Added ARC_SDA_12 relocation. * bfd-in2.h: Regenerated from the previous changes. * libbfd.h: Regenerated from the previous changes. include/ChangeLog: Cupertino Miranda <cmiranda@synopsys.com> * elf/arc-reloc.def: Fixed relocation formula for N*, SDA, SDA_12, SDA_16_LD*, S13_PCREL, N32_ME, SECTOFF_* relocations. * opcode/arc-func.h (replace_disp12s): Added. Used for SDA_12 relocation. |
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Maciej W. Rozycki
|
0c11728627 |
BFD: Let targets handle relocations against absolute symbols
Fix a generic BFD issue with relocations against absolute symbols, which are installed without using any individual relocation handler provided by the backend. This causes any absolute section's addend to be lost on REL targets such as o32 MIPS, and also relocation-specific calculation adjustments are not made. As an example assembling this program: $ cat test.s .text foo: b bar b baz .set bar, 0x1234 $ as -EB -32 -o test-o32.o test.s $ as -EB -n32 -o test-n32.o test.s produces this binary code: $ objdump -dr test-o32.o test-n32.o test-o32.o: file format elf32-tradbigmips Disassembly of section .text: 00000000 <foo>: 0: 10000000 b 4 <foo+0x4> 0: R_MIPS_PC16 *ABS* 4: 00000000 nop 8: 1000ffff b 8 <foo+0x8> 8: R_MIPS_PC16 baz c: 00000000 nop test-n32.o: file format elf32-ntradbigmips Disassembly of section .text: 00000000 <foo>: 0: 10000000 b 4 <foo+0x4> 0: R_MIPS_PC16 *ABS*+0x1230 4: 00000000 nop 8: 10000000 b c <foo+0xc> 8: R_MIPS_PC16 baz-0x4 c: 00000000 nop $ where it is clearly visible in `test-o32.o', which uses REL relocations, that the absolute section's addend equivalent to the value of `bar' -- a reference to which cannot be fully resolved at the assembly time, because the reference is PC-relative -- has been lost, as has been the relocation-specific adjustment of -4, required to take into account the PC+4-relative calculation made by hardware with branches and seen in the external symbol reference to `baz' as the `ffff' addend encoded in the instruction word. In `test-n32.o', which uses RELA relocations, the absolute section's addend has been correctly retained. Give precedence then in `bfd_perform_relocation' and `bfd_install_relocation' to any individual relocation handler the backend selected may have provided, while still resorting to the generic calculation otherwise. This retains the semantics which we've had since forever or before the beginning of our repository history, and is at the very least compatible with `bfd_elf_generic_reloc' being used as the handler. Retain the `bfd_is_und_section' check unchanged at the beginning of `bfd_perform_relocation' since this does not affect the semantics of the function. The check returns the same `bfd_reloc_undefined' code the check for a null `howto' does, so swapping the two does not matter. Also the check is is mutually exclusive with the `bfd_is_abs_section' check, since a section cannot be absolute and undefined both at once, so swapping the two does not matter either. With this change applied the program quoted above now has the in-place addend correctly calculated and installed in the field being relocated: $ objdump -dr fixed-o32.o fixed-o32.o: file format elf32-tradbigmips Disassembly of section .text: 00000000 <foo>: 0: 1000048c b 1234 <bar> 0: R_MIPS_PC16 *ABS* 4: 00000000 nop 8: 1000ffff b 8 <foo+0x8> 8: R_MIPS_PC16 baz c: 00000000 nop $ Add a set of MIPS tests to cover the relevant cases, including absolute symbols with addends, and verifying that PC-relative relocations against symbols concerned resolve to the same value in the final link regardless of whether the REL or the RELA relocation form is used. Exclude linker tests though which would overflow the in-place addend on REL targets and use them as dump patterns for RELA targets only. bfd/ * reloc.c (bfd_perform_relocation): Try the `howto' handler first with relocations against absolute symbols. (bfd_install_relocation): Likewise. gas/ * testsuite/gas/mips/mips16-branch-absolute.d: Update patterns. * testsuite/gas/mips/branch-absolute.d: New test. * testsuite/gas/mips/branch-absolute-n32.d: New test. * testsuite/gas/mips/branch-absolute-n64.d: New test. * testsuite/gas/mips/branch-absolute-addend-n32.d: New test. * testsuite/gas/mips/branch-absolute-addend-n64.d: New test. * testsuite/gas/mips/mips16-branch-absolute-n32.d: New test. * testsuite/gas/mips/mips16-branch-absolute-n64.d: New test. * testsuite/gas/mips/mips16-branch-absolute-addend-n32.d: New test. * testsuite/gas/mips/mips16-branch-absolute-addend-n64.d: New test. * testsuite/gas/mips/micromips-branch-absolute.d: New test. * testsuite/gas/mips/micromips-branch-absolute-n32.d: New test. * testsuite/gas/mips/micromips-branch-absolute-n64.d: New test. * testsuite/gas/mips/micromips-branch-absolute-addend-n32.d: New test. * testsuite/gas/mips/micromips-branch-absolute-addend-n64.d: New test. * testsuite/gas/mips/branch-absolute.s: New test source. * testsuite/gas/mips/branch-absolute-addend.s: New test source. * testsuite/gas/mips/mips16-branch-absolute-addend.s: New test source. * testsuite/gas/mips/micromips-branch-absolute.s: New test source. * testsuite/gas/mips/micromips-branch-absolute-addend.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. ld/ * testsuite/ld-mips-elf/branch-absolute.d: New test. * testsuite/ld-mips-elf/branch-absolute-n32.d: New test. * testsuite/ld-mips-elf/branch-absolute-n64.d: New test. * testsuite/ld-mips-elf/branch-absolute-addend.d: New test. * testsuite/ld-mips-elf/branch-absolute-addend-n32.d: New test. * testsuite/ld-mips-elf/branch-absolute-addend-n64.d: New test. * testsuite/ld-mips-elf/micromips-branch-absolute.d: New test. * testsuite/ld-mips-elf/micromips-branch-absolute-n32.d: New test. * testsuite/ld-mips-elf/micromips-branch-absolute-n64.d: New test. * testsuite/ld-mips-elf/micromips-branch-absolute-addend.d: New test. * testsuite/ld-mips-elf/micromips-branch-absolute-addend-n32.d: New test. * testsuite/ld-mips-elf/micromips-branch-absolute-addend-n64.d: New test. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests, except from `branch-absolute-addend' and `micromips-branch-absolute-addend', referred indirectly only. |
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Maciej W. Rozycki
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c9775dde32 |
MIPS16: Add R_MIPS16_PC16_S1 branch relocation support
For R_MIPS16_PC16_S1 the calculation is `(sign_extend(A) + S - P) >> 1' and the usual MIPS16 bit shuffling applies to relocated field handling, as per the encoding of the branch target in the extended form of the MIPS16 B, BEQZ, BNEZ, BTEQZ and BTNEZ instructions. include/ * elf/mips.h (R_MIPS16_PC16_S1): New relocation. bfd/ * elf32-mips.c (elf_mips16_howto_table_rel): Add R_MIPS16_PC16_S1. (mips16_reloc_map): Likewise. * elf64-mips.c (mips16_elf64_howto_table_rel): Likewise. (mips16_elf64_howto_table_rela): Likewise. (mips16_reloc_map): Likewise. * elfn32-mips.c (elf_mips16_howto_table_rel): Likewise. (elf_mips16_howto_table_rela): Likewise. (mips16_reloc_map): Likewise. * elfxx-mips.c (mips16_branch_reloc_p): New function. (mips16_reloc_p): Handle R_MIPS16_PC16_S1. (b_reloc_p): Likewise. (mips_elf_calculate_relocation): Likewise. (_bfd_mips_elf_check_relocs): Likewise. * reloc.c (BFD_RELOC_MIPS16_16_PCREL_S1): New relocation. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas/ * config/tc-mips.c (mips16_reloc_p): Handle BFD_RELOC_MIPS16_16_PCREL_S1. (b_reloc_p): Likewise. (limited_pcrel_reloc_p): Likewise. (md_pcrel_from): Likewise. (md_apply_fix): Likewise. (tc_gen_reloc): Likewise. (md_convert_frag): Likewise. (mips_fix_adjustable): Update comment. * testsuite/gas/mips/mips16-branch-reloc-2.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-branch-reloc-3.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-branch-addend-2.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-branch-addend-3.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-branch-absolute.d: Remove error output, add dump patterns. * testsuite/gas/mips/mips16-branch-reloc-2.l: Remove file. * testsuite/gas/mips/mips16-branch-reloc-3.l: Remove file. * testsuite/gas/mips/mips16-branch-addend-2.l: Remove file. * testsuite/gas/mips/mips16-branch-addend-3.l: Remove file. * testsuite/gas/mips/mips16-branch-absolute.l: Remove file. * testsuite/gas/mips/mips16-branch-addend-2.s: Add padding. * testsuite/gas/mips/branch-weak.s: Adjust alignment, avoid implicit instruction padding, avoid MIPS16 JR->JRC conversion. * testsuite/gas/mips/branch-weak-6.d: New test. * testsuite/gas/mips/branch-weak-7.d: New test. * testsuite/gas/mips/mips.exp: Run the new tests. ld/ * testsuite/ld-mips-elf/mips16-branch-2.d: New test. * testsuite/ld-mips-elf/mips16-branch-3.d: New test. * testsuite/ld-mips-elf/mips16-branch-addend-2.d: New test. * testsuite/ld-mips-elf/mips16-branch-addend-3.d: New test. * testsuite/ld-mips-elf/mips16-branch.s: New test source. * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests. |
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Alan Modra
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1a72702bb3 |
Return void from linker callbacks
The ldmain.c implementation of these linker callback functions always return true, so any code handling a false return is dead. What's more, some of the bfd backends abort if ever a false return is seen, and there seems to be some confusion in gdb's compile-object-load.c. The return value was never meant to be "oh yes, a multiple_definition error occurred", but rather "out of memory or other catastrophic failure". This patch removes the status return on the callbacks that always return true. I kept the return status for "notice" because that one does happen to need to return "out of memory". include/ * bfdlink.h (struct bfd_link_callbacks): Update comments. Return void from multiple_definition, multiple_common, add_to_set, constructor, warning, undefined_symbol, reloc_overflow, reloc_dangerous and unattached_reloc. bfd/ * aoutx.h: Adjust linker callback calls throughout file, removing dead code. * bout.c: Likewise. * coff-alpha.c: Likewise. * coff-arm.c: Likewise. * coff-h8300.c: Likewise. * coff-h8500.c: Likewise. * coff-i960.c: Likewise. * coff-mcore.c: Likewise. * coff-mips.c: Likewise. * coff-ppc.c: Likewise. * coff-rs6000.c: Likewise. * coff-sh.c: Likewise. * coff-tic80.c: Likewise. * coff-w65.c: Likewise. * coff-z80.c: Likewise. * coff-z8k.c: Likewise. * coff64-rs6000.c: Likewise. * cofflink.c: Likewise. * ecoff.c: Likewise. * elf-bfd.h: Likewise. * elf-m10200.c: Likewise. * elf-m10300.c: Likewise. * elf32-arc.c: Likewise. * elf32-arm.c: Likewise. * elf32-avr.c: Likewise. * elf32-bfin.c: Likewise. * elf32-cr16.c: Likewise. * elf32-cr16c.c: Likewise. * elf32-cris.c: Likewise. * elf32-crx.c: Likewise. * elf32-d10v.c: Likewise. * elf32-epiphany.c: Likewise. * elf32-fr30.c: Likewise. * elf32-frv.c: Likewise. * elf32-ft32.c: Likewise. * elf32-h8300.c: Likewise. * elf32-hppa.c: Likewise. * elf32-i370.c: Likewise. * elf32-i386.c: Likewise. * elf32-i860.c: Likewise. * elf32-ip2k.c: Likewise. * elf32-iq2000.c: Likewise. * elf32-lm32.c: Likewise. * elf32-m32c.c: Likewise. * elf32-m32r.c: Likewise. * elf32-m68hc1x.c: Likewise. * elf32-m68k.c: Likewise. * elf32-mep.c: Likewise. * elf32-metag.c: Likewise. * elf32-microblaze.c: Likewise. * elf32-moxie.c: Likewise. * elf32-msp430.c: Likewise. * elf32-mt.c: Likewise. * elf32-nds32.c: Likewise. * elf32-nios2.c: Likewise. * elf32-or1k.c: Likewise. * elf32-ppc.c: Likewise. * elf32-s390.c: Likewise. * elf32-score.c: Likewise. * elf32-score7.c: Likewise. * elf32-sh.c: Likewise. * elf32-sh64.c: Likewise. * elf32-spu.c: Likewise. * elf32-tic6x.c: Likewise. * elf32-tilepro.c: Likewise. * elf32-v850.c: Likewise. * elf32-vax.c: Likewise. * elf32-visium.c: Likewise. * elf32-xstormy16.c: Likewise. * elf32-xtensa.c: Likewise. * elf64-alpha.c: Likewise. * elf64-hppa.c: Likewise. * elf64-ia64-vms.c: Likewise. * elf64-mmix.c: Likewise. * elf64-ppc.c: Likewise. * elf64-s390.c: Likewise. * elf64-sh64.c: Likewise. * elf64-x86-64.c: Likewise. * elflink.c: Likewise. * elfnn-aarch64.c: Likewise. * elfnn-ia64.c: Likewise. * elfxx-mips.c: Likewise. * elfxx-sparc.c: Likewise. * elfxx-tilegx.c: Likewise. * linker.c: Likewise. * pdp11.c: Likewise. * pe-mips.c: Likewise. * reloc.c: Likewise. * reloc16.c: Likewise. * simple.c: Likewise. * vms-alpha.c: Likewise. * xcofflink.c: Likewise. * elf32-rl78.c (get_symbol_value, get_romstart, get_ramstart): Delete status param. Adjust calls to these and linker callbacks throughout. * elf32-rx.c: (get_symbol_value, get_gp, get_romstart, get_ramstart): Delete status param. Adjust calls to these and linker callbacks throughout. ld/ * ldmain.c (multiple_definition, multiple_common, add_to_set, constructor_callback, warning_callback, undefined_symbol, reloc_overflow, reloc_dangerous, unattached_reloc): Return void. * emultempl/elf32.em: Adjust callback calls. gdb/ * compile/compile-object-load.c (link_callbacks_multiple_definition, link_callbacks_warning, link_callbacks_undefined_symbol, link_callbacks_undefined_symbol, link_callbacks_reloc_overflow, link_callbacks_reloc_dangerous, link_callbacks_unattached_reloc): Return void. |
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Jim Wilson
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b7f28d873c |
Enable R_AARCH64_NONE for 64-bit code.
* elfnn-aarch64.c: Unconditionally enable R_AARCH64_NULL and R_AARCH64_NONE. Use HOWTO64 for R_AARCH64_NULL. * relocs.c: Add BFD_RELOC_AARCH64_NULL. * bfd-in2.h: Regenerate. * libbfd.h: Likewise. |
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Andrew Burgess
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4b0c052e45 |
arc/nps400 : New cmem instructions and associated relocation
Add support for arc/nps400 cmem instructions, these load and store instructions are hard-wired to access "0x57f00000 + 16-bit-offset". Supporting this relocation required some additions to the arc relocation handling in the bfd library, as well as the standard changes required to add a new relocation type. There's a test of the new instructions in the assembler, and a test of the relocation in the linker. bfd/ChangeLog: * reloc.c: Add BFD_RELOC_ARC_NPS_CMEM16 entry. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elf32-arc.c: Add 'opcode/arc.h' include. (struct arc_relocation_data): Add symbol_name. (arc_special_overflow_checks): New function. (arc_do_relocation): Use arc_special_overflow_checks, reindent as required, add an extra comment. (elf_arc_relocate_section): Setup symbol_name in reloc_data. gas/ChangeLog: * testsuite/gas/arc/nps400-3.d: New file. * testsuite/gas/arc/nps400-3.s: New file. include/ChangeLog: * elf/arc-reloc.def: Add ARC_NPS_CMEM16 reloc. * opcode/arc.h (NPS_CMEM_HIGH_VALUE): Define. ld/ChangeLog: * testsuite/ld-arc/arc.exp: New file. * testsuite/ld-arc/nps-1.s: New file. * testsuite/ld-arc/nps-1a.d: New file. * testsuite/ld-arc/nps-1b.d: New file. * testsuite/ld-arc/nps-1b.err: New file. opcodes/ChangeLog: * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst instructions. * arc-opc.c (insert_nps_cmem_uimm16): New function. (extract_nps_cmem_uimm16): New function. (arc_operands): Add NPS_XLDST_UIMM16 operand. |
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Dan Gissel
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37b01f6a13 |
Fix some places where octet to byte conversions are needed.
PR 19713 * elf.c (_bfd_elf_section_offset): Ensure that the returned offset uses bytes not octets. * elflink.c (resolve_section): Likewise. Add a bfd parameter. (eval_section): Pass the input_bfd to resolve_section. (bfd_elf_perform_complex_relocation): Convert byte offset to octets before read and writing values. (elf_link_input_bfd): Add byte to octet conversions. (elf_reloc_link_order): Likewise. (elf_fixup_link_order): Likewise. (bfd_elf_final_link): Likewise. * reloc.c (_bfd_final_link_relocate): Likewise. * syms.c (_bfd_stab_section_find_nearest_line): Likewise. |
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Nick Clifton
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737684142b |
Fix a seg-fault in the linker when it encounters a corrupt binary containing a reloc with no associated symbol.
PR ld/19628 * reloc.c (bfd_generic_get_relocated_section_contents): Stop processing if we encounter a reloc without an associated symbol. |
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Alan Modra
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6f2750feaf | Copyright update for binutils | ||
Mickael Guene
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72d98d16ed |
[ARM] Add support for thumb1 pcrop relocations.
To support thumb1 execute-only code we need to support four new relocations (R_ARM_THM_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G2_NC and R_ARM_THM_ALU_ABS_G3_NC). These relocations allow the static linker to finalize construction of symbol address. Typical sequence of code to get address of the symbol foo is then the following : movs r3, #:upper8_15:#foo lsls r3, #8 adds r3, #:upper0_7:#foo lsls r3, #8 adds r3, #:lower8_15:#foo lsls r3, #8 adds r3, #:lower0_7:#foo This will give following sequence of text and relocations after assembly : 4: 2300 movs r3, #0 4: R_ARM_THM_ALU_ABS_G3_NC foo 6: 021b lsls r3, r3, #8 8: 3300 adds r3, #0 8: R_ARM_THM_ALU_ABS_G2_NC foo a: 021b lsls r3, r3, #8 c: 3300 adds r3, #0 c: R_ARM_THM_ALU_ABS_G1_NC foo e: 021b lsls r3, r3, #8 10: 3300 adds r3, #0 10: R_ARM_THM_ALU_ABS_G0_NC foo |
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Alan Modra
|
006589cfa1 |
R_PPC64_ENTRY
Add a new relocation that marks large-model entry code, for edit back to medium-model. include/elf/ * ppc64.h (R_PPC64_ENTRY): Define. bfd/ * reloc.c (BFD_RELOC_PPC64_ENTRY): New. * elf64-ppc.c (reloc_howto_type ppc64_elf_howto_raw): Add entry for R_PPC64_ENTRY. (LD_R2_0R12, ADD_R2_R2_R12, LIS_R2, ADDIS_R2_R12): Define. (ppc64_elf_reloc_type_lookup): Handle R_PPC64_ENTRY. (ppc64_elf_relocate_section): Edit code at R_PPC64_ENTTY. Use new insn defines. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate. |
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Tristan Gingold
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f075eb5e6b |
binutils: add support for arm-*-darwin and aarch64-*-darwin.
Currently only in bfd and binutils. ChangeLog/ * configure.ac: Add aarch64-*-darwin* and arm-*-darwin*. * configure: Regenerate. bfd/ChangeLog/ * targets.c (aarch64_mach_o_vec, arm_mach_o_vec): Declare. (_bfd_target_vector): Add new vectors. * reloc.c (BFD_RELOC_MACH_O_SUBTRACTOR32) (BFD_RELOC_MACH_O_SUBTRACTOR64, BFD_RELOC_MACH_O_ARM64_ADDEND) (BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGE21) (BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGEOFF12) (BFD_RELOC_MACH_O_ARM64_POINTER_TO_GOT): New relocations. (BFD_RELOC_MACH_O_X86_64_SUBTRACTOR32) (BFD_RELOC_MACH_O_X86_64_SUBTRACTOR64): Remove. * mach-o-x86-64.c (bfd_mach_o_x86_64_swap_reloc_out): Change name of subtractor relocations. * config.bfd: Handle aarch64-*-darwin*, arm-*-darwin*. * Makefile.am (BFD32_BACKENDS): Add mach-o-arm.lo. (BFD32_BACKENDS_CFILES): Add mach-o-arm.c. (BFD64_BACKENDS): Add mach-o-aarch64.lo. (BFD64_BACKENDS_CFILES): Add mach-o-aarch64.c. * configure.ac: Handle aarch64_mach_o_vec and arm_mach_o_vec. * mach-o-aarch64.c: New file. * mach-o-arm.c: New file. * Makefile.in: Regenerate. * bfd-in2.h: Regenerate. * configure: Regenerate. * libbfd.h: Regenerate. |
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Peter Bergner
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a680de9a98 |
Add assembler, disassembler and linker support for power9.
include/opcode/
* ppc.h (PPC_OPCODE_POWER9): New define.
(PPC_OPCODE_VSX3): Likewise.
opcodes/
* ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
Add PPC_OPCODE_VSX3 to the vsx entry.
(powerpc_init_dialect): Set default dialect to power9.
* ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
extract_l1 insert_xtq6, extract_xtq6): New static functions.
(insert_esync): Test for illegal L operand value.
(DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
PPCVSX3): New defines.
(powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
<mcrxr>: Use XBFRARB_MASK.
<addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
<doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
<tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
include/elf/
* ppc.h (R_PPC_REL16DX_HA): New reloction.
* ppc64.h (R_PPC64_REL16DX_HA): Likewise.
bfd/
* elf32-ppc.c (ppc_elf_howto_raw): Add R_PPC_REL16DX_HA.
(ppc_elf_reloc_type_lookup): Handle R_PPC_REL16DX_HA.
(ppc_elf_addr16_ha_reloc): Likewise.
(ppc_elf_check_relocs): Likewise.
(ppc_elf_relocate_section): Likewise.
(is_insn_dq_form): Handle lxv and stxv instructions.
* elf64-ppc.c (ppc64_elf_howto_raw): Add R_PPC64_REL16DX_HA.
(ppc64_elf_reloc_type_lookup): Handle R_PPC64_REL16DX_HA.
(ppc64_elf_ha_reloc): Likewise.
(ppc64_elf_check_relocs): Likewise.
(ppc64_elf_relocate_section): Likewise.
* bfd-in2.h: Regenerate.
* libbfd.h: Likewise.
* reloc.c (BFD_RELOC_PPC_REL16DX_HA): New.
elfcpp/
* powerpc.h (R_POWERPC_REL16DX_HA): Define.
gas/
* doc/as.texinfo (Target PowerPC): Document -mpower9 and -mpwr9.
* doc/c-ppc.texi (PowerPC-Opts): Likewise.
* config/tc-ppc.c (md_show_usage): Likewise.
(md_assemble): Handle BFD_RELOC_PPC_REL16DX_HA.
(md_apply_fix): Likewise.
(ppc_handle_align): Handle power9's group ending nop.
gas/testsuite/
* gas/ppc/altivec3.s: New test.
* gas/ppc/altivec3.d: Likewise.
* gas/ppc/vsx3.s: Likewise.
* gas/ppc/vsx3.d: Likewise.
* gas/ppc/power9.s: Likewise.
* gas/ppc/power9.d: Likewise.
* gas/ppc/ppc.exp: Run them.
* gas/ppc/power8.s <lxvx, lxvd2x, stxvx, stxvd2x>: Add new tests.
* gas/ppc/power8.d: Likewise.
* gas/ppc/vsx.s: <lxvx, stxvx>: Rename invalid mnemonics ...
<lxvd2x, stxvd2x>: ...to this.
* gas/ppc/vsx.d: Likewise.
gold/
* gold/powerpc.cc (Powerpc_relocate_functions::addr16_dq): New function.
(Powerpc_relocate_functions::addr16dx_ha): Likewise.
(Target_powerpc::Scan::local): Handle R_POWERPC_REL16DX_HA.
(Target_powerpc::Scan::global): Likewise.
(Target_powerpc::Relocate::relocate): Likewise.
ld/testsuite/
* ld-powerpc/addpcis.d: New test.
* ld-powerpc/addpcis.s: New test.
* ld-powerpc/powerpc.exp: Run it.
|
||
|
Cupertino Miranda
|
6f4b1afcdc |
Fix errors in the gas testsuite for the ARC target.
bfd * reloc.c (BFD_RELOC_ARC_32_PCREL): New entry. (ARC_TLS_DTPOFF): Arrange it in order. * elf32-arc.c (arc_elf_howto_ini): Update formula. (get_middle_endian_relocation): New function. (PDATA): Define. * bfd-in2.h: Regenerate. * libbfd.h: Likewise. elf * arc-reloc.def (ARC_32_PCREL): New definition. gas * config/tc-arc.c (tokenize_arguments): Avoid creating unused symbols when parsing relocation types. (md_apply_fix): Handle TLS relocations. Fix BFD_RELOC_ARC_32_PCREL relocation. (arc_check_reloc): Emit BFD_RELOC_ARC_32_PCREL relocation. |
||
H.J. Lu
|
56ceb5b540 |
Add R_X86_64_[REX_]GOTPCRELX support to gas and ld
This patch adds support for the R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX relocations proposed in https://groups.google.com/forum/#!topic/x86-64-abi/n9AWHogmVY0 to gas and ld. It updates gas to generate R_X86_64_GOTPCRELX, R_X86_64_REX_GOTPCRELX if there is a REX prefix, relocation for memory operand, foo@GOTPCREL(%rip). With the locally defined symbol, foo, we convert mov foo@GOTPCREL(%rip), %reg to lea foo(%rip), %reg and convert call/jmp *foo@GOTPCREL(%rip) to nop call foo/jmp foo nop When PIC is false, convert test %reg, foo@GOTPCREL(%rip) to test $foo, %reg and convert binop foo@GOTPCREL(%rip), %reg to binop $foo, %reg where binop is one of adc, add, and, cmp, or, sbb, sub, xor instructions. bfd/ * elf64-x86-64.c: Include opcode/i386.h. (x86_64_elf_howto_table): Add R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX. (R_X86_64_standard): Replace R_X86_64_PLT32_BND with R_X86_64_REX_GOTPCRELX. (x86_64_reloc_map): Add BFD_RELOC_X86_64_GOTPCRELX and BFD_RELOC_X86_64_REX_GOTPCRELX. (need_convert_mov_to_lea): Renamed to ... (need_convert_load): This. (elf_x86_64_check_relocs): Handle R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX. Replace need_convert_mov_to_lea with need_convert_load. (elf_x86_64_gc_sweep_hook): Handle R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX. (elf_x86_64_size_dynamic_sections): Likewise. (elf_x86_64_relocate_section): Likewise. (elf_x86_64_convert_mov_to_lea): Renamed to ... (elf_x86_64_convert_load): This. Replace need_convert_mov_to_lea with need_convert_load. Support R_X86_64_GOTPCRELX and R_X86_64_REX_GOTPCRELX transformations. * reloc.c (BFD_RELOC_X86_64_GOTPCRELX): New. (BFD_RELOC_X86_64_REX_GOTPCRELX): Likewise. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. gas/ * config/tc-i386.c (tc_i386_fix_adjustable): Handle BFD_RELOC_X86_64_GOTPCRELX and BFD_RELOC_X86_64_REX_GOTPCRELX. (tc_gen_reloc): Likewise. (i386_validate_fix): Generate BFD_RELOC_X86_64_GOTPCRELX or BFD_RELOC_X86_64_REX_GOTPCRELX if fx_tcbit2 is set. * config/tc-i386.h (TC_FORCE_RELOCATION_LOCAL): Also return true for BFD_RELOC_X86_64_GOTPCRELX and BFD_RELOC_X86_64_REX_GOTPCRELX. gas/testsuite/ * gas/i386/i386.exp: Run x86-64-gotpcrel. * gas/i386/x86-64-gotpcrel.d: New file. * gas/i386/x86-64-gotpcrel.s: Likewise. * gas/i386/ilp32/x86-64-gotpcrel.d: Likewise. * gas/i386/x86-64-localpic.d: Replace R_X86_64_GOTPCREL with R_X86_64_REX_GOTPCRELX. * gas/i386/ilp32/x86-64-localpic.d: Likewise. include/elf/ * x86-64.h (R_X86_64_GOTPCRELX): New. (R_X86_64_REX_GOTPCRELX): Likewise. ld/testsuite/ * ld-ifunc/ifunc-5r-local-x86-64.d: Replace R_X86_64_GOTPCREL with R_X86_64_REX_GOTPCRELX. * ld-x86-64/plt-main1.rd: Likewise. * ld-x86-64/plt-main3.rd: Likewise. * ld-x86-64/plt-main4.rd: Likewise. * ld-x86-64/gotpcrel1.dd: New file. * ld-x86-64/gotpcrel1.out: Likewise. * ld-x86-64/gotpcrel1a.S: Likewise. * ld-x86-64/gotpcrel1b.c: Likewise. * ld-x86-64/gotpcrel1c.c: Likewise. * ld-x86-64/gotpcrel1d.S: Likewise. * ld-x86-64/load1.s: Likewise. * ld-x86-64/load1a.d: Likewise. * ld-x86-64/load1b.d: Likewise. * ld-x86-64/load1c.d: Likewise. * ld-x86-64/load1d.d: Likewise. * ld-x86-64/x86-64.exp: Run load1a, load1b, load1c and load1d tests. Run gotpcrel1 test. |
||
|
H.J. Lu
|
02a866936d |
Add R_386_GOT32X support to gas and ld
This patch adds support for the R_386_GOT32X relocation proposed in https://groups.google.com/forum/#!topic/ia32-abi/GbJJskkid4I to gas and ld. It updates gas to generate R_386_GOT32X relocation for memory operand, foo@GOT[(%reg)]. We must encode "mov foo@GOT, %eax" with the 0x8b opcode, instead of the 0xb8 opcode, so that it can be transformed to "lea foo, %eax". With the locally defined symbol, foo, we convert mov foo@GOT[(%reg1)], %reg2 to lea foo[@GOTOFF(%reg1)], %reg2 and convert call/jmp *foo@GOT[(%reg)] to nop call foo/jmp foo nop When PIC is false, convert test %reg1, foo@GOT[(%reg2)] to test $foo, %reg1 and convert binop foo@GOT[(%reg1)], %reg2 to binop $foo, %reg2 where binop is one of adc, add, and, cmp, or, sbb, sub, xor instructions. bfd/ * elf32-i386.c: Include opcode/i386.h. (elf_howto_table): Add R_386_GOT32X. (R_386_ext2): Replace R_386_IRELATIVE with R_386_GOT32X. (elf_i386_reloc_type_lookup): Handle BFD_RELOC_386_GOT32X. (need_convert_mov_to_lea): Renamed to ... (need_convert_load): This. (elf_i386_check_relocs): Handle R_386_GOT32X. Replace need_convert_mov_to_lea with need_convert_load. (elf_i386_gc_sweep_hook): Handle R_386_GOT32X. (elf_i386_size_dynamic_sections): Likewise. (elf_i386_relocate_section): Likewise. (elf_i386_convert_mov_to_lea): Renamed to ... (elf_i386_convert_load): This. Replace need_convert_mov_to_lea with need_convert_load. Support R_386_GOT32X transformations. * reloc.c (BFD_RELOC_386_GOT32X): New. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. gas/ * config/tc-i386.c (tc_i386_fix_adjustable): Handle BFD_RELOC_386_GOT32X. (tc_gen_reloc): Likewise. (match_template): Force 0x8b encoding for "mov foo@GOT, %eax". (output_disp): Check for "call/jmp *mem", "mov mem, %reg", "test %reg, mem" and "binop mem, %reg" where binop is one of adc, add, and, cmp, or, sbb, sub, xor instructions. Set fx_tcbit if the REX prefix is generated. Set fx_tcbit2 if BFD_RELOC_386_GOT32X should be generated. (i386_validate_fix): Generate BFD_RELOC_386_GOT32X if fx_tcbit2 is set. gas/testsuite/ * gas/i386/got.d: New file. * gas/i386/got.s: Likewise. * gas/i386/i386.exp: Run got. * gas/i386/localpic.d: Replace R_386_GOT32 with R_386_GOT32X. * gas/i386/mixed-mode-reloc32.d: Likewise. * gas/i386/reloc32.d: Likewise. include/elf/ * i386.h (R_386_GOT32X): New relocation. ld/testsuite/ * ld-i386/branch1.d: New file. * ld-i386/branch1.s: Likewise. * ld-i386/call1.d: Likewise. * ld-i386/call1.s: Likewise. * ld-i386/call2.d: Likewise. * ld-i386/call2.s: Likewise. * ld-i386/got1.dd: Likewise. * ld-i386/got1.out: Likewise. * ld-i386/got1a.S: Likewise. * ld-i386/got1b.c: Likewise. * ld-i386/got1c.c: Likewise. * ld-i386/got1d.S: Likewise. * ld-i386/jmp1.d: Likewise. * ld-i386/jmp1.s: Likewise. * ld-i386/jmp2.d: Likewise. * ld-i386/jmp2.s: Likewise. * ld-i386/load1.d: Likewise. * ld-i386/load1.s: Likewise. * ld-i386/load2.d: Likewise. * ld-i386/load2.s: Likewise. * ld-i386/load3.d: Likewise. * ld-i386/load3.s: Likewise. * ld-i386/load4.s: Likewise. * ld-i386/load4a.d: Likewise. * ld-i386/load4b.d: Likewise. * ld-i386/load5.s: Likewise. * ld-i386/load5a.d: Likewise. * ld-i386/load5b.d: Likewise. * ld-i386/load6.d: Likewise. * ld-i386/load6.s: Likewise. * ld-i386/i386.exp: Run branch1, call1, call2, jmp1, jmp2, load1, load2, load3, load4a, load4b, load5a, load5b and load6 tests. Run got1 test. |
||
|
Nick Clifton
|
886a250647 |
New ARC implementation.
bfd * archures.c: Remove support for older ARC. Added support for new
ARC cpus (ARC600, ARC601, ARC700, ARCV2).
* bfd-in2.h: Likewise.
* config.bfd: Likewise.
* cpu-arc.c: Likewise.
* elf32-arc.c: Totally changed file with a refactored
inplementation of the ARC port.
* libbfd.h: Added ARC specific relocation types.
* reloc.c: Likewise.
gas * config/tc-arc.c: Revamped file for ARC support.
* config/tc-arc.h: Likewise.
* doc/as.texinfo: Add new ARC options.
* doc/c-arc.texi: Likewise.
ld * configure.tgt: Added target arc-*-elf* and arc*-*-linux-uclibc*.
* emulparams/arcebelf_prof.sh: New file
* emulparams/arcebelf.sh: Likewise.
* emulparams/arceblinux_prof.sh: Likewise.
* emulparams/arceblinux.sh: Likewise.
* emulparams/arcelf_prof.sh: Likewise.
* emulparams/arcelf.sh: Likewise.
* emulparams/arclinux_prof.sh: Likewise.
* emulparams/arclinux.sh: Likewise.
* emulparams/arcv2elfx.sh: Likewise.
* emulparams/arcv2elf.sh: Likewise.
* emultempl/arclinux.em: Likewise.
* scripttempl/arclinux.sc: Likewise.
* scripttempl/elfarc.sc: Likewise.
* scripttempl/elfarcv2.sc: Likewise
* Makefile.am: Add new ARC emulations.
* Makefile.in: Regenerate.
* NEWS: Mention the new feature.
opcodes * arc-dis.c: Revamped file for ARC support
* arc-dis.h: Likewise.
* arc-ext.c: Likewise.
* arc-ext.h: Likewise.
* arc-opc.c: Likewise.
* arc-fxi.h: New file.
* arc-regs.h: Likewise.
* arc-tbl.h: Likewise.
binutils * readelf.c (get_machine_name): Remove A5 reference. Add ARCompact
and ARCv2.
(get_machine_flags): Handle EM_ARCV2 and EM_ARCOMPACT.
(guess_is_rela): Likewise.
(dump_relocations): Likewise.
(is_32bit_abs_reloc): Likewise.
(is_16bit_abs_reloc): Likewise.
(is_none_reloc): Likewise.
* NEWS: Mention the new feature.
include * dis-asm.h (arc_get_disassembler): Correct declaration.
* arc-reloc.def: Macro file with definition of all relocation
types.
* arc.h: Changed macros for the newly supported ARC cpus. Altered
enum defining the supported relocations.
* common.h: Changed EM_ARC_A5 definition to EM_ARC_COMPACT. Added
macro for EM_ARC_COMPACT2.
* arc-func.h: New file.
* arc.h: Likewise.
|
||
Renlin Li
|
3b957e5b07 |
[Binutils][AARCH64]Add TLS IE large memory support.
bfd/ 2015-10-02 Renlin Li <renlin.li@arm.com> * reloc.c: Make AARCH64_TLSIE_MOVW_GOTTPREL_G1 and AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC defined in alphabetical order. * libbfd.h: Regenerate. * bfd-in2.h: Likewise. * elfnn-aarch64.c (elfNN_aarch64_howto_table): Make TLSIE_MOVW_GOTTPREL_G1 check overflow. (aarch64_reloc_got_type): Add support for TLSIE_MOVW_GOTTPREL_G1 and TLSIE_MOVW_GOTTPREL_G0_NC. (elfNN_aarch64_final_link_relocate): Likewise. (elfNN_aarch64_relocate_section): Likewise. (elfNN_aarch64_gc_sweep_hook): Likewise. (elfNN_aarch64_check_relocs): Likewise. * elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Likewise. (_bfd_aarch64_elf_resolve_relocation): Likewise. gas/ 2015-10-02 Renlin Li <renlin.li@arm.com> * config/tc-aarch64.c (reloc_table): Add two entries for gottprel_g0_nc and gottprel_g1. (process_movw_reloc_info): Add support. (md_apply_fix): Likewise. (aarch64_force_relocation): Likewise. gas/testsuite/ 2015-10-02 Renlin Li <renlin.li@arm.com> * gas/aarch64/reloc-gottprel_g0_nc.d: New. * gas/aarch64/reloc-gottprel_g0_nc.s: New. * gas/aarch64/reloc-gottprel_g1.d: New. * gas/aarch64/reloc-gottprel_g1.s: New. ld/testsuite/ 2015-10-02 Renlin Li <renlin.li@arm.com> * ld-aarch64/tls-large-ie.d: New. * ld-aarch64/tls-large-ie.s: New. * ld-aarch64/aarch64-elf.exp: Run new test. |
||
|
Renlin Li
|
3e8286c0d2 |
[GAS][AARCH64]Add BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC support.
bfd/ 2015-10-02 Renlin Li <renlin.li@arm.com> * reloc.c (BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC): New entry. * elfnn-aarch64.c (elfNN_aarch64_howto_table): New entry for BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC. * libbfd.h: Regenerate. * bfd-in2.h: Likewise gas/ 2015-10-02 Renlin Li <renlin.li@arm.com> * config/tc-aarch64.c (reloc_table): New relocation modifier tlsgd_g0_nc. (process_movw_reloc_info): Support BFD_RELOC_AARCH64_TLSGD_MOVW_G1. (md_apply_fix): Likewise. (aarch64_force_relocation): Likewise. gas/testsuite/ 2015-10-02 Renlin Li <renlin.li@arm.com> * gas/aarch64/reloc-tlsgd_g0_nc.d: New. * gas/aarch64/reloc-tlsgd_g0_nc.s: New. |
||
|
Renlin Li
|
1aa66fb152 |
[GAS][AARCH64]Add BFD_RELOC_AARCH64_TLSGD_MOVW_G1 support.
bfd/ 2015-10-02 Renlin Li <renlin.li@arm.com> * reloc.c (BFD_RELOC_AARCH64_TLSGD_MOVW_G1): New entry. * elfnn-aarch64.c (elfNN_aarch64_howto_table): New entry for BFD_RELOC_AARCH64_TLSGD_MOVW_G1. * bfd-in2.h: Regenerate. * libbfd.h: Likewise. gas/ 2015-10-02 Renlin Li <renlin.li@arm.com> * config/tc-aarch64.c (reloc_table): New relocation modifier tlsgd_g1. (process_movw_reloc_info): Support BFD_RELOC_AARCH64_TLSGD_MOVW_G1. (md_apply_fix): Likewise. (aarch64_force_relocation): Likewise. gas/testsuite/ 2015-10-02 Renlin Li <renlin.li@arm.com> * gas/aarch64/reloc-tlsgd_g1.s: New. * gas/aarch64/reloc-tlsgd_g1.s: New. |
||
|
Renlin Li
|
ca632371ce |
[GAS][AARCH64]Add BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC Support.
bfd/ 2015-10-02 Renlin Li <renlin.li@arm.com> * reloc.c (BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC): New. * elfnn-aarch64.c (elfNN_aarch64_howto_table): New entry MOVW_GOTOFF_G0_NC. * libbfd.h: Regnerate. * bfd-in2.h: Regenerate. gas/ 2015-10-02 Renlin Li <renlin.li@arm.com> * config/tc-aarch64.c (reloc_table): New relocation modifier gotoff_g0_nc. (process_movw_reloc_info): Support gotoff_g0_nc. (md_apply_fix): Likewise. gas/testsuite/ 2015-10-02 Renlin Li <renlin.li@arm.com> * gas/aarch64/reloc-gotoff_g0_nc.s: New. * gas/aarch64/reloc-gotoff_g0_nc.d: New. |
||
|
Renlin Li
|
654248e7f7 |
[GAS][AARCH64]Add BFD_RELOC_AARCH64_MOVW_GOTOFF_G1 Support.
bfd/ 2015-10-02 Renlin Li <renlin.li@arm.com> * reloc.c (BFD_RELOC_AARCH64_MOVW_GOTOFF_G1): New. * elfnn-aarch64.c (elfNN_aarch64_howto_table): New entry for MOVW_GOTOFF_G1. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate. gas/ 2015-10-02 Renlin Li <renlin.li@arm.com> * config/tc-aarch64.c (reloc_table): New relocation modifier gotoff_g1. (process_movw_reloc_info): Support newly added modifier. (md_apply_fix): Likewise. gas/testsuite/ 2015-10-02 Renlin Li <renlin.li@arm.com> * gas/aarch64/reloc-gotoff_g1.s: New. * gas/aarch64/reloc-gotoff_g1.d: New. |
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|
Renlin Li
|
7c2bea1ad1 |
[AArch64] Fix a typo in the comment for BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
2015-08-25 Renlin Li <renlin.li@arm.com> bfd/ * reloc.c (BFD_RELOC_AARCH64_LD64_GOTOFF_LO15): Use LP64 instead of ILP64. * bfd-in2.h: Regenerate. |
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Jiong Wang
|
4c5625238c |
[AArch64][5/6] GAS support TLSLD load/store relocation types
2015-08-19 Jiong Wang <jiong.wang@arm.com> bfd/ * reloc.c: New entries, including BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC, BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC, BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC. BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC. * elfnn-aarch64.c (elfNN_aarch64_howto_table): Likewise. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas/ * config/tc-aarch64.c (reloc_table): New relocation types support for dtprel_lo12. (ldst_lo12_determine_real_reloc_type): Support BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC, BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC, BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC, BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC. (parse_operands): Likewise. (md_apply_fix): Likewise (aarch64_force_relocation): Likewise. (process_movw_reloc_info): Likewise. gas/testsuite/ * gas/aarch64/reloc-dtprel_lo12-ldst8.s: New testcase. * gas/aarch64/reloc-dtprel_lo12_nc-ldstc.s: Likewise. * gas/aarch64/reloc-dtprel_lo12-ldst16.s: Likewise. * gas/aarch64/reloc-dtprel_lo12_nc-ldst16.s: Likewise. * gas/aarch64/reloc-dtprel_lo12-ldst32.s: Likewise. * gas/aarch64/reloc-dtprel_lo12_nc-ldst32.s: Likewise. * gas/aarch64/reloc-dtprel_lo12-ldst64.s: Likewise. * gas/aarch64/reloc-dtprel_lo12_nc-ldst64.s: Likewise. * gas/aarch64/reloc-dtprel_lo12-ldst8.d: New expectation file. * gas/aarch64/reloc-dtprel_lo12_nc-ldst8.d: Likewise. * gas/aarch64/reloc-dtprel_lo12-ldst16.d: Likewise. * gas/aarch64/reloc-dtprel_lo12_nc-ldst16.d: Likewise. * gas/aarch64/reloc-dtprel_lo12-ldst32.d: Likewise. * gas/aarch64/reloc-dtprel_lo12_nc-ldst32.d: Likewise. * gas/aarch64/reloc-dtprel-lo12-ldst64.d: Likewise. * gas/aarch64/reloc-dtprel_lo12_nc-ldst64.d: Likewise. |
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|
Jiong Wang
|
49df5539f9 |
[AArch64][3/6] GAS support TLSLD move/add relocation types
2015-08-19 Jiong Wang <jiong.wang@arm.com> bfd/ * reloc.c (BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12, BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0, BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC, BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1, BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC, BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2): New entries. * elfnn-aarch64.c (elfNN_aarch64_howto_table): Likewise. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas/ * config/tc-aarch64.c (reloc_table): New relocation modifiers, "dtprel_hi12", "dtprel_g0", "dtprel_g0_nc", "dtprel_g1", "dtprel_g1_nc", "dtprel_g2". (md_apply_fix): Support new relocation types. (aarch64_force_relocation): Likewise. (process_movw_reloc_info): Likewise. gas/testsuite/ * gas/aarch64/reloc-dtprel_g0.s: New testcase. * gas/aarch64/reloc-dtprel_g0-ilp32.s: Likewise. * gas/aarch64/reloc-dtprel_g0_nc.s: Likewise. * gas/aarch64/reloc-dtprel_g0_nc-ilp32.s: Likewise. * gas/aarch64/reloc-dtprel_g1.s: Likewise. * gas/aarch64/reloc-dtprel_g1-ilp32.s: Likewise. * gas/aarch64/reloc-dtprel_g1_nc.s: Likewise. * gas/aarch64/reloc-dtprel_g2.s: Likewise. * gas/aarch64/reloc-dtprel_hi12.s: Likewise. * gas/aarch64/reloc-dtprel_hi12-ilp32.s: Likewise. * gas/aarch64/reloc-dtprel_g0.d: New expectation file. * gas/aarch64/reloc-dtprel_g0-ilp32.d: Likewise. * gas/aarch64/reloc-dtprel_g0_nc.d: Likewise. * gas/aarch64/reloc-dtprel_g0_nc-ilp32.d: Likewise. * gas/aarch64/reloc-dtprel_g1.d: Likewise. * gas/aarch64/reloc-dtprel_g1-ilp32.d: Likewise. * gas/aarch64/reloc-dtprel_g1_nc.d: Likewise. * gas/aarch64/reloc-dtprel_g2.d: Likewise. * gas/aarch64/reloc-dtprel_hi12.d: Likewise. * gas/aarch64/reloc-dtprel_hi12-ilp32.d: Likewise. |
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Jiong Wang
|
13289c10e2 |
[AArch64][1/6] GAS support BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
2015-08-19 Jiong Wang <jiong.wang@arm.com> bfd/ * reloc.c (BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC): New entry. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elfnn-aarch64.c (elfNN_aarch64_howto_table): New entry for BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC. gas/ * config/tc-aarch64.c (reloc_table): New relocation modifiers. (md_apply_fix): Support BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC. (aarch64_force_relocation): Likewise. gas/testsuite/ * gas/aarch64/reloc-dtprel_lo12_nc.s: New testcase. * gas/aarch64/reloc-dtprel_lo12_nc-ilp32.s: Likewise. * gas/aarch64/reloc-dtprel_lo12_nc.d: New expectation file. * gas/aarch64/reloc-dtprel_lo12_nc-ilp32.d: Likewise. |
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H.J. Lu
|
0e1862bb40 |
Add output_type to bfd_link_info
The "shared" field in bfd_link_info is set for both DSO and and PIE.
There are separate fields for executable and relocatable outputs. This
patch adds an "output_type" field:
enum output_type
{
type_unknown = 0,
type_executable,
type_dll,
type_relocatable
};
and a "pic" field to bfd_link_info to replace shared, executable and
relocatable fields so that we can use the "output_type" field to check
for output type and the "pic" field check if output is PIC. Macros,
bfd_link_executable, bfd_link_dll, bfd_link_relocatable, bfd_link_pic
and bfd_link_pie, are provided to check for output features.
bfd/
* bfd/aoutx.h: Replace shared, executable, relocatable and pie
fields with bfd_link_executable, bfd_link_dll,
bfd_link_relocatable, bfd_link_pic and bfd_link_pie.
* bfd/bout.c: Likewise.
* bfd/coff-alpha.c: Likewise.
* bfd/coff-arm.c: Likewise.
* bfd/coff-i386.c: Likewise.
* bfd/coff-i960.c: Likewise.
* bfd/coff-m68k.c: Likewise.
* bfd/coff-mcore.c: Likewise.
* bfd/coff-mips.c: Likewise.
* bfd/coff-ppc.c: Likewise.
* bfd/coff-rs6000.c: Likewise.
* bfd/coff-sh.c: Likewise.
* bfd/coff-tic80.c: Likewise.
* bfd/coff-x86_64.c: Likewise.
* bfd/coff64-rs6000.c: Likewise.
* bfd/coffgen.c: Likewise.
* bfd/cofflink.c: Likewise.
* bfd/ecoff.c: Likewise.
* bfd/ecofflink.c: Likewise.
* bfd/elf-bfd.h: Likewise.
* bfd/elf-eh-frame.c: Likewise.
* bfd/elf-ifunc.c: Likewise.
* bfd/elf-m10200.c: Likewise.
* bfd/elf-m10300.c: Likewise.
* bfd/elf-s390-common.c: Likewise.
* bfd/elf-vxworks.c: Likewise.
* bfd/elf.c: Likewise.
* bfd/elf32-arm.c: Likewise.
* bfd/elf32-avr.c: Likewise.
* bfd/elf32-bfin.c: Likewise.
* bfd/elf32-cr16.c: Likewise.
* bfd/elf32-cr16c.c: Likewise.
* bfd/elf32-cris.c: Likewise.
* bfd/elf32-crx.c: Likewise.
* bfd/elf32-d10v.c: Likewise.
* bfd/elf32-dlx.c: Likewise.
* bfd/elf32-epiphany.c: Likewise.
* bfd/elf32-fr30.c: Likewise.
* bfd/elf32-frv.c: Likewise.
* bfd/elf32-ft32.c: Likewise.
* bfd/elf32-h8300.c: Likewise.
* bfd/elf32-hppa.c: Likewise.
* bfd/elf32-i370.c: Likewise.
* bfd/elf32-i386.c: Likewise.
* bfd/elf32-i860.c: Likewise.
* bfd/elf32-ip2k.c: Likewise.
* bfd/elf32-iq2000.c: Likewise.
* bfd/elf32-lm32.c: Likewise.
* bfd/elf32-m32c.c: Likewise.
* bfd/elf32-m32r.c: Likewise.
* bfd/elf32-m68hc11.c: Likewise.
* bfd/elf32-m68hc1x.c: Likewise.
* bfd/elf32-m68k.c: Likewise.
* bfd/elf32-mcore.c: Likewise.
* bfd/elf32-mep.c: Likewise.
* bfd/elf32-metag.c: Likewise.
* bfd/elf32-microblaze.c: Likewise.
* bfd/elf32-moxie.c: Likewise.
* bfd/elf32-msp430.c: Likewise.
* bfd/elf32-mt.c: Likewise.
* bfd/elf32-nds32.c: Likewise.
* bfd/elf32-nios2.c: Likewise.
* bfd/elf32-or1k.c: Likewise.
* bfd/elf32-ppc.c: Likewise.
* bfd/elf32-rl78.c: Likewise.
* bfd/elf32-rx.c: Likewise.
* bfd/elf32-s390.c: Likewise.
* bfd/elf32-score.c: Likewise.
* bfd/elf32-score7.c: Likewise.
* bfd/elf32-sh-symbian.c: Likewise.
* bfd/elf32-sh.c: Likewise.
* bfd/elf32-sh64.c: Likewise.
* bfd/elf32-spu.c: Likewise.
* bfd/elf32-tic6x.c: Likewise.
* bfd/elf32-tilepro.c: Likewise.
* bfd/elf32-v850.c: Likewise.
* bfd/elf32-vax.c: Likewise.
* bfd/elf32-visium.c: Likewise.
* bfd/elf32-xc16x.c: Likewise.
* bfd/elf32-xstormy16.c: Likewise.
* bfd/elf32-xtensa.c: Likewise.
* bfd/elf64-alpha.c: Likewise.
* bfd/elf64-hppa.c: Likewise.
* bfd/elf64-ia64-vms.c: Likewise.
* bfd/elf64-mmix.c: Likewise.
* bfd/elf64-ppc.c: Likewise.
* bfd/elf64-s390.c: Likewise.
* bfd/elf64-sh64.c: Likewise.
* bfd/elf64-x86-64.c: Likewise.
* bfd/elflink.c: Likewise.
* bfd/elfnn-aarch64.c: Likewise.
* bfd/elfnn-ia64.c: Likewise.
* bfd/elfxx-mips.c: Likewise.
* bfd/elfxx-sparc.c: Likewise.
* bfd/elfxx-tilegx.c: Likewise.
* bfd/i386linux.c: Likewise.
* bfd/linker.c: Likewise.
* bfd/m68klinux.c: Likewise.
* bfd/pdp11.c: Likewise.
* bfd/pe-mips.c: Likewise.
* bfd/peXXigen.c: Likewise.
* bfd/reloc.c: Likewise.
* bfd/reloc16.c: Likewise.
* bfd/sparclinux.c: Likewise.
* bfd/sunos.c: Likewise.
* bfd/vms-alpha.c: Likewise.
* bfd/xcofflink.c: Likewise.
include/
* include/bfdlink.h (output_type): New enum.
(bfd_link_executable): New macro.
(bfd_link_dll): Likewise.
(bfd_link_relocatable): Likewise.
(bfd_link_pic): Likewise.
(bfd_link_pie): Likewise.
(bfd_link_info): Remove shared, executable, pie and relocatable.
Add output_type and pic.
ld/
* ld/ldctor.c: Replace shared, executable, relocatable and pie
fields with bfd_link_executable, bfd_link_dll,
bfd_link_relocatable, bfd_link_pic and bfd_link_pie.
* ld/ldemul.c: Likewise.
* ld/ldfile.c: Likewise.
* ld/ldlang.c: Likewise.
* ld/ldmain.c: Likewise.
* ld/ldwrite.c: Likewise.
* ld/lexsup.c: Likewise.
* ld/pe-dll.c: Likewise.
* ld/plugin.c: Likewise.
* ld/emultempl/aarch64elf.em: Likewise.
* ld/emultempl/aix.em: Likewise.
* ld/emultempl/alphaelf.em: Likewise.
* ld/emultempl/armcoff.em: Likewise.
* ld/emultempl/armelf.em: Likewise.
* ld/emultempl/avrelf.em: Likewise.
* ld/emultempl/beos.em: Likewise.
* ld/emultempl/cr16elf.em: Likewise.
* ld/emultempl/elf-generic.em: Likewise.
* ld/emultempl/elf32.em: Likewise.
* ld/emultempl/genelf.em: Likewise.
* ld/emultempl/generic.em: Likewise.
* ld/emultempl/gld960.em: Likewise.
* ld/emultempl/gld960c.em: Likewise.
* ld/emultempl/hppaelf.em: Likewise.
* ld/emultempl/irix.em: Likewise.
* ld/emultempl/linux.em: Likewise.
* ld/emultempl/lnk960.em: Likewise.
* ld/emultempl/m68hc1xelf.em: Likewise.
* ld/emultempl/m68kcoff.em: Likewise.
* ld/emultempl/m68kelf.em: Likewise.
* ld/emultempl/metagelf.em: Likewise.
* ld/emultempl/mipself.em: Likewise.
* ld/emultempl/mmo.em: Likewise.
* ld/emultempl/msp430.em: Likewise.
* ld/emultempl/nds32elf.em: Likewise.
* ld/emultempl/needrelax.em: Likewise.
* ld/emultempl/nios2elf.em: Likewise.
* ld/emultempl/pe.em: Likewise.
* ld/emultempl/pep.em: Likewise.
* ld/emultempl/ppc32elf.em: Likewise.
* ld/emultempl/ppc64elf.em: Likewise.
* ld/emultempl/sh64elf.em: Likewise.
* ld/emultempl/solaris2.em: Likewise.
* ld/emultempl/spuelf.em: Likewise.
* ld/emultempl/sunos.em: Likewise.
* ld/emultempl/tic6xdsbt.em: Likewise.
* ld/emultempl/ticoff.em: Likewise.
* ld/emultempl/v850elf.em: Likewise.
* ld/emultempl/vms.em: Likewise.
* ld/emultempl/vxworks.em: Likewise.
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|
Jiong Wang
|
70151fb54a |
[AArch64][7/8] GAS support BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
2015-08-11 Jiong Wang <jiong.wang@arm.com> include/elf/ * aarch64.h (R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12): Define. bfd/ * reloc.c (BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12): New entry. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elfnn-aarch64.c (elfNN_aarch64_howto_table): New entry for BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12. gas/ * config/tc-aarch64.c (reloc_table): New relocation modifiers "dtprel_lo12". (md_apply_fix): Support BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12. (aarch64_force_relocation): Likewise. gas/testsuite/ * gas/aarch64/reloc-dtprel_lo12-1.s: New testcase. * gas/aarch64/reloc-dtprel_lo12-ilp32-1.s: Likewise. * gas/aarch64/reloc-dtprel_lo12-1.d: New expectation file. * gas/aarch64/reloc-dtprel_lo12-ilp32-1.d: Likewise. |
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|
Jiong Wang
|
a12fad50d2 |
[AArch64][5/8] GAS support BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
2015-08-11 Jiong Wang <jiong.wang@arm.com> bfd/ * reloc.c (BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC): New entry. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elfnn-aarch64.c (elfNN_aarch64_howto_table): New entry for BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC. gas/ * config/tc-aarch64.c (reloc_table): New relocation modifiers. (md_apply_fix): Support BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC. (aarch64_force_relocation): Likewise. gas/testsuite/ * gas/aarch64/reloc-tlsldm_lo12_nc-1.s: New testcase. * gas/aarch64/reloc-tlsldm_lo12_nc-ilp32-1.s: Likewise. * gas/aarch64/reloc-tlsldm_lo12_nc-1.d: New expectation file. * gas/aarch64/reloc-tlsldm_lo12_nc-ilp32-1.d: Likewise. |
||
|
Jiong Wang
|
1107e076cf |
[AArch64][2/8] GAS support BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
2015-08-11 Jiong Wang <jiong.wang@arm.com> bfd/ * reloc.c (BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21): New entry. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elfnn-aarch64.c (elfNN_aarch64_howto_table): New entry for BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21. gas/ * config/tc-aarch64.c (reloc_table): New relocation modifiers. (md_apply_fix): Support BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21. (aarch64_force_relocation): Likewise. gas/testsuite/ * gas/aarch64/reloc-tlsldm-page-1.s: New testcase. * gas/aarch64/reloc-tlsldm-page-ilp32-1.s: Likewise. * gas/aarch64/reloc-tlsldm-page-1.d: New expectation file. * gas/aarch64/reloc-tlsldm-page-ilp32-1.d: Likewise. |
||
|
Jiong Wang
|
6c37fedc41 | [AArch64][2/3] GAS support BFD_RELOC_AARCH64_TLSLD_ADR_PREL21 | ||
Sandra Loosemore
|
8c163c5a87 |
Relocations for Nios II R2
2015-07-01 Sandra Loosemore <sandra@codesourcery.com> Cesar Philippidis <cesar@codesourcery.com> bfd/ * bfd-in2.h: Regenerated. * elf32-nios2.c (elf_nios2_howto_table_rel): Rename to... (elf_nios2_r1_howto_table_rel): This. (elf_nios2_r2_howto_table_rel): New. (BFD_IS_R2): New. (lookup_howto): Add ABFD parameter. Adjust to look up in either the R1 or R2 relocation table, as determined by ABFD. (nios2_reloc_map): Add R2 relocations. (nios2_elf32_bfd_reloc_type_lookup): Do lookup using lookup_howto. Pass it the ABFD parameter. (nios2_elf32_bfd_reloc_name_lookup): Use ABFD to decide whether to return an R1 or R2 relocation. (nios2_elf32_info_to_howto): Do lookup using lookup_howto. Pass it the ABFD parameter. (nios2_elf32_do_call26_relocate): Check for alignment on a 4-byte boundary. (nios2_elf32_relocate_section): Adjust call to lookup_howto. * libbfd.h: Regenerated. * reloc.c (BFD_RELOC_NIOS2_R2_S12): New. (BFD_RELOC_NIOS2_R2_I10_1_PCREL): New. (BFD_RELOC_NIOS2_R2_T1I7_1_PCREL): New. (BFD_RELOC_NIOS2_R2_T1I7_2): New. (BFD_RELOC_NIOS2_R2_T2I4): New. (BFD_RELOC_NIOS2_R2_T2I4_1): New. (BFD_RELOC_NIOS2_R2_T2I4_2): New. (BFD_RELOC_NIOS2_R2_X1I7_2): New. (BFD_RELOC_NIOS2_R2_X2L5): New. (BFD_RELOC_NIOS2_R2_F1I5_2): New. (BFD_RELOC_NIOS2_R2_L5I4X1): New. (BFD_RELOC_NIOS2_R2_T1X1I6): New. (BFD_RELOC_NIOS2_R2_T1X1I6_2): New. include/elf/ * nios2.h (R_NIOS2_R2_S12): New. (R_NIOS2_R2_I10_1_PCREL): New. (R_NIOS2_R2_T1I7_1_PCREL): New. (R_NIOS2_R2_T1I7_2): New. (R_NIOS2_R2_T2I4): New. (R_NIOS2_R2_T2I4_1): New. (R_NIOS2_R2_T2I4_2): New. (R_NIOS2_R2_X1I7_2): New. (R_NIOS2_R2_X2L5): New. (R_NIOS2_R2_F1I5_2): New. (R_NIOS2_R2_L5I4X1): New. (R_NIOS2_R2_T1X1I6): New. (R_NIOS2_R2_T1X1I6_2): New. (R_NIOS2_ILLEGAL): Renumber. |
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|
Nick Clifton
|
54f66250d7 |
Add support for SADDR addressing to the RL78 port.
gas * config/rl78-parse.y: Tag all saddr expressions throughout.
(SET_SA): New.
(expr_is_saddr): Allow symbolic expressions.
* config/tc-rl78.c (md_apply_fix): Handle SADDR.
bfd * elf32-rl78.c (rl78_elf_howto_table): Add RH_SADDR.
(rl78_reloc_map): Add R_RL78_RH_SADDR.
* reloc.c: Add BFD_RELOC_RL78_SADDR.
* libbfd.h: Regenerate.
* bfd-in2.h: Regenerate.
|
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|
Renlin Li
|
87f5fbcc7a |
[AArch64] Gas add BFD_RELOC_AARCH64_LD64_GOTOFF_LO15 support
2015-06-15 Renlin Li <renlin.li@arm.com>
bfd/
* reloc.c (BFD_RELOC_AARCH64_LD64_GOTOFF_LO15): New entry.
* elfnn-aarch64.c (elfNN_aarch64_howto_table): New entry for
BFD_RELOC_AARCH64_LD64_GOTOFF_LO15.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas/
* config/tc-aarch64.c (reloc_table): New relocation modifier.
(md_apply_fix): Support BFD_RELOC_AARCH64_LD64_GOTOFF_LO15.
(aarch64_force_relocation): Ditto
gas/testsuite/
* gas/aarch64/reloc-insn.s: Update test
* gas/aarch64/reloc-insn.d: Update expected result.
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Jiong Wang
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3d715ce420 |
[AArch64] GAS support BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
This patch add BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14 support in Gas. The relocation modifier === :gotpage_lo14:symbol 2015-06-01 Jiong.Wang <jiong.wang@arm.com> bfd/ * reloc.c (BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14): New entry. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elfnn-aarch64.c (elfNN_aarch64_howto_table): New entry for BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14. gas/ * config/tc-aarch64.c (reloc_table): New relocation modifiers. (md_apply_fix): Support BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14. (aarch64_force_relocation): Ditto. gas/testsuite/ * gas/aarch64/ilp32-basic.s: New testcase. * gas/aarch64/ilp32-basic.d: Ditto. |
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Jiong Wang
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a921b5bd70 |
[AArch64] GAS Support BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
2015-06-01 Jiong.Wang <jiong.wang@arm.com> bfd/ * reloc.c (BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15): New entry. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elfnn-aarch64.c (elfNN_aarch64_howto_table): New entry for BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15. gas/ * config/tc-aarch64.c (reloc_table): New relocation modifiers. (md_apply_fix): Support BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15. (aarch64_force_relocation): Ditto. gas/testsuite/ * gas/aarch64/reloc-insn.s: New testcase. * gas/aarch64/reloc-insn.d: Ditto. |
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Marcus Shawcroft
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3c12b05436 | Add ADR :tlsgd: directive and TLSGD_ADR_PREL21 support. | ||
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Alan Modra
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3f8107ab38 |
FT32 initial support
FT32 is a new 32-bit RISC core developed by FTDI for embedded applications. * configure.ac: Add FT32 support. * configure: Regenerate. bfd/ * Makefile.am: Add FT32 files. * archures.c (enum bfd_architecture): Add bfd_arch_ft32. (bfd_mach_ft32): Define. (bfd_ft32_arch): Declare. (bfd_archures_list): Add bfd_ft32_arch. * config.bfd: Handle FT32. * configure.ac: Likewise. * cpu-ft32.c: New file. * elf32-ft32.c: New file. * reloc.c (BFD_RELOC_FT32_10, BFD_RELOC_FT32_20, BFD_RELOC_FT32_17, BFD_RELOC_FT32_18): Define. * targets.c (_bfd_target_vector): Add ft32_elf32_vec. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * Makefile.in: Regenerate. * configure: Regenerate. * po/SRC-POTFILES.in: Regenerate. binutils/ * readelf.c: Add FT32 support. gas/ * Makefile.am: Add FT32 files. * config/tc-ft32.c: New file. * config/tc-ft32.h: New file. * configure.tgt: Add FT32 support. * Makefile.in: Regenerate. * po/POTFILES.in: Regenerate. gas/testsuite/ * gas/ft32/ft32.exp: New file. * gas/ft32/insn.d: New file. * gas/ft32/insn.s: New file. include/ * dis-asm.h (print_insn_ft32): Declare. include/elf/ * common.h (EM_FT32): Define. * ft32.h: New file. include/opcode/ * ft32.h: New file. ld/ * Makefile.am: Add FT32 files. * configure.tgt: Handle FT32 target. * emulparams/elf32ft32.sh: New file. * scripttempl/ft32.sc: New file. * Makefile.in: Regenerate. opcodes/ * Makefile.am: Add FT32 files. * configure.ac: Handle FT32. * disassemble.c (disassembler): Call print_insn_ft32. * ft32-dis.c: New file. * ft32-opc.c: New file. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate. |
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Alan Modra
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6346d5ca43 |
Fallout from recent bfd_reloc_outofrange changes
Commit |