This is a minor fix to commit 96462b0129
("RISC-V: Implement Ztso extension"). Currently, it sets EF_RISCV_TSO ELF
flag when initial ISA string contains the 'Ztso' extension. However, GAS
has a way to update the ISA string: ".option arch".
When the architecture is updated by ".option arch", EF_RISCV_RVC ELF flag
is set when the 'C' extension is detected. Analogously, this commit sets
the EF_RISCV_TSO when the 'Ztso' extension is detected.
gas/ChangeLog:
* config/tc-riscv.c (s_riscv_option): Set TSO ELF flag if the
'Ztso' extension is specified via ".option arch" directive.
This patch support ZTSO extension. It will turn on the tso flag for elf_flags
once we have enabled Ztso extension. This is intended to implement v0.1 of
the proposed specification which can be found in Chapter 25 of,
https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-spec.pdf.
bfd\ChangeLog:
* elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Set TSO flag.
* elfxx-riscv.c: Add Ztso's arch.
binutils\ChangeLog:
* readelf.c (get_machine_flags): Set TSO flag.
gas\ChangeLog:
* config/tc-riscv.c (riscv_set_tso): Ditto.
(riscv_set_arch): Ditto.
* testsuite/gas/riscv/ztso.d: New test.
include\ChangeLog:
* elf/riscv.h (EF_RISCV_TSO): Ditto.
Since we have the same behaviors of CALL and CALL_PLT relocs in linker for now,
3b1450b38c
And the psabi already deprecate the CALL reloc,
a0dced8501
Therefore, we should always generate R_RISCV_CALL_PLT reloc for call, even if
it has @plt postfix. I believe LLVM (https://reviews.llvm.org/D132530) already
support this, so GNU as should do the same thing.
gas/
* config/tc-riscv.c (riscv_ip): Always generate CALL_PLT reloc for
call, even if it has @plt postfix.
* testsuite/gas/riscv/no-relax-reloc.d: Updated CALL to CALL_PLT.
* testsuite/gas/riscv/relax-reloc.d: Likewise.
ld/
* testsuite/ld-riscv-elf/variant_cc-r.d: Updated CALL to CALL_PLT.
The last patch wasn't all that shiny. There are rather a lot more
relocations that can hit the assertion in md_apply_fix if the symbol
is local or absolute. Fix them all.
* config/tc-ppc.c (ppc_force_relocation): Add all relocs that
expect a symbol in md_apply_fix. Remove tls pcrel relocs
already covered in general tls match range.
Not that anyone would want to indirect via the GOT when an address can
be loaded directly with pla, the following:
pld 3,x@got@pcrel
x:
leads to "Internal error in md_apply_fix", because the generic parts
of assembler fixup handling convert the fx_pcrel fixup to one without
a symbol. Stop that happening.
* config/tc-ppc.c (ppc_force_relocation): Add PLT_PCREL34 and
assorted GOT_PCREL34 relocs.
Clang generates a warning on unused (technically, written but not read
thereafter) variables. By the default configuration (with "-Werror"), it
causes a build failure (unless "--disable-werror" is specified).
This commit adds ATTRIBUTE_UNUSED attribute to some of them, which means
they are *possibly* unused (can be used but no warnings occur when
unused) and removes others.
bfd/ChangeLog:
* elf32-lm32.c (lm32_elf_size_dynamic_sections): Mark unused
rgot_count variable.
* elf32-nds32.c (elf32_nds32_unify_relax_group): Remove unused
count variable.
* mmo.c (mmo_scan): Mark unused lineno variable.
binutils/ChangeLog:
* windmc.c (write_rc): Remove unused i variable.
gas/ChangeLog:
* config/tc-riscv.c (riscv_ip): Remove unused argnum variable.
ld/ChangeLog:
* pe-dll.c (generate_reloc): Remove unused bi and page_count
variables.
Some components of GNU Binutils will pass "-Wstack-usage=262144" when
"GCC >= 5.0" is detected. However, Clang does not support "-Wstack-usage",
despite that related configuration part in bfd/warning.m4 handles the latest
Clang (15.0.0 as of this writing) as "GCC >= 5.0".
The option "-Wstack-usage" was ignored when the first version of Clang is
released but even this "ignoring" behavior is removed before Clang 4.0.0.
So, if we give Clang "-Wstack-usage=262144", it generates a warning, making
the build failure.
This commit checks "__clang__" macro to prevent adding the option if the
compiler is identified as Clang.
bfd/ChangeLog:
* warning.m4: Stop appending "-Wstack-usage=262144" option when
compiled with Clang.
* configure: Regenerate.
binutils/ChangeLog:
* configure: Regenerate.
gas/ChangeLog:
* configure: Regenerate.
gold/ChangeLog:
* configure: Regenerate.
gprof/ChangeLog:
* configure: Regenerate.
ld/ChangeLog:
* configure: Regenerate.
opcodes/ChangeLog:
* configure: Regenerate.
The -mfuture and -Mfuture options which are used for adding potential
new ISA instructions were not documented. They also lacked a bitmask
so new instructions could not be enabled by those options. Fixed.
binutils/
* doc/binutils.texi: Document -Mfuture.
gas/
* config/tc-ppc.c: Document -mfuture
* doc/c-ppc.texi: Likewise.
include/
* opcode/ppc.h (PPC_OPCODE_FUTURE): Define.
opcodes/
* ppc-dis.c (ppc_opts) <future>: Use it.
* ppc-opc.c (FUTURE): Define.
It looks like I copied the SIZE init across from
binutils/testsuite/config/default.exp without some necessary editing.
* testsuite/config/default.exp (SIZE): Adjust relative path.
Vector CSRs are also required on smaller vector subsets.
Not only that the most of vector CSRs are general purpose (and must be
accessible for every vector subsets), current minimum vector subset 'Zve32x'
requires fixed point arithmetic, making remaining non-general purpose
(fixed point arithmetic only) CSRs mandatory for such subsets.
So, those CSRs must be accessible from 'Zve32x', not just from 'V'.
This commit fixes this issue which caused CSR accessibility warnings.
gas/ChangeLog:
* config/tc-riscv.c (riscv_csr_address): Change vector CSR
requirement from 'V' to 'Zve32x'.
* testsuite/gas/riscv/csr-version-1p9p1.l: Change vector CSR
requirement from 'V' to 'Zve32x'.
* testsuite/gas/riscv/csr-version-1p10.l: Likewise.
* testsuite/gas/riscv/csr-version-1p11.l: Likewise.
* testsuite/gas/riscv/csr-version-1p12.l: Likewise.
PR 29559
* dwarf2dbg.c (out_debug_info): Place DW_TAG_unspecified_type at
the end of the list of children, not at the start of the CU
information.
* testsuite/gas/elf/dwarf-3-func.d: Update expected output.
* testsuite/gas/elf/dwarf-5-func-global.d: Likewise.
* testsuite/gas/elf/dwarf-5-func-local.d: Likewise.
* testsuite/gas/elf/dwarf-5-func.d: Likewise.
This patch makes possible to print the highest address (-1) and the addresses
related to gp which value is -1. This is particularly useful if the highest
address space is used for I/O registers and corresponding symbols are defined.
Besides, despite that it is very rare to have GP the highest address, it would
be nice because we enabled highest address printing on regular cases.
gas/ChangeLog:
* testsuite/gas/riscv/dis-addr-topaddr.s: New test for the top
address (-1) printing.
* testsuite/gas/riscv/dis-addr-topaddr-32.d: Likewise.
* testsuite/gas/riscv/dis-addr-topaddr-64.d: Likewise.
* testsuite/gas/riscv/dis-addr-topaddr-gp.s: New test for
GP-relative addressing when GP is the highest address (-1).
* testsuite/gas/riscv/dis-addr-topaddr-gp-32.d: Likewise.
* testsuite/gas/riscv/dis-addr-topaddr-gp-64.d: Likewise.
opcodes/ChangeLog:
* riscv-dis.c (struct riscv_private_data): Add `to_print_addr' to
enable printing the highest address.
(maybe_print_address): Utilize `to_print_addr'.
(riscv_disassemble_insn): Likewise.
If either the base register is `zero', `tp' or `gp' and XLEN is 32, an
incorrectly sign-extended address is produced when printing. This commit
fixes this by fitting an address into a 32-bit value on RV32.
Besides, H. Peter Anvin discovered that we have wrong address computation
for JALR instruction (the initial bug is back in 2018). This commit also
fixes that based on the idea of Palmer Dabbelt.
gas/
pr29342
* testsuite/gas/riscv/lla32.d: Reflect RV32 address computation fix.
* testsuite/gas/riscv/dis-addr-overflow.s: New testcase.
* testsuite/gas/riscv/dis-addr-overflow-32.d: Likewise.
* testsuite/gas/riscv/dis-addr-overflow-64.d: Likewise.
opcodes/
pr29342
* riscv-dis.c (maybe_print_address): Fit address into 32-bit on RV32.
(print_insn_args): Fix JALR address by adding EXTRACT_ITYPE_IMM.
Address sequences involving ADDIW/C.ADDIW instructions require special
handling to sign-extend lower 32-bits of the original result.
This commit tests whether this sign-extension works.
gas/ChangeLog:
* testsuite/gas/riscv/dis-addr-addiw.s: New to test the address
computation with sign extension as used in ADDIW/C.ADDIW.
* testsuite/gas/riscv/dis-addr-addiw-a.d: Test PC sign bit 0.
* testsuite/gas/riscv/dis-addr-addiw-b.d: Test PC sign bit 1.
gas/ChangeLog:
* testsuite/gas/riscv/dis-addr-addiw-a.d: New test.
* testsuite/gas/riscv/dis-addr-addiw-b.d: New test.
* testsuite/gas/riscv/dis-addr-addiw.s: New test.
Running configure and make in binutils-gdb.
$ ./configure
$ make
In file included from ./as.h:37,
from ./config/loongarch-lex.l:21,
from config/loongarch-lex-wrapper.c:20:
./config.h:206: error: “PACKAGE” redefined [-Werror]
#define PACKAGE "gas"
...
gas/config
* loongarch-lex-wrapper.c
Three-part patch set from Tsukasa OI to support zmmul in assembler.
The 'Zmmul' is a RISC-V extension consisting of only multiply instructions
(a subset of 'M' which has multiply and divide instructions).
bfd/
* elfxx-riscv.c (riscv_implicit_subsets): Add 'Zmmul' implied by 'M'.
(riscv_supported_std_z_ext): Add 'Zmmul' extension.
(riscv_multi_subset_supports): Add handling for new instruction class.
gas/
* testsuite/gas/riscv/attribute-09.d: Updated implicit 'Zmmul' by 'M'.
* testsuite/gas/riscv/option-arch-02.d: Likewise.
* testsuite/gas/riscv/m-ext.s: New test.
* testsuite/gas/riscv/m-ext-32.d: New test (RV32).
* testsuite/gas/riscv/m-ext-64.d: New test (RV64).
* testsuite/gas/riscv/zmmul-32.d: New expected output.
* testsuite/gas/riscv/zmmul-64.d: Likewise.
* testsuite/gas/riscv/m-ext-fail-xlen-32.d: New test (failure
by using RV64-only instructions in RV32).
* testsuite/gas/riscv/m-ext-fail-xlen-32.l: Likewise.
* testsuite/gas/riscv/m-ext-fail-zmmul-32.d: New failure test
(RV32 + Zmmul but with no M).
* testsuite/gas/riscv/m-ext-fail-zmmul-32.l: Likewise.
* testsuite/gas/riscv/m-ext-fail-zmmul-64.d: New failure test
(RV64 + Zmmul but with no M).
* testsuite/gas/riscv/m-ext-fail-zmmul-64.l: Likewise.
* testsuite/gas/riscv/m-ext-fail-noarch-64.d: New failure test
(no Zmmul or M).
* testsuite/gas/riscv/m-ext-fail-noarch-64.l: Likewise.
include/
* opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_ZMMUL.
ld/
* testsuite/ld-riscv-elf/attr-merge-arch-01.d: We don't care zmmul in
these testcases, so just replaced m by a.
* testsuite/ld-riscv-elf/attr-merge-arch-01a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-01b.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-02a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-user-ext-01.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_a2p0.s: Renamed.
* testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_a2p1.s: Renamed.
opcodes/
* riscv-opc.c (riscv_opcodes): Updated multiply instructions to zmmul.
out_inc_line_addr and relax_inc_line_addr are passed INT_MAX as
line_delta to flag end of section. This filters its way down to
size_inc_line_addr and emit_inc_line_addr. Pass line_delta on to
scale_addr_delta where it can be used to omit an unaligned opcode
error.
PR 29494
* dwarf2dbg.c (scale_addr_delta): Delete unnecessary forward decl.
Add line_delta param. Don't print error at end of section, just
round the address down.
(size_inc_line_addr, emit_inc_line_addr): Adjust calls.
PR 29517
* dwarf2dbg.c (GAS_ABBREV_COMP_UNIT): New defined constant.
(GAS_ABBREV_SUBPROG): New defined constant.
(GAS_ABBREV_NO_TYPE): New defined constant.
(out_debug_abbrev): Use the new defined constants when emitting
abbreviation numbers. Generate an abbreviation for an unspecified
type.
(out_debug_info): Use the new defined constants when referring to
abbreviations. Generate a use of the no_type abbreviation.
Reference the use when generating DIEs for functions.
* testsuite/gas/elf/dwarf-3-func.d: Update to allow for newly
extended output from the assembler.
* testsuite/gas/elf/dwarf-5-func-global.d: Likewise.
* testsuite/gas/elf/dwarf-5-func-local.d: Likewise.
* testsuite/gas/elf/dwarf-5-func.d: Likewise.
PR 29519
* config/tc-aarch64.c (s_unreq): Use find_end_of_line().
(s_aarch64_cpu): Likewise.
(s_aarch64_arch): Likewise.
(s_aarch64_arch_extension): Likewise.
* testsuite/gas/aarch64/pr29519.d: New test driver file.
* testsuite/gas/aarch64/pr29519.s: New test source file.
There's been a long-standing bug in the arm backend where
target-specific directives did not correctly handle lines with
multiple statements. This patch fixes the issue for all the cases
I've been able to find.
It does result in a slight change in behaviour when errors are
encountered: where, previously,
.cpu arm6 bar
would result in the error "junk at end of line, first unrecognized
character is `b'", we now get "unknown cpu `arm6 bar'", which I think
is slightly more helpful anyway. Similar errors are generated for
other directives.
Instructions that can load immediate support using constant
variable like ".equ var, 123 li.w/d resgister, var".
gas/
* config/loongarch-parse.y
* config/tc-loongarch.c
Add four testcases.One is a program using constant variable,
one test using label is unsupported, and another two test
almost instructions that can load immediate.
gas/
* testsuite/gas/loongarch/li.d
* testsuite/gas/loongarch/li.s
* testsuite/gas/loongarch/imm_ins_label-fail.d
* testsuite/gas/loongarch/imm_ins_label-fail.l
* testsuite/gas/loongarch/imm_ins_label-fail.s
* testsuite/gas/loongarch/imm_ins.d
* testsuite/gas/loongarch/imm_ins.s
* testsuite/gas/loongarch/imm_ins_32.d
* testsuite/gas/loongarch/imm_ins_32.s
Emitting this warning for every insn, including ones having actual
errors, is annoying. Introduce a boolean variable to emit the warning
just once on the first insn after .arch may have changed the things, and
move the warning to output_insn(). (I didn't want to go as far as
checking whether the .arch actually turned off the i386 bit, but doing
so would be an option.)
When displaying operands, invalid opcodes may overflow operand buffer
due to additional styling characters. Each style is encoded with 3
bytes. Define MAX_OPERAND_BUFFER_SIZE for operand buffer size and
increase it from 100 bytes to 128 bytes to accommodate 9 sets of styles
in an operand.
gas/
PR binutils/29483
* testsuite/gas/i386/i386.exp: Run pr29483.
* testsuite/gas/i386/pr29483.d: New file.
* testsuite/gas/i386/pr29483.s: Likewise.
opcodes/
PR binutils/29483
* i386-dis.c (MAX_OPERAND_BUFFER_SIZE): New.
(obuf): Replace 100 with MAX_OPERAND_BUFFER_SIZE.
(staging_area): Likewise.
(op_out): Likewise.
This changes readelf output a little, removing the 0x prefix on hex
output when the value is 0, except in cases where a fixed field
width is shown. %#010x is not a good replacement for 0x%08x.
svstep and svshape instructions subtract 1 before encoding some of the
operands. Obviously zero is not supported for these operands. Whilst
PPC_OPERAND_PLUS1 fits perfectly to mark that maximal value should be
incremented, there is no flag which marks the fact that zero values are
not allowed. This patch adds a new flag, PPC_OPERAND_NONZERO, for this
purpose.
This patch adds support for LibreSOC machine and SVP64 extension flag
for PowerPC architecture. SV (Simple-V) is a strict RISC-paradigm
Scalable Vector Extension for the Power ISA. SVP64 is the 64-bit
Prefixed instruction format implementing SV. Funded by NLnet through EU
Grants No: 825310 and 825322, SV is in DRAFT form and is to be publicly
submitted via the OpenPOWER Foundation ISA Working Group via the
newly-created External RFC Process.
For more details, visit https://libre-soc.org.
Commit 53f2b36a54 exposed a bug in sb_scrub_and_add_sb that could
result in losing input. If scrubbing results in expansion past the
holding capacity of do_scrub_chars output buffer, then do_scrub_chars
stashes the extra input for the next call. That call never came
because sb_scrub_and_add_sb wrongly decided it was done. Fix that by
allowing sb_scrub_and_add_sb to see whether there is pending input.
Also allow a little extra space so that in most cases we won't need
to resize the output buffer.
sb_scrub_and_add_sb also limited output to the size of the input,
rather than the actual output buffer size. Fixing that resulted in a
fail of gas/testsuite/macros/dot with an extra warning: "end of file
not at end of a line; newline inserted". OK, so the macro in dot.s
really does finish without end-of-line. Apparently the macro
expansion code relied on do_scrub_chars returning early. So fix that
too by adding a newline if needed in macro_expand_body.
PR 29466
* app.c (do_scrub_pending): New function.
* as.h: Declare it.
* input-scrub.c (input_scrub_include_sb): Add extra space for
two .linefile directives.
* sb.c (sb_scrub_and_add_sb): Take into account pending input.
Allow output to max.
* macro.c (macro_expand_body): Add terminating newline.
* testsuite/config/default.exp (SIZE, SIZEFLAGS): Define.
* testsuite/gas/macros/app5.d,
* testsuite/gas/macros/app5.s: New test.
* testsuite/gas/macros/macros.exp: Run it.
PR gas/29451
While out_debug_abbrev() properly skips such functions, out_debug_info()
mistakenly didn't. It needs to calculate the high_pc expression ahead of
time, in order to skip emitting any data for the function if the value
is zero.
The one case which would still leave a zero-size entry is when
symbol_get_obj(symp)->size ends up evaluating to zero. I hope we can
expect that to not be the case, otherwise we'd need to have a way to
post-process .debug_info contents between resolving expressions and
actually writing the data out to the file. Even then it wouldn't be
entirely obvious in which way to alter the data.
It is unclear to me why the corresponding MOV (no Q suffix) can be
issued without REX.W, but MOVQ has to have that prefix (bit). Add
NoRex64 and in exchange drop Size64.
While the x/y/z suffix isn't necessary to use in this case, it is still
odd that these forms don't support broadcast (unlike their AVX512F /
AVX512DQ counterparts). The lack thereof can e.g. make macro-ized
programming more difficult.
The commit 1369522f36 ("Recognize the new ELF
compression type for ZSTD.") added the new ELF compression type but it
accidentally broke a GAS testcase. Since testing for the section type
"2048" (SHF_COMPRESSED) is not going to be portable in the long term, it
now tests SHF_LINK_ORDER ("128") instead.
Using SHF_LINK_ORDER (with possibly sh_link == 0) is an idea by Jan Beulich.
gas/ChangeLog:
* testsuite/gas/elf/section10.s: Use SHF_LINK_ORDER to test
mixed numeric and alpha values.
* testsuite/gas/elf/section10.d: Reflect the change above.
BFD_VMA_FMT can't be used in format strings that need to be
translated, because the translation won't work when the type of
bfd_vma differs from the machine used to compile .pot files. We've
known about this for a long time, but patches slip through review.
So just get rid of BFD_VMA_FMT, instead using the appropriate PRId64,
PRIu64, PRIx64 or PRIo64 and SCN variants for scanf. The patch is
mostly mechanical, the only thing requiring any thought is casts
needed to preserve PRId64 output from bfd_vma values, or to preserve
one of the unsigned output formats from bfd_signed_vma values.
- Drop the rounding type check: We're past template matching, and none
of the involved insns support embedded rounding.
- Drop the extension opcode check: None of the involved opcodes have
variants with it being other than None.
- Instead check opcode space, even if just to be on the safe side going
forward.
- Reduce the number of comparisons by folding two groups.
First of all rename the meanwhile misleading Opcode_SIMD_FloatD, as it
has also been used for KMOV* and BNDMOV. Then simplify the condition
selecting which form if "reversing" to use - except for the MOV to/from
control/debug/test registers all extended opcode space insns use bit 0
(rather than bit 1) to indicate the direction (from/to memory) of an
operation. With that, D can simply be set on the first of the two
templates, while the other can be dropped.
This patch extends assembler support for the use of register names to
allow for pseudo-registers, e.g. ra_auth_code register.
This is done particularly with CFI directives in mind, allowing for
expressions of the type:
.cfi_register ra_auth_code, 12
gas/Changelog:
* config/tc-arm.c (tc_arm_regname_to_dw2regnum): Add
REG_TYPE_PSEUDO handling.
* testsuite/gas/arm/cfi-pacbti-m-readelf.d: New.
* testsuite/gas/arm/cfi-pacbti-m.s: New.
This patch modifies the internal `struct reg_entry' numbering of DWARF
pseudo-registers to match values assigned in DWARF standards (see "4.1
DWARF register names" in [1])so ra_auth_code goes from 12 to 143 and
amends the unwinder .save directive-processing code to correctly handle
mixed register-type save directives.
The mechanism for splitting the register list is also re-written to
comply with register ordering on push statements, being that registers
are stored on the stack in numerical order, with the lowest numbered
register at the lowest address [2].
Consequently, the parsing of the hypothetical directive
.save{r4-r7, r10, ra_auth_core, lr}
has been changed such as rather than producing
.save{r4-r7, r10}
.save{ra_auth_code}
.save{lr}
as was the case with previous implementation, now produces:
.save{lr}
.save{ra_auth_code}
.save{r4-r7, r10}
[1] <https://github.com/ARM-software/abi-aa/blob/main/aadwarf32/aadwarf32.rst>
[2] <https://developer.arm.com/documentation/dui0473/j/arm-and-thumb-instructions/push>
gas/Changelog:
* config/tc-arm.c (REG_RA_AUTH_CODE): New.
(parse_dot_save): Likewise.
(parse_reg_list): Remove obsolete code.
(reg_names): Set ra_auth_code to 143.
(s_arm_unwind_save): Handle core and pseudo-register lists via
parse_dot_save.
(s_arm_unwind_save_mixed): Deleted.
(s_arm_unwind_save_pseudo): Handle one register at a time.
* testsuite/gas/arm/unwind-pacbti-m-readelf.d: Fix test.
* testsuite/gas/arm/unwind-pacbti-m.d: Likewise.
This syntactic sugar is present in both classical and emerging
architectures, like Alpha, SPARC and RISC-V, and assembler macros
doing the same thing can already be found in the wild e.g. [1], proving
the feature's popularity. It's better to provide support directly in the
assembler so downstream users wouldn't have to re-invent this over and
over again.
[1]: https://sourceware.org/git/?p=glibc.git;a=blob;f=sysdeps/unix/sysv/linux/loongarch/sysdep.h;h=c586df819cd90;hb=HEAD#l28
Also re-order the jump/branch opcodes while at it, so that insns are
sorted in ascending order according to opcodes, and the label form
preceding the real definition.
These two macros print either a 16 digit hex number or an 8 digit
hex number. Unfortunately they depend on both target and host, which
means that the output for 32-bit targets may be either 8 or 16 hex
digits.
Replace them in most cases with code that prints a bfd_vma using
PRIx64. In some cases, deliberately lose the leading zeros.
This change some output, notably in base/offset fields of m68k
disassembly which I think looks better that way, and in error
messages. I've kept leading zeros in symbol dumps (objdump -t)
and in PE header dumps.
bfd/
* bfd-in.h (fprintf_vma, sprintf_vma, printf_vma): Delete.
* bfd-in2.h: Regenerate.
* bfd.c (bfd_sprintf_vma): Don't use sprintf_vma.
(bfd_fprintf_vma): Don't use fprintf_vma.
* coff-rs6000.c (xcoff_reloc_type_tls): Don't use sprintf_vma.
Instead use PRIx64 to print bfd_vma values.
(xcoff_ppc_relocate_section): Likewise.
* cofflink.c (_bfd_coff_write_global_sym): Likewise.
* mmo.c (mmo_write_symbols_and_terminator): Likewise.
* srec.c (srec_write_symbols): Likewise.
* elf32-xtensa.c (print_r_reloc): Similarly for fprintf_vma.
* pei-x86_64.c (pex64_dump_xdata): Likewise.
(pex64_bfd_print_pdata_section): Likewise.
* som.c (som_print_symbol): Likewise.
* ecoff.c (_bfd_ecoff_print_symbol): Use bfd_fprintf_vma.
opcodes/
* dis-buf.c (perror_memory, generic_print_address): Don't use
sprintf_vma. Instead use PRIx64 to print bfd_vma values.
* i386-dis.c (print_operand_value, print_displacement): Likewise.
* m68k-dis.c (print_base, print_indexed): Likewise.
* ns32k-dis.c (print_insn_arg): Likewise.
* ia64-gen.c (_opcode_int64_low, _opcode_int64_high): Delete.
(opcode_fprintf_vma): Delete.
(print_main_table): Use PRIx64 to print opcode.
binutils/
* od-macho.c: Replace all uses of printf_vma with bfd_printf_vma.
* objcopy.c (copy_object): Don't use sprintf_vma. Instead use
PRIx64 to print bfd_vma values.
(copy_main): Likewise.
* readelf.c (CHECK_ENTSIZE_VALUES): Likewise.
(dynamic_section_mips_val): Likewise.
(print_vma): Don't use printf_vma. Instead use PRIx64 to print
bfd_vma values.
(dump_ia64_vms_dynamic_fixups): Likewise.
(process_version_sections): Likewise.
* rddbg.c (stab_context): Likewise.
gas/
* config/tc-i386.c (offset_in_range): Don't use sprintf_vma.
Instead use PRIx64 to print bfd_vma values.
(md_assemble): Likewise.
* config/tc-mips.c (load_register, macro): Likewise.
* messages.c (as_internal_value_out_of_range): Likewise.
* read.c (emit_expr_with_reloc): Likewise.
* config/tc-ia64.c (note_register_values): Don't use fprintf_vma.
Instead use PRIx64 to print bfd_vma values.
(print_dependency): Likewise.
* listing.c (list_symbol_table): Use bfd_sprintf_vma.
* symbols.c (print_symbol_value_1): Use %p to print pointers.
(print_binary): Likewise.
(print_expr_1): Use PRIx64 to print bfd_vma values.
* write.c (print_fixup): Use %p to print pointers. Don't use
fprintf_vma.
* testsuite/gas/all/overflow.l: Update expected output.
* testsuite/gas/m68k/mcf-mov3q.d: Likewise.
* testsuite/gas/m68k/operands.d: Likewise.
* testsuite/gas/s12z/truncated.d: Likewise.
ld/
* deffilep.y (def_file_print): Don't use fprintf_vma. Instead
use PRIx64 to print bfd_vma values.
* emultempl/armelf.em (gld${EMULATION_NAME}_finish): Don't use
sprintf_vma. Instead use PRIx64 to print bfd_vma values.
* emultempl/pe.em (gld${EMULATION_NAME}_finish): Likewise.
* ldlang.c (lang_map): Use %V to print region origin.
(lang_one_common): Don't use sprintf_vma.
* ldmisc.c (vfinfo): Don't use fprintf_vma or sprintf_vma.
* pe-dll.c (pe_dll_generate_def_file): Likewise.
gdb/
* remote.c (remote_target::trace_set_readonly_regions): Replace
uses of sprintf_vma with bfd_sprintf_vma.
This commit enables disassembler styling for AArch64. After this
commit it is possible to have objdump style AArch64 disassembler
output (using --disassembler-color option). Once the required GDB
patches are merged, GDB will also style the disassembler output.
The changes to support styling are mostly split between two files
opcodes/aarch64-dis.c and opcodes/aarch64-opc.c.
The entry point for the AArch64 disassembler can be found in
aarch64-dis.c, this file handles printing the instruction mnemonics,
and assembler directives (e.g. '.byte', '.word', etc). Some operands,
mostly relating to assembler directives are also printed from this
file. This commit changes all of this to pass through suitable
styling information.
However, for most "normal" instructions, the instruction operands are
printed using a two step process. From aarch64-dis.c, in the
print_operands function, the function aarch64_print_operand is called,
this function is in aarch64-opc.c, and converts an instruction operand
into a string. Then, back in print_operands (aarch64-dis.c), the
operand string is printed.
Unfortunately, the string returned by aarch64_print_operand can be
quite complex, it will include syntax elements, like '[' and ']', in
addition to register names and immediate values. In some cases, a
single operand will expand into what will appear (to the user) as
multiple operands separated with a ','.
This makes the task of styling more complex, all these different
components need to by styled differently, so we need to get the
styling information out of aarch64_print_operand in some way.
The solution that I propose here is similar to the solution that I
used for the i386 disassembler.
Currently, aarch64_print_operand uses snprintf to write the operand
text into a buffer provided by the caller.
What I propose is that we pass an extra argument to the
aarch64_print_operand function, this argument will be a structure, the
structure contains a callback function and some state.
When aarch64_print_operand needs to format part of its output this can
be done by using the callback function within the new structure, this
callback returns a string with special embedded markers that indicate
which mode should be used for each piece of text. Back in
aarch64-dis.c we can spot these special style markers and use this to
split the disassembler output up and apply the correct style to each
piece.
To make aarch64-opc.c clearer a series of new static functions have
been added, e.g. 'style_reg', 'style_imm', etc. Each of these
functions formats a piece of text in a different style, 'register' and
'immediate' in this case.
Here's an example taken from aarch64-opc.c of the new functions in
use:
snprintf (buf, size, "[%s, %s]!",
style_reg (styler, base),
style_imm (styler, "#%d", opnd->addr.offset.imm));
The aarch64_print_operand function is also called from the assembler
to aid in printing diagnostic messages. Right now I have no plans to
add styling to the assembler output, and so, the callback function
used in the assembler ignores the styling information and just returns
an plain string.
I've used the source files in gas/testsuite/gas/aarch64/ for testing,
and have manually gone through and checked that the styling looks
reasonable, however, I'm not an AArch64 expert, so it is possible that
the odd piece is styled incorrectly. Please point out any mistakes
I've made.
With objdump disassembler color turned off, there should be no change
in the output after this commit.
The original approach has resulted in anomalies when . is involved in an
operand of one of the affected insns. We cannot leave . unresolved, or
else it'll be resolved at the end of assembly, then pointing to the
address of a section rather than at the insn of interest. Undo part of
the original change and instead check whether a relocation cannot be
omitted in md_apply_fix().
By resolving the expressions again, equates (see the adjustment of the
respective testcase) will now be evaluated, and hence relocations
against absolute addresses be emitted. This ought to be okay as long as
the equates aren't global (and hence can't be overridden). If a need
for such arises, quite likely the only way to address this would be to
invent yet another expression evaluation mode, leaving everything
_except_ . un-evaluated.
There's a further anomaly in how transitive equates are handled. In
.set x, 0x12345678
.eqv bar, x
foo:
adrp x0, x
add x0, x0, :lo12:x
adrp x0, bar
add x0, x0, :lo12:bar
the first two relocations are now against *ABS*:0x12345678 (as said
above), whereas the latter two relocations would be against x. (Before
the change here, the first two relocations are against x and the latter
two against bar.) But this is an issue seen elsewhere as well, and would
likely require adjustments in the target-independent parts of the
assembler instead of trying to hack around this for every target.
This commit adds `OP_V' (OP-V: vector instruction opcode for now
ratified `V' extension) to .insn opcode name list. Although vector
instruction encoding is not implemented in `.insn' directive, it will
help future implementation of custom vector `.insn'.
gas/ChangeLog:
* config/tc-riscv.c (opcode_name_list): Add `OP_V'.
* testsuite/gas/riscv/insn.s: Add testcase.
* testsuite/gas/riscv/insn.d: Likewise.
* testsuite/gas/riscv/insn-dwarf.d: Reflect insn.s update.
I clearly screwed up in 6ff00b5e12 ("x86/Intel: correct permitted
operand sizes for AVX512 scatter/gather") giving all AVX512F scatter
insns Dword element size. Update testcases (also their gather parts),
utilizing that there previously were two identical lines each (for no
apparent reason).
Assuming GMSD is a special operand, marked as O_md1, the code:
.set VREG, GMSD
.set REG, VREG
extsw REG, 2
...fails upon attempts to resolve the value of the symbol. This happens
since machine-dependent values are not handled in the giant op switch.
We introduce a custom md_resolve_symbol macro; the ports can use this
macro to customize the behavior when resolve_symbol_value hits O_md
operand.
The ciphers 5,7, and 9 are missing when parsing an assembly
instruction leading to errors when those ciphers are
used.
gas/config
* tc-arc.c (md_assembly): Update strspn string with the
missing ciphers.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
Both forms were missing VexW0 (thus allowing Evex.W=1 to be encoded by
suitable means, which would cause #UD). The memory operand form further
was using the wrong Masking value, thus allowing zeroing-masking to be
encoded for the store form (which would again cause #UD).
I meant to make this change before committing, to let compilers know
the code on the false branch of md_parse_name is dead.
* config/tc-ppc.c (ppc_parse_name): Return void.
* config/tc-ppc.h (md_parse_name): Always true.
(ppc_parse_name): Update prototype.
Allows register names to appear in symbol assignments, so for example
tocp = %r2
mr %r3,tocp
now assembles.
* gas/config/tc-ppc.c (REG_NAME_CNT): Delete, replace uses with
ARRAY_SIZE.
(register_name): Rename to..
(md_operand): ..this. Only handle %reg.
(cr_names): Rename to..
(cr_cond): ..this. Just keep conditions.
(ppc_parse_name): Add mode param. Search both cr_cond and
pre_defined_registers. Handle absolute and register symbol
values here rather than in expr.c:operand().
(md_assemble): Don't special case register name matching in
operands, except to set cr_operand as appropriate.
* gas/config/tc-ppc.h (md_operand): Don't define.
(md_parse_name, ppc_parse_name): Update.
* read.c (pseudo_set): Copy over entire O_register value.
* testsuite/gas/ppc/regsyms.d.
* testsuite/gas/ppc/regsyms.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
It might be possible to hit md_end before md_begin is called, don't
segfault if so. Also, remove a useless check.
* gas/config/tc-ppc.c (insn_calloc): Remove needless overflow
check.
(ppc_md_end): Check ppc_hash before deleting. Clear ppc_hash.
Cleaning up the subsym_hash memory is a real pain. Keys and values
entered into the table are quite diverse. In some cases the key is
allocated and thus needs to be freed, in others the key is a const
string. Values are similar, and in some cases not even a string.
Tidy this by inserting a new subsym_ent_t that describes key/value
type. This meant the math_hash table was no longer needed. The patch
also tidies how math functions are called, those that are supposed to
return int now no longer return their value in a float.
* config/tc-tic54x.c (math_hash): Delete.
(subsym_proc_entry): Move earlier, make proc a union, merge with..
(math_proc_entry): ..this. Delete type.
(math_procs): Merge into subsym_procs.
(subsym_ent_t): New. Use this type in subsym_hash..
(stag_add_field_symbols, tic54x_var, tic54x_macro_info): ..here..
(md_begin, subsym_create_or_replace, subsym_lookup): ..and here..
(subsym_substitute): ..and here. Adjust subsym_proc_entry
function calls. Free replacement when not returned.
(subsym_get_arg): Adjust subsym_lookup.
(free_subsym_ent, subsym_htab_create ): New functions, use when
creating subsym_hash.
(free_local_label_ent, local_label_htab_create): Similarly.
(tic54x_remove_local_label): Delete.
(tic54x_clear_local_labels): Simplify.
(tic54x_asg): Use notes obstack to dup strings.
(tic54x_eval): Likewise.
(subsym_ismember): Likewise.
(math_cvi, math_int, math_sgn): Return int.
(tic54x_macro_start): Decrement macro_level before calling as_fatal.
(tic54x_md_end): New function.
* config/tc-tic54h.c (tic54x_md_end): Declare.
(md_end): Define.
Using notes_calloc means all of the string hash table memory should
now be freed before gas exits, even though htab_delete isn't called.
This also means that the hash table free_f and del_f must be NULL,
because freeing notes obstack memory results in all more recently
allocated notes memory being freed too. So hash table resizing won't
free any memory, and will be a little faster. Also, htab_delete won't
do anything (and be quick about it).
Since htab_traverse can also resize hash tables (to make another
traversal faster if the table is largely empty), stop that happening
when only one traversal is done.
* as.h: Reorder hash.h after symbols.h for notes_calloc decl.
* hash.h (str_htab_create): Use notes_calloc. Do not free.
* symbols.c (resolve_local_symbol_values): Don't resize
during hash table traversal.
* config/obj-elf.c (elf_frob_file_after_relocs): Likewise.
* config/tc-ia64.c (ia64_adjust_symtab, ia64_frob_file): Likewise.
* config/tc-nds32.c (nds32_elf_analysis_relax_hint): Likewise.
This allocates entries added to the string hash tables on the notes
obstack, so that at least those do not leak. A followup patch will
switch over the str_hash allocation to notes_calloc, which is why I
haven't implemented deleting all the target string hash tables.
* config/obj-coff-seh.c (get_pxdata_name, alloc_pxdata_item): Use
notes obstack for string hash table entries.
* config/tc-alpha.c (get_alpha_reloc_tag, md_begin): Likewise.
* config/tc-h8300.c (md_begin): Likewise.
* config/tc-ia64.c (dot_rot, dot_pred_rel, dot_alias): Likewise.
* config/tc-nds32.c (nds32_relax_hint): Likewise.
* config/tc-riscv.c (riscv_init_csr_hash): Likewise.
* config/tc-score.c (s3_insert_reg): Likewise.
(s3_build_score_ops_hsh, s3_build_dependency_insn_hsh): Likewise.
* config/tc-score7.c (s7_build_score_ops_hsh): Likewise.
(s7_build_dependency_insn_hsh): Likewise.
* config/tc-tic4x.c (tic4x_asg): Likewise.
The arc opcode hash table has entries that have a realloc'd field.
This doesn't lend itself to obstack allocation, so freeing must be
done with a purpose built hashtab del_f.
* config/tc-arc.c (arc_opcode_free): New function.
(md_begin): Pass the above as del_f to htab_create_alloc.
(arc_md_end): New function.
* config/tc-arc.h (arc_md_end): Declare.
(md_end): Define.
This tidies memory used by the two x86 gas string hash tables before
exiting. I'm using a two-pronged approach, firstly the obvious call
to htab_delete plus telling the libiberty/hashtab.c infrastructure to
free tuples generated by str_hash_insert, and secondly putting the x86
core_optab memory on the notes obstack. It would be possible to free
core_optab memory by using a custom hash table del_f on x86, as I do
for arc, but a later patch will move all the string hash memory to the
notes obstack.
* config/tc-i386.c (md_begin): Use notes_alloc for core_optab.
(386_md_end): New function.
* config/tc-i386.h (386_md_end): Declare.
(md_end): Define.
* hash.h (str_htab_create): Pass free as del_f.
Only inline functions should be defined in hash.h, there's no benefit
in having multiple copies of hash_string_tuple and eq_string_tuple.
Also, use the table alloc_f when allocating tuples to be stored, so
that these functions are usable with different memory allocation
strategies.
* hash.h (struct string_tuple, string_tuple_t): Move earlier.
(string_tuple_alloc): Add table param, allocate using table alloc_f.
(str_hash_insert): Adjust to suit. Call table->free_f when
entry is not used.
(hash_string_tuple, eq_string_tuple): Move to..
* hash.c: ..here.
Currently md_end is typically used for some final actions rather than
freeing memory like other *_end functions. Rename it to md_finish,
and rename target implementation. The renaming of target functions
makes it possible to find them all with "grep md_finish",
eg. md_mips_end is renamed to mips_md_finish, not md_mips_finish.
This patch leaves a number of md_end functions unchanged, those that
either do nothing or deallocate memory, and calls them late.
The idea here is that target maintainers implement md_end functions to
tidy memory, if anyone cares. Freeing persistent memory in gas is
not at all important, except that it can hide more important memory
leaks, those that happen once per some frequent gas operation, amongst
these unimportant memory leaks.
* as.c (main): Rename md_end to md_finish.
* config/tc-alpha.c, * config/tc-alpha.h,
* config/tc-arc.c, * config/tc-arc.h,
* config/tc-arm.c, * config/tc-arm.h,
* config/tc-csky.c, * config/tc-csky.h,
* config/tc-ia64.c, * config/tc-ia64.h,
* config/tc-mcore.c, * config/tc-mcore.h,
* config/tc-mips.c, * config/tc-mips.h,
* config/tc-mmix.c, * config/tc-mmix.h,
* config/tc-msp430.c, * config/tc-msp430.h,
* config/tc-nds32.c, * config/tc-nds32.h,
* config/tc-ppc.c, * config/tc-ppc.h,
* config/tc-pru.c, * config/tc-pru.h,
* config/tc-riscv.c, * config/tc-riscv.h,
* config/tc-s390.c, * config/tc-s390.h,
* config/tc-sparc.c, * config/tc-sparc.h,
* config/tc-tic4x.c, * config/tc-tic4x.h,
* config/tc-tic6x.c, * config/tc-tic6x.h,
* config/tc-v850.c, * config/tc-v850.h,
* config/tc-xtensa.c, * config/tc-xtensa.h,
* config/tc-z80.c, * config/tc-z80.h: Similarly.
* output-file.c (output_file_close): Call md_end.
So that the notes obstack can be used for persistent storage in
parse_args.
* as.c (parse_args): Use notes_alloc and notes_strdup.
(free_notes): New function.
(main): Init notes obstack, and arrange to be freed on exit.
* read.c (read_begin): Don't init notes obstack.
(read_end): Free cond_obstack.
* subsegs.c (subsegs_end): Don't free cond_obstack or notes.
itbl_files seems to be debug code. Get rid of it.
* as.c (struct itbl_file_list): Delete.
(itbl_files): Delete.
(parse_args): Don't keep itbl_files list.
Use notes obstack for dwcfi_hash entries, and free table. Freeing the
table makes memory checkers complain more about "definitely lost"
memory as we've moved some from the "still reachable" category.
That will be fixed with a later patch.
* dw2gencfi.c (get_debugseg_name): Allocate on notes obstack.
(alloc_debugseg_item): Likewise.
(dwcfi_hash_find_or_make): Adjust failure path free.
(cfi_finish): Delete dwfci_hash.
Another case of duplicated hash.h code, the only minor difference
being that macro->format_hash was created with 7 entries vs. str_hash
with 16 entries.
* macro.c (macro_init, define_macro): Use str_htab_create.
(do_formals, define_macro, macro_expand_body): Use str_hash_insert
(macro_expand_body): Use str_hash_find and str_hash_delete.
(delete_macro): Likewise.
(sub_actual, macro_expand, check_macro): Use str_hash_find.
(expand_irp): Use str_htab_create and str_hash_insert.
* macro.h (struct macro_struct): Tidy.
(struct macro_hash_entry, macro_hash_entry_t, hash_macro_entry),
(eq_macro_entry, macro_entry_alloc, macro_entry_find),
(struct formal_hash_entry, formal_hash_entry_t),
(hash_formal_entry, eq_formal_entry, formal_entry_alloc),
(formal_entry_find): Delete.
* config/tc-iq2000.c (iq2000_add_macro): Use str_htab_create
and str_hash_insert.
po_hash code duplicates the str_hash code in hash.h for no good reason.
* read.c (struct po_entry, po_entry_t): Delete.
(hash_po_entry, eq_po_entry, po_entry_alloc, po_entry_find): Delete.
(pop_insert): Use str_hash_insert.
(pobegin): Use str_htab_create.
(read_a_source_file, s_macro): Use str_hash_find.
read_symbol_name mallocs the string it returns. Free it when done.
* read.c (read_symbol_name): Free name on error path.
* config/tc-ppc.c (ppc_GNU_visibility): Free name returned from
read_symbol_name.
(ppc_extern, ppc_globl, ppc_weak): Likewise.
This is mostly a tidy with the aim of being able to free
out_file_name, but it does fix a possible attempt to unlink the output
file twice (not that that matters).
* as.h (keep_it): New global.
* as.c (keep_it): Delete.
(close_output_file): Delete, merged into..
* output-file.c (output_file_close): ..here. Delete parameter.
* output-file.h (output_file_close): Update prototype.
Makes it a little easier to use the notes obstack for persistent
storage.
* as.h (gas_mul_overflow): Define.
* symbols.h (notes_alloc, notes_calloc, notes_memdup),
(notes_strdup, notes_concat, notes_free): Declare.
* symbols.c (notes_alloc, notes_calloc, notes_memdup),
(notes_strdup, notes_concat, notes_free): New functions.
(save_symbol_name): Use notes_strdup.
(symbol_create, local_symbol_make, local_symbol_convert),
(symbol_clone, decode_local_label_name): Use notes_alloc.
arm gas is only supposed to warn once per symbol for -mwarn-syms, but
doesn't because the str_hash_find added with commit 629310abec
always returns NULL. That's so because the str_hash_insert inserts a
NULL value for the key,value pair. Let str_hash_insert do the job
instead.
* config/tc-arm.c (arm_tc_equal_in_insn): Correct already_warned
logic.
* testsuite/gas/arm/pr18347.s: Modify to generate duplicate
warning without this patch.
Until we update the recommended versions of autoconf/automake, files
should be regenerated with automake-1.15.1 and autoconf-2.69. That's
not because we think those versions are golden, and newer versions are
bad. It's simply because maintainers want to be able to update
configury files without trouble, and if someone regenerates files with
automake-1.16.5 then --enable-maintainer-mode builds will hit errors:
checking that generated files are newer than configure... configure.ac:26: error: version mismatch. This is Automake 1.15.1,
configure.ac:26: but the definition used by this AM_INIT_AUTOMAKE
configure.ac:26: comes from Automake 1.16.5. You should recreate
configure.ac:26: aclocal.m4 with aclocal and run automake again.
WARNING: 'automake-1.15' is probably too old.
Correcting this requires regenerating the files by hand.
This commit adds Zfhmin and Zhinxmin extensions (subsets of Zfh and
Zhinx extensions, respectively). In the process supporting Zfhmin and
Zhinxmin extension, this commit also changes how instructions are
categorized considering Zfhmin, Zhinx and Zhinxmin extensions.
Detailed changes,
* From INSN_CLASS_ZFH to INSN_CLASS_ZFHMIN:
flh, fsh, fmv.x.h and fmv.h.x.
* From INSN_CLASS_ZFH to INSN_CLASS_ZFH_OR_ZHINX:
fmv.h.
* From INSN_CLASS_ZFH_OR_ZHINX to INSN_CLASS_ZFH_OR_ZHINX:
fneg.h, fabs.h, fsgnj.h, fsgnjn.h, fsgnjx.h,
fadd.h, fsub.h, fmul.h, fdiv.h, fsqrt.h, fmin.h, fmax.h,
fmadd.h, fnmadd.h, fmsub.h, fnmsub.h,
fcvt.w.h, fcvt.wu.h, fcvt.h.w, fcvt.h.wu,
fcvt.l.h, fcvt.lu.h, fcvt.h.l, fcvt.h.lu,
feq.h, flt.h, fle.h, fgt.h, fge.h,
fclass.h.
* From INSN_CLASS_ZFH_OR_ZHINX to INSN_CLASS_ZFHMIN_OR_ZHINXMIN:
fcvt.s.h and fcvt.h.s.
* From INSN_CLASS_D_AND_ZFH_INX to INSN_CLASS_ZFHMIN_AND_D:
fcvt.d.h and fcvt.h.d.
* From INSN_CLASS_Q_AND_ZFH_INX to INSN_CLASS_ZFHMIN_AND_Q:
fcvt.q.h and fcvt.h.q.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_implicit_subsets): Change implicit
subsets. Zfh->Zicsr is not needed and Zfh->F is replaced with
Zfh->Zfhmin and Zfhmin->F. Zhinx->Zicsr is not needed and
Zhinx->Zfinx is replaced with Zhinx->Zhinxmin and
Zhinxmin->Zfinx.
(riscv_supported_std_z_ext): Added zfhmin and zhinxmin.
(riscv_multi_subset_supports): Rewrite handling for new
instruction classes.
(riscv_multi_subset_supports_ext): Updated.
(riscv_parse_check_conflicts): Change error message to include
zfh and zfhmin extensions.
gas/ChangeLog:
* testsuite/gas/riscv/zfhmin-d-insn-class-fail.s: New complex
error handling test.
* testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d: Likewise.
* testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l: Likewise.
* testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d: Likewise.
* testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l: Likewise.
* testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d: Likewise.
* testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l: Likewise.
* testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d: Likewise.
* testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l: Likewise.
* testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d: Likewise.
* testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l: Likewise.
* testsuite/gas/riscv/zhinx.d: Renamed from fp-zhinx-insns.d
and refactored.
* testsuite/gas/riscv/zhinx.s: Likewise.
include/ChangeLog:
* opcode/riscv.h (enum riscv_insn_class): Removed INSN_CLASS_ZFH,
INSN_CLASS_D_AND_ZFH_INX and INSN_CLASS_Q_AND_ZFH_INX. Added
INSN_CLASS_ZFHMIN, INSN_CLASS_ZFHMIN_OR_ZHINXMIN,
INSN_CLASS_ZFHMIN_AND_D and INSN_CLASS_ZFHMIN_AND_Q.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Change instruction classes for
Zfh and Zfhmin instructions. Fix `fcvt.h.lu' instruction
(two operand variant) mask.
This commit fixes floating point operand register names from ABI ones
to dynamically set ones.
gas/ChangeLog:
* testsuite/gas/riscv/zfinx-dis-numeric.s: Test new behavior of
Zfinx extension and -M numeric disassembler option.
* testsuite/gas/riscv/zfinx-dis-numeric.d: Likewise.
opcodes/ChangeLog:
* riscv-dis.c (riscv_disassemble_insn): Use dynamically set GPR
names to disassemble Zfinx instructions.
This commit fixes how instructions are masked on Zhinx+Z{d,q}inx.
fcvt.h.d and fcvt.d.h require ((D&&Zfh)||(Zdinx&&Zhinx)) and
fcvt.h.q and fcvt.q.h require ((Q&&Zfh)||(Zqinx&&Zhinx)).
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Fix feature gate
on INSN_CLASS_{D,Q}_AND_ZFH_INX.
(riscv_multi_subset_supports_ext): Fix feature gate diagnostics
on INSN_CLASS_{D,Q}_AND_ZFH_INX.
gas/ChangeLog:
* testsuite/gas/riscv/fp-zhinx-insns.d: Add Zqinx to -march
for proper testing.
This once again allows to reduce redundancy in (and size of) the opcode
table.
Don't go as far as also making D work on the two 5-operand XOP insns:
This would significantly complicate the code, as there the first
(immediate) operand would need special treatment in several places.
Note that the .s suffix isn't being enabled to have any effect, for
being deprecated. Whereas neither {load} nor {store} pseudo prefixes
make sense here, as the respective operands are inputs (loads) only
anyway, regardless of order. Hence there is (as before) no way for the
programmer to request the alternative encoding to be used for register-
only insns.
Note further that it is always the first original template which is
retained (and altered), to make sure the same encoding as before is
used for register-only insns. This has the slightly odd (but pre-
existing) effect of XOP register-only insns having XOP.W clear, but FMA4
ones having VEX.W set.
The middle operand would have gone entirely unchecked, allowing e.g.
vmovss %xmm0, %esp, %xmm2
to assemble successfully, or e.g.
vmovss %xmm0, $4, %xmm2
causing an internal error. Alongside dealing with this also drop a
related comment, which hasn't been applicable anymore since the
introduction of 3-operand patterns with D set (and which perhaps never
had been logical to be there, as reverse-matched insns don't make it
there in the first place).
When using just slightly non-trivial combinations of .arch, it can be
quite useful to be able to go back to prior state without needing to
re-invoke perhaps many earlier directives and without needing to invoke
perhaps many "negative" ones. Like some other architectures allow
saving (pushing) and restoring (popping) present/prior state.
For now require the same .code<N> to be in effect for ".arch pop" that
was in effect for the corresponding ".arch push".
Also change the global "no_cond_jump_promotion" to be bool, to match the
new struct field.
I never really understood upon what basis ".arch .no*" options were made
available. Let's not have any "criteria" at all, and simply allow
disabling of all of them. Then we also have all data for a sub-arch in
a single place, as we now only need a single table.
So far there was no way to reset the architecture to that assembly would
start with in the absence of any overrides (command line or directives).
Note that for Intel MCU "default" is merely an alias of "iamcu".
While there also zap a stray @item from the doc section, as noticed
when inspecting the generated output (which still has some quirks, but
those aren't easy to address without re-flowing almost the entire
section).
While it may not be necessary in i386_target_format() (but then setting
the variable to NULL also wouldn't be necessary), at least in the other
cases strings may already have accumulated.
This is in preparation of dropping the leading . from the strings.
While there also move PROCESSOR_GENERIC{32,64} from the middle of AMD
entries to near the top.
Putting individual elements behind macros, besides (imo) improving
readability, will make subsequent (and likely also future) changes less
intrusive.
Utilize this right away to pack the table a little more tightly, by
converting "skip" to bool and putting it earlier in a group of bitfields
together with "len".
Lots of memory used in gas should go on this obstack. The patch also
frees all the gas obstacks on exit, which isn't a completely trivial
task.
* subsegs.c (alloc_seginfo): New function.
(subseg_change, subseg_get): Use it.
(subsegs_end): New function.
* as.h (subsegs_end): Declare.
* output-file.c: Include subsegs.h
(stash_frchain_obs): New function.
(output_file_close): Save obstacks attached to output bfd before
closing. Call subsegs_end with the array of obstacks.
The only case where 64-bit code uses non-sign-extended (can also be
considered zero-extended) displacements is when an address size override
is in place for a memory operand (i.e. particularly excluding
displacements of direct branches, which - if at all - are controlled by
operand size, and then are still sign-extended, just from 16 bits).
Hence the distinction in templates is unnecessary, allowing code to be
simplified in a number of places. The only place where logic becomes
more complicated is when signed-ness of relocations is determined in
output_disp().
The other caveat is that Disp64 cannot be specified anymore in an insn
template at the same time as Disp32. Unlike for non-64-bit mode,
templates don't specify displacements for both possible addressing
modes; the necessary adjustment to the expected ones has already been
done in match_template() anyway (but of course the logic there needs
tweaking now). Hence the single template so far doing so is split.
Commit 7d5e4556a3 rendered the check near the end of what is now
i386_finalize_displacement() entirely dead for AT&T mode, since for
operands involving a displacement .unspecified will always be set. But
the logic there is bogus anyway - Intel syntax operand size specifiers
are of no interest there either. The only thing which matters in the
"displacement only" determination is .baseindex.
Of course when masking displacement kinds we should not at the same time
also mask off other attributes.
Furthermore the type mask returned by lex_got() also needs to be
adjusted: The only case where we want Disp32 (rather than Disp32S) is
when dealing with 32-bit addressing mode in 64-bit code.
There are two related problems here: The use of "addr32" on a direct
branch would, besides causing a warning, result in operands to be
permitted which mistakenly are refused without "addr32". Plus at some
point not too long ago I'm afraid it may have been me who regressed the
relocation addends emitted for such branches. Correct both problems,
adding a testcase to guard against regressing this again.
The function aarch64_print_operand (aarch64-opc.c) is responsible for
converting an instruction operand into the textual representation of
that operand.
In some cases, a comment is included in the operand representation,
though this (currently) only happens for the last operand of the
instruction.
In a future commit I would like to enable the new libopcodes styling
for AArch64, this will allow objdump and GDB[1] to syntax highlight
the disassembler output, however, having operands and comments
combined in a single string like this makes such styling harder.
In this commit, I propose to extend aarch64_print_operand to take a
second buffer. Any comments for the instruction are written into this
extra buffer. The two callers of aarch64_print_operand are then
updated to pass an extra buffer, and print any resulting comment.
In this commit no styling is added, that will come later. However, I
have adjusted the output slightly. Before this commit some comments
would be separated from the instruction operands with a tab character,
while in other cases the comment was separated with two single spaces.
After this commit I use a single tab character in all cases. This
means a few test cases needed updated. If people would prefer me to
move everyone to use the two spaces, then just let me know. Or maybe
there was a good reason why we used a mix of styles, I could probably
figure out a way to maintain the old output exactly if that is
critical.
Other than that, there should be no user visible changes after this
commit.
[1] GDB patches have not been merged yet, but have been posted to the
GDB mailing list:
https://sourceware.org/pipermail/gdb-patches/2022-June/190142.html
To support feature gate like Smstateen && H, this commit adds certain
CSR feature gate handling. It also changes how RV32-only CSRs are
handled for cleanliness.
gas/ChangeLog:
* config/tc-riscv.c (riscv_csr_address): Add CSR feature gate
handling for H. Change handling on RV32.
Commit 04f096fb9e ("Move the xc16x target to the obsolete list") moved
the architecture from the "obsolete but still available" to the
"obsolete / support removed" list in config.bfd, making the architecture
impossible to enable (except maybe via "enable everything" options").
Note that I didn't touch */po/*.po{,t} on the assumption that these
would be updated by some (half)automatic means.
This patch has been pending for almost a year... However, I noticed that
llvm can already re-order the extensions, even if they are out of orders.
Not really sure if they can also re-order the single letter extensions,
but at least we can do this for the multi-letter extensions in binutils.
bfd/
* elfxx-riscv.c (riscv_parse_prefixed_ext): Removed the code which are
used to check the prefixed extension orders.
gas/
* testsuite/gas/riscv/march-fail-order-x-z.d: Removed since we will help
tp reorder the prefixed extensions for now.
* testsuite/gas/riscv/march-fail-order-x-z.l: Likewise.
* testsuite/gas/riscv/march-fail-order-x.d: Likewise.
* testsuite/gas/riscv/march-fail-order-x.l: Likewise.
* testsuite/gas/riscv/march-fail-order-z.d: Likewise.
* testsuite/gas/riscv/march-fail-order-z.l: Likewise.
According to the picture 28.1 in the current ISA spec, h is no larger the
multi-letter extension, it is a single extension after v. Therefore, this
patch fix the implementation, and use the single h to control hypervisor
CSRs and instructions, which we promised to do before.
bfd/
* elfxx-riscv.c (riscv_supported_std_ext): Added h with version 1.0 after v.
(riscv_supported_std_h_ext): Removed.
(riscv_all_supported_ext): Updated since riscv_supported_std_h_ext is removed.
(riscv_prefix_ext_class): Removed RV_ISA_CLASS_H.
(parse_config): Updated since riscv_prefix_ext_class is removed.
(riscv_recognized_prefixed_ext): Likewise.
(riscv_get_default_ext_version): Likewise.
(riscv_multi_subset_supports): Handle INSN_CLASS_H for hypervisor instructions.
(riscv_multi_subset_supports_ext): Likewise.
gas/
* config/tc-riscv.c (riscv_csr_class): Added CSR_CLASS_H and CSR_CLASS_H_32 for
hypervisor CSRs.
(riscv_csr_address): Likewise.
* testsuite/gas/riscv/csr-version-1p10.d: Updated since hypervisor CSRs are
controlled by single h extension for now.
* testsuite/gas/riscv/csr-version-1p10.l: Likewise.
* testsuite/gas/riscv/csr-version-1p11.d: Likewise.
* testsuite/gas/riscv/csr-version-1p11.l: Likewise.
* testsuite/gas/riscv/csr-version-1p12.d: Likewise.
* testsuite/gas/riscv/csr-version-1p12.l: Likewise.
* testsuite/gas/riscv/csr-version-1p9p1.d: Likewise.
* testsuite/gas/riscv/csr-version-1p9p1.l: Likewise.
* testsuite/gas/riscv/h-ext-32.d: Added h to architecture string.
* testsuite/gas/riscv/h-ext-64.d: Likewise.
* testsuite/gas/riscv/march-fail-single-prefix-h: Removed since h is no
longer multi-letter extension.
* testsuite/gas/riscv/march-fail-unknown-h.d: Likewise.
include/
* opcode/riscv-opc.h: Control hypervisor CSRs by h extension, rather than
the privileged spec verisons.
* opcode/riscv.h (riscv_insn_class): Added INSN_CLASS_H.
opcodes/
* riscv-opc.c (riscv_opcodes): Control hypervisor instructions by h extension.
This commit fixes inconsistent error message format involving compressed
funct<n> fields. In specific, funct6 had an error message with range
0..2^<n> ("0..64") unlike other funct<n> fields with 0..2^<n>-1
(e.g. funct4 with "0..15").
gas/ChangeLog:
* config/tc-riscv.c (riscv_ip): Fix inconsistent error message.
When handling section names in quotes obj_elf_section_name calls
demand_copy_C_string, which puts the name on the gas notes obstack.
Such strings aren't usually freed, since obstack_free frees all more
recently allocated objects as well as its arg. When handling
non-quoted names, obj_elf_section_name mallocs the name. Due to the
mix of allocation strategies it isn't possible for callers to free
names, if that was desirable. Partially fix this by always creating
names on the obstack, which is more efficient anyway. (You still
can't obstack_free on error paths due to the xtensa
tc_canonicalize_section_name.) Also remove a couple of cases where
the name is dup'd for no good reason as far as I know.
PR 29256
* config/obj-elf.c (obj_elf_section_name): Create name on notes
obstack.
(obj_elf_attach_to_group): Don't strdup group name.
(obj_elf_section): Likewise.
(obj_elf_vendor_attribute): Use xmemdup0 rather than xstrndup.
Triggered by a file containing just "#N" or "#A". fgets when hitting
EOF before reading anything returns NULL and does not write to buf.
strchr (buf, '\n') then is reading from uninitialised memory.
* input-file.c (input_file_open): Don't assume buf contains
zero string terminator when fgets returns NULL.
PR 29250
binutils/
* dwarf.c (display_debug_frames): Set col_type[reg] on sizing
pass over FDE to cie->col_type[reg] if CIE specifies reg.
Handle DW_CFA_restore and DW_CFA_restore_extended on second
pass using the same logic. Remove unnecessary casts. Don't
call frame_need_space on second pass over FDE.
gas/
* testsuite/gas/i386/ehinterp.d,
* testsuite/gas/i386/ehinterp.s: New test.
* testsuite/gas/i386/i386.exp: Run it.
MIPS should not be using BFD_RELOC_16 for its R_MIPS_16 relocation,
since R_MIPS_16 specifies a 16-bit field in a 32-bit word.
BFD_RELOC_16, emitted by generic code to handle fixups on 16-bit data
directives, expects fixups to operate on the whole of a 16-bit word.
This patch corrects the problem by using BFD_RELOC_MIPS_16, a new bfd
reloc that is used to generate R_MIPS_16. BFD_RELOC_16 is handled in
md_apply_fix for cases where the fixup can be applied at assembly
time. Like BFD_RELOC_8, BFD_RELOC_16 now has no corresponding object
file relocation, and thus .half, .hword, .short and .dc.w must be
resolved at assembly time. BFD_RELOC_MIPS_REL16 is removed by this
patch since it isn't used.
PR 3243
PR 26542
* reloc.c (BFD_RELOC_MIPS_16): Rename from BFD_RELOC_MIPS_REL16.
* elf32-mips.c (mips_reloc_map): Map BFD_RELOC_MIPS_16 to R_MIPS_16.
* elf64-mips.c (mips_reloc_map): Likewise, delete BFD_RELOC_MIPS_REL16.
* elfn32-mips.c (mips_reloc_map): Likewise.
* libbfd.h: Regenerate.
* bfd-in2.h: Regenerate.
gas/
* config/tc-mips.c (append_insn): Handle BFD_RELOC_MIPS_16.
(macro_build): Likewise.
(mips_percent_op <%half>): Generate BFD_RELOC_MIPS_16.
(md_apply_fix): Handle BFD_RELOC_16 and BFD_RELOC_MIPS_16 when fx_done.
ld/
* testsuite/ld-mips-elf/reloc-local-overflow.d,
* testsuite/ld-mips-elf/reloc-local-overflow.s: Rewrite.
Make it a little more obvious that remap_debug_filename returns an
allocated string (that should be freed) by returning a char * rather
than const char *. Free a few missed cases in dwarf2dbg.c, and free
other memory allocated in dwarf2dbg.c. Also remove static
initialisation of variables and initialise in dwarf2_init instead,
in order to ensure gas state is saner for oss-fuzz.
* remap.c (remap_debug_filename): Remove const from return.
* as.h (remap_debug_filename): Update prototype.
* config/obj-elf.c (obj_elf_ident): Simplify free of
remap_debug_filename output.
* stabs.c (stabs_generate_asm_file): Likewise.
* dwarf2dbg.c (dirs, dirs_in_use, dirs_allocated, current): Don't
initialise statically..
(dwarf2_init): ..do so here, along with most other static vars.
(assign_file_to_slot): Don't set files_allocated until we
succeed in allocating memory.
(purge_generated_debug): Add bool param, free more stuff if true.
(dwarf2_directive_filename): Adjust purge_generated_debug call.
(process_entries): Don't free line_entry here..
(dwarf2_cleanup): ..do so here instead, new function.
(dwarf2_finish): Call dwarf2_cleanup. When chaining together
subseg line entries, unhook entries from old subseg list.
(dwarf2_directive_loc): Free remap_debug_filename string.
(out_dir_and_file_list): Likewise.
(out_debug_str): Likewise.
oss-fuzz hits a flaky crash with a double-free. I think this is due
to gas static state not being reinitialised between testcases, a bug
with oss-fuzz not gas. Anyway, this patch should avoid the problem.
* input-scrub.c (input_scrub_push): Move init of sb_index..
(input_scrub_reinit): ..to here.
Fix the signed overflows by using unsigned variables and detect
overflow at BUG! comment.
* atof-generic.c (atof_generic): Avoid signed integer overflow.
Return ERROR_EXPONENT_OVERFLOW if exponent overflows a long.
This fixes some horrible code using do_scrub_chars. What we had ran
text through do_scrub_chars twice, directly in read_a_source_file and
again via the input_scrub_include_sb call. That's silly, and since
do_scrub_chars is a state machine, possibly wrong. More silliness is
evident in the temporary malloc'd buffer for do_scrub_chars output,
which should have been written directly to sbuf.
So, get rid of the do_scrub_chars call and support functions, leaving
scrubbing to input_scrub_include_sb. I did wonder about #NO_APP
overlapping input_scrub_next_buffer buffers, but that should only
happen if the string starts in one file and finishes in another.
* read.c (scrub_string, scrub_string_end): Delete.
(scrub_from_string): Delete.
(read_a_source_file): Rewrite #APP processing.
It is possible for sb_scrub_and_add_sb to not consume all of the input
string buffer. If this happens for reasons explained in the comment,
do_scrub_chars can leave pointers to the string buffer for the next
call. This patch fixes that by ensuring the input is drained. Note
that the behaviour for an empty string buffer is also changed,
avoiding another do_scrub_chars bug where empty input and single char
sized output buffers could result in a write past the end of the
output.
sb.c (sb_scrub_and_add_sb): Loop until all of input sb is
consumed.
git commit 202be274a4 went a little wild in removing trailing spaces
in gas/testsuite/gas/i386/{secidx.d,secrel.d}, causing
x86_64-w64-mingw32 +FAIL: i386 secrel reloc
x86_64-w64-mingw32 +FAIL: i386 secidx reloc
I could have just replaced the trailing space, but let's fix the
objdump output instead. Touches lots of testsuite files.
The following test fails on the armeb-gnu-eabi target:
FAIL: Unwind information for Armv8.1-M.Mainline PACBTI extension
This patch adjusts the expected output for big endian.
The zhinx extension is a sub-extension in zfinx, corresponding to
zfh extension but use GPRs instead of FPRs.
This patch expanded the zfh insn class define, since zfh and zhinx
use the same opcodes, thanks for Nelson's works.
changelog in V2: Add missing classes of 'zfh' and 'zhinx' in
"riscv_multi_subset_supports_ext".
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): New extensions.
(riscv_multi_subset_supports_ext): New extensions.
gas/ChangeLog:
* testsuite/gas/riscv/fp-zhinx-insns.d: New test.
* testsuite/gas/riscv/fp-zhinx-insns.s: New test.
include/ChangeLog:
* opcode/riscv.h (enum riscv_insn_class): New INSN classes.
opcodes/ChangeLog:
* riscv-opc.c: Modify INSN_CLASS.
While working on another patch[1] I had need to touch this code in
i386-dis.c:
ins->obufp = ins->mnemonicendp;
for (i = strlen (ins->obuf) + prefix_length; i < 6; i++)
oappend (ins, " ");
oappend (ins, " ");
(*ins->info->fprintf_styled_func)
(ins->info->stream, dis_style_mnemonic, "%s", ins->obuf);
What this code does is add whitespace after the instruction mnemonic
and before the instruction operands.
The problem I ran into when working on this code can be seen by
assembling this input file:
.text
nop
retq
Now, when I disassemble, here's the output. I've replaced trailing
whitespace with '_' so that the issue is clearer:
Disassembly of section .text:
0000000000000000 <.text>:
0: 90 nop
1: c3 retq___
Notice that there's no trailing whitespace after 'nop', but there are
three spaces after 'retq'!
What happens is that instruction mnemonics are emitted into a buffer
instr_info::obuf, then instr_info::mnemonicendp is setup to point to
the '\0' character at the end of the mnemonic.
When we emit the whitespace, this is then added starting at the
mnemonicendp position. Lets consider 'retq', first the buffer is
setup like this:
'r' 'e' 't' 'q' '\0'
Then we add whitespace characters at the '\0', converting the buffer
to this:
'r' 'e' 't' 'q' ' ' ' ' ' ' '\0'
However, 'nop' is actually an alias for 'xchg %rax,%rax', so,
initially, the buffer is setup like this:
'x' 'c' 'h' 'g' '\0'
Then in NOP_Fixup we spot that we have an instruction that is an alias
for 'nop', and adjust the buffer to this:
'n' 'o' 'p' '\0' '\0'
The second '\0' is left over from the original buffer contents.
However, when we rewrite the buffer, we don't afjust mnemonicendp,
which still points at the second '\0' character.
Now, when we insert whitespace we get:
'n' 'o' 'p' '\0' ' ' ' ' ' ' ' ' '\0'
Notice the whitespace is inserted after the first '\0', so, when we
print the buffer, the whitespace is not printed.
The fix for this is pretty easy, I can change NOP_Fixup to adjust
mnemonicendp, but now a bunch of tests start failing, we now produce
whitespace after the 'nop', which the tests don't expect.
So, I could update the tests to expect the whitespace....
...except I'm not a fan of trailing whitespace, so I'd really rather
not.
Turns out, I can pretty easily update the whitespace emitting code to
spot instructions that have zero operands and just not emit any
whitespace in this case. So this is what I've done.
I've left in the fix for NOP_Fixup, I think updating mnemonicendp is
probably a good thing, though this is not really required any more.
I've then updated all the tests that I saw failing to adjust the
expected patterns to account for the change in whitespace.
[1] https://sourceware.org/pipermail/binutils/2022-April/120610.html
bfd_hostptr_t is defined as a type large enough to hold either a long
or a pointer. It mostly appears in the coff backend code in casts.
include/coff/internal.h struct internal_syment and union
internal_auxent have the only uses in data structures, where
comparison with include/coff/external.h and other code reveals that
the type only needs to be large enough for a 32-bit integer or a
pointer. That should mean replacing with uintptr_t is OK.
Requiring C99 means that uses of bfd_uint64_t can be replaced with
uint64_t, and similarly for bfd_int64_t, BFD_HOST_U_64_BIT, and
BFD_HOST_64_BIT. This patch does that, removes #ifdef BFD_HOST_*
and tidies a few places that print 64-bit values.
MASM doesn't support the separate operand form; the modifier belongs
after the instruction instead. Accept this form alongside the original
(now legacy) one. Short of having access to a MASM version to actually
check in how far "after the instruction" is a precise statement in their
documentation, allow both that and the SDM mandated form where the
modifier is on the last register operand (with a possible immediate
operand following).
Sadly the split out function, at least for the time being, needs to cast
away constness at some point, as the two callers disagree in this
regard.
Adjust some, but not all of the testcases.
As a preparatory step to allowing proper non-operand forms of specifying
embedded rounding / SAE, convert the internal representation to non-
operand form. While retaining properties (and in a few cases perhaps
providing more meaningful diagnostics), this means doing away with a few
hundred standalone templates, thus - as a nice side effect - reducing
memory consumption / cache occupancy.
MASM doesn't consider {sae} and alike a separate operand; it is attached
to the last register operand instead, just like spelled out by the SDM.
Make the disassembler follow this first, before also adjusting the
assembler (such that it'll be easy to see that the assembler change
doesn't alter generated code).
MASM doesn't support the {1to<n>} form; DWORD BCST (paralleling
DWORD PTR) and alike are to be used there instead. Accept these forms
alongside the original (now legacy) ones.
Acceptance of the original {1to<n>} operand suffix is retained both for
backwards compatibility and to disambiguate VFPCLASSP{S,D,H} and vector
conversions with shrinking element sizes. I have no insight (yet) into
how MASM expects those to be disambiguated.
Adjust some, but not all of the testcases.
MASM doesn't support the {1to<n>} form; DWORD BCST (paralleling
DWORD PTR) and alike are to be used there instead. Make the disassembler
follow this first, before also adjusting the assembler (such that it'll
be easy to see that the assembler change doesn't alter generated code).
For VFPCLASSP{S,D,H} and vector conversions with shrinking element sizes
the original {1to<n>} operand suffix is retained, to disambiguate
output. I have no insight (yet) into how MASM expects those to be
disambiguated.
Whilst reviewing Luis' proposed change to s_arm_unwind_save_mixed
yesterday I noticed that we were making use of __builting_clzl
directly within the main function, which is not guaranteed to be
portable. Whilst studying the code further, I also realized that it
could be rewritten without using it and also reworked to remove a lot
of unnecessary iterations steps. So this patch does that (and also
removes the source of the warning that Luis was trying to fix).
Finally, with the rewrite we can also simplify the caller of this
routine as the new version can handle all the cases directly.
* config/tc-arm.c (s_arm_unwind_save_mixed): Rewrite without
using __builtin_clzl.
(s_arm_unwind_save): Simplify logic for simple/mixed register saves.
This commit makes RV32 + 'Q' extension (version 2.2 or later) not
conflicting since this combination is no longer prohibited by the
specification.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_parse_check_conflicts): Remove conflict
detection that prohibits RV32Q on 'Q' version 2.2 or later.
gas/ChangeLog:
* testsuite/gas/riscv/march-fail-rv32iq.d: Removed.
* testsuite/gas/riscv/march-fail-rv32iq.l: Likewise.
* testsuite/gas/riscv/march-fail-rv32iq2p0.d: New test
showing RV32IQ fails on 'Q' extension version 2.0.
* testsuite/gas/riscv/march-fail-rv32iq2p0.l: Likewise.
* testsuite/gas/riscv/march-fail-rv32iq2.d: Likewise.
* testsuite/gas/riscv/march-fail-rv32iq-isa-2p2.d: New test
showing RV32IQ fails on ISA specification version 2.2.
* testsuite/gas/riscv/march-ok-rv32iq2p2.d: New test
showing RV32IQ succesds on 'Q' extension version 2.2.
* testsuite/gas/riscv/march-ok-rv32iq-isa-20190608.d: New test
showing RV32IQ succesds on ISA specification 20190608.
Per Power ISA Version 3.1B 3.3.12, isel uses BC field rather than CRB
field present in binutils sources. Also, per 1.6.2, BC has the same
semantics as BA and BB fields, so this should keep the same flags and
mask, only with the different offset.
opcodes/
* ppc-opc.c
(BC): Define new field, with the same definition as CRB field,
but with the PPC_OPERAND_CR_BIT flag present.
gas/
* testsuite/gas/ppc/476.d: Update.
* testsuite/gas/ppc/a2.d: Update.
* testsuite/gas/ppc/e500.d: Update.
* testsuite/gas/ppc/power7.d: Update.
With the upcoming SVP64 extension[0] to PowerPC architecture, it became
evident that PowerPC operand indices no longer fit 8 bits. This patch
switches the underlying type to uint16_t, also introducing a special
typedef so that any future extension goes even smoother.
[0] https://libre-soc.org
include/
* opcode/ppc.h (ppc_opindex_t): New typedef.
(struct powerpc_opcode): Use it.
(PPC_OPINDEX_MAX): Define.
gas/
* write.h (struct fix): Increase size of fx_pcrel_adjust.
Reorganise.
* config/tc-ppc.c (insn_validate): Use ppc_opindex_t for operands.
(md_assemble): Likewise.
(md_apply_fix): Likewise. Mask fx_pcrel_adjust with PPC_OPINDEX_MAX.
(ppc_setup_opcodes): Adjust opcode index assertion.
opcodes/
* ppc-dis.c (skip_optional_operands): Use ppc_opindex_t for
operand pointer.
(lookup_powerpc, lookup_prefix, lookup_vle, lookup_spe2): Likewise.
(print_insn_powerpc): Likewise.
As fmv.x.q and fmv.q.x instructions are RV128-only (not RV64-only),
it should be removed until RV128 support for GNU Binutils is required
again.
gas/ChangeLog:
* testsuite/gas/riscv/fmv.x.q-rv64-fail.d: New failure test.
* testsuite/gas/riscv/fmv.x.q-rv64-fail.l: Likewise.
* testsuite/gas/riscv/fmv.x.q-rv64-fail.s: Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_FMV_X_Q, MASK_FMV_X_Q,
MATCH_FMV_Q_X, MASK_FMV_Q_X): Remove RV128-only instructions.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Remove RV128-only instructions.
The current assembler accepts system registers FPCXTNS and FPCXTS for Armv8.1-M
Mainline Instructions VSTR, VLDR, VMRS and VMSR.
Assembler should be also allowing FPCXT_NS, fpcxt_ns, fpcxtns, FPCXT_S, fpcxt_s
and fpcxts. This patch fixes the issue.
Like the placeholder types added in 04dfe7aa52 ("Arm64: follow-on to
PR gas/27217 fix"), these are also placeholders which are subsequently
resolved (albeit later, hence this being a separate issue). As for the
resolved types 1 is returned, these pseudo-relocs should also have 1
returned to force retaining of the [eventual] relocations. This is also
spelled out individually for each of them in md_apply_fix().
PR gas/27217
Prior to trying to address PR gas/28888 I noticed anomalies in how
certain insns would / wouldn't be affected in similar ways.
Commit eac4eb8ecb ("Fix a problem assembling AArch64 sources when a
relocation is generated against a symbol that has a defined value") had
two copy-and-paste mistakes, passing the wrong type to
aarch64_force_reloc().
It further failed to add placeholder relocation types to that function's
block of case labels leading to a return of 1. While not of interest for
aarch64_force_relocation() (these placeholders are resolved right in
parse_operands()), calls to aarch64_force_reloc() happen before that
resolution would take place.
* config/tc-arm.c (parse_reg_list): Add handling of mixed register
types.
(reg_names): Enumerate pseudoregister according to mapped physical
register number.
(s_arm_unwind_save_pseudo): Modify function signature.
(s_arm_unwind_save_core): Likewise.
(s_arm_unwind_save_mixed): New function.
(s_arm_unwind_save): Generate register list mask to pass to nested
functions.
* testsuite/gas/arm/unwind-pacbti-m.s: Expand test for mixed
register type lists.
* testsuite/gas/arm/unwind-pacbti-m.d: Likewise.
* testsuite/gas/arm/unwind-pacbti-m-readelf.d: Likewise.
Compilers would put decimal numbers there, so I think we should treat
finding octal numbers the same as finding bignums - ignore them as
actually being comments of some very specific form.
Any construct which to the scrubber looks like a C preprocessor
line/file "directive" is converted to .linefile, but the amount of
checking the scrubber does is minimal (albeit it does let through only
decimal digits for the line part of the contruct). Since the scrubber
conversion is further tied to # being a line comment character, anything
which upon closer inspection turns out not to be a line/file "directive"
is supposed to be treated as a comment, i.e. ignored. Therefore we
cannot use get_absolute_expression(), as this may raise errors. Open-
code the function instead, treating everything not resulting in
O_constant as a comment as well.
Furthermore also bounds-check the parsed value. This bounds check tries
to avoid implementation defined behavior (which may be the raising of an
implementation defined signal), but for now makes the assumption that
int has less than 64 bits. The way bfd_signed_vma (which is what offsetT
aliases) is defined in bfd.h for the BFD64 case I cannot really see a
clean way of avoiding this assumption. Omitting the #ifdef, otoh, would
risk "condition is always false" warnings by compilers.
Convert get_linefile_number() to return bool at this occasion as well.
do_repeat_with_expander() already deals with the "no expander" case
quite fine, so there's really little point having two functions. What it
lacks compared with do_repeat() is a call to sb_build(), which can
simply be moved (and the then redundant sb_new() be avoided). Along with
this moving also flip if the main if()'s condition such that the "no
expander" case is handled first.
When assembling code previously pre-processed by a C compiler, long
enough comments may have been collapsed into "# <line> <file>"
constructs. If we skip these, line numbers (and possibly even file
names) will be off / wrong in both diagnostics and debug info.
First of all convert to switch(), in preparation of adding another
directive here which may not be ignored. While doing so drop dead code:
A string the first two characters of which do not match "if" also wont
match "ifdef" or "ifndef".
s390_insert_operand ()'s val, min and max are encoded PCRel32 values
and need to be left-shifted by 1 before being shown to the user.
Left-shifting negative values is undefined behavior in C, but the
current code does not try to prevent it, causing UBSan to complain.
Fix by casting the values to their unsigned equivalents before
shifting.
The new test failed on s390-linux due to bfd_sprintf_vma trimming
output to 32 bits for 32-bit targets. The test was faulty anyway,
expecting zero as the min end of the range is plainly wrong, but
that's what you get if you cast min to int.
* config/tc-s390.c (s390_insert_operand): Print range error using
PRId64.
* testsuite/gas/s390/zarch-z900-err.l: Correct expected output.
as does not accept instructions like brasl %r0,.-0x100000000, because
of two problems with the generic overflow check:
1. PCRel32 operands are signed, but are treated as unsigned.
2. The allowed range for these operands is [-(1 << 32), (1 << 32) - 1],
and not [-(1 << 31), (1 << 31) - 1].
Fix both by disabling the generic overflow check - it's not needed,
because s390_insert_operand () performs its own.
gas/
* config/tc-s390.c (md_gather_operands): Set fx_no_overflow.
* testsuite/gas/s390/s390.exp: Add zarch-z900-err.
* testsuite/gas/s390/esa-z900.d: New test.
* testsuite/gas/s390/esa-z900.s: New test.
* testsuite/gas/s390/zarch-z900-err.l: New test.
* testsuite/gas/s390/zarch-z900-err.s: New test.
So far an SAE-only specifier was accepted for static-rounding insns,
while SAE-only insns didn't accept static rounding specifiers. If
anything it would make sense the other way around, allowing SAE-only
insns to have the (ignored) rounding mode specified individually rather
than globally via -mevexrcig=. But for now make things match the SDM.
The way SAE templates are constructed was always puzzling me (including
the need for separate templates in the first place), and expressing the
extzra attribute via Imm8 actually has a bad effect: Ordinary immediates
would also be accepted, leading to an extra byte being added after the
instruction (i.e. generating bad code). Before re-working this (in
particular to accept proper Intel syntax there), fix the immediate issue
by adding the so far missing check.
For an unclear reason corresponding AVX512F tests were apparently not
cloned or used as reference here, and instead the bogus legacy forms of
the insns (with the embedded rounding specifier not last) were used.
It's not just REX.W which is ignored with opcode 0x90. The same goes for
REX.R and REX.X as well as empty REX. None of these are forms of
"xchg %eax,%eax" (which would mean zero-extending %eax to %rax), so they
also shouldn't be disassembled this way.
While there simplify things: A single hook function suffices, thus
making it unnecessary to keep two expressions in sync. And checking
ins->address_mode for mode_64bit also is unnecessary, as "rex" can be
non-zero only in that case anyway.
Before the change tc-m68k maintained a list of seen labels.
Alignment check traversed label list to resolve symbol to label.
This caused quadratic slowdown as each symbol was checked against
each label. Worst affected files are the ones built with debugging
enabled as DWARF generates many labels.
The change embeds auxiliary label information right into symbol using
TC_SYMFIELD_TYPE.
Before the change test from PR 29058 did not finish in 10 minutes. After
the change it finishes in 2 seconds.
gas/ChangeLog:
PR 29058
* config/tc-m68k.h (TC_SYMFIELD_TYPE): define as m68k_tc_sy.
* config/tc-m68k.c (m68k_frob_label): Use TC_SYMFIELD_TYPE to
store label information.
With the sole user of the return value gone, convert the return type to
void. This in turn allows simplifying another construct, by moving it
slightly later in the function.
These were used originally to represent "# <line> <file>" constructs
inserted by (typically) compilers when pre-processing. Quite some time
ago they were replaced by .linefile though. Since the original
directives were never documented, we ought to be able to remove support
for them. As a result in a number of case function parameter aren't used
anymore and can hence be dropped.
Commit 7992631e8c ("gas/Dwarf: improve debug info generation from .irp
and alike blocks"), while dealing okay with actual assembly source files
not using .file/.line and alike outside but not inside of .macro, has
undue effects when the logical file/line pair was already overridden:
Line numbers would continuously increment while processing the expanded
macro, while the goal of the PR gas/16908 workaround is to keep the
expansion associated with the line invoking the macro. However, as soon
as enough state was overridden _inside_ the macro to cause as_where() to
no longer fall back top as_where_physical(), honor this by resuming the
bumping of the logical line number.
Note that from_sb_is_expansion's initializer was 1 for an unknown
reason. While renaming the variable and changing its type, also change
the initializer to "expanding_none", which would have been "0" in the
original code. Originally the initializer value itself wasn't ever used
anyway (requiring sb_index != -1), as it necessarily had changed in
input_scrub_include_sb() alongside setting sb_index to other than -1.
Strictly speaking input_scrub_insert_line() perhaps shouldn't use
expanding_none, yet none of the other enumerators fit there either. And
then strictly speaking that function probably shouldn't exist in the
first place. It's used only by tic54x.
Commit 7992631e8c ("gas/Dwarf: improve debug info generation from .irp
and alike blocks"), while dealing okay with actual assembly source files
not using .file/.line and alike outside but not inside of .irp et al,
has undue effects when the logical file/line pair was already
overridden: Line numbers would continuously increment upon every
iteration, thus potentially getting far off. Furthermore it left it to
the user to actually insert .file/.line inside such constructs. Note
though that before aforementioned change things weren't pretty either:
Diagnostics (and debug info) would be associated with the directive
terminating the iteration construct, rather than with the actual lines.
Handle this automatically by simply latching the present line and then
re-instating coordinates first thing on every iteration; note that the
file can't change from what was previously pushed on the scrubber's
state stack, and hence can be taken from there by using a new flavor of
.linefile (which is far better memory-footprint-wise than recording the
full path in the inserted directive). (This then leaves undisturbed any
file/line control occurring in the body of the construct, as these will
only be seen and processed afterwards.)
As the comment says, hppa doesn't support use of BFD_RELOC_* in
.reloc directives. Using xfail can result in a spurious XPASS result
as BFD_RELOC values change.
* testsuite/gas/elf/pr27228.d: Change xfail to notarget for hppa.
bfd * coff-i386.c (in_reloc_p): Add R_SECTION.
(howto_table): Add R_SECTION.
(coff_pe_i386_relocation_section): Add support for R_SECTION.
(coff_i386_reloc_type_lookup): Add support for
BFD_RELOC_16_SECCIDX.
* coff-x86_64.c (in_reloc_p): Add R_SECTION.
(howto_table): Add R_SECTION.
(coff_pe_amd64_relocation_section): Add support for R_SECTION.
(coff_amd64_reloc_type_lookup): Add support for
BFD_RELOC_16_SECCIDX.
* reloc.c: Add BFD_RELOC_16_SECIDX.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas * config/tc-i386.c (pe_directive_secidx): New function.
(md_pseudo_table): Add support for secidx.
(x86_cons_fix_new): Likewise.
(tc_gen_reloc): Likewise.
* expr.c (op_rank): Add O_secidx.
* expr.h (operatorT): Likewise.
* symbols.c (resolve_symbol_value): Add support for O_secidx.
* testsuite/gas/i386/secidx.s: New test source file.
* testsuite/gas/i386/secidx.d: New test driver file.
* testsuite/gas/i386/i386.exp: Run new test.
include * coff/i386.h: Define R_SECTION.
* coff/x86_64.h: Likewise.
ld * testsuite/ld-pe/secidx1.s: New test source file.
* testsuite/ld-pe/secidx2.s: New test source file.
* testsuite/ld-pe/secidx.d: New test driver file.
* testsuite/ld-pe/secidx_64.d: New test driver file.
* testsuite/ld-pe/pe.exp: Add new tests.
To help tools like addr2line looking up function names, in particular
when dealing with e.g. PE/COFF binaries (linked from ELF objects), where
there's no ELF symbol table to fall back to, emit minimalistic
information for functions marked as such and having their size
specified.
Notes regarding the restriction to (pure) ELF:
- I realize this is a layering violation; I don't see how to deal with
that in a better way.
- S_GET_SIZE(), when OBJ_MAYBE_ELF is defined, looks wrong: Unlike
S_SET_SIZE() it does not check whether the hook is NULL.
- symbol_get_obj(), when OBJ_MAYBE_ELF is defined, looks unusable, as
its return type can only ever be one object format's type (and this
may then not be ELF's).
The new testcases are limited to x86 because I wanted to include the
case where function size can't be determined yet at the time Dwarf2 info
is generated. As .nops gains support by further targets, they could also
be added here then (with, as necessary, expecations suitably relaxed to
cover for insn size differences).
