PR 28436
* config/tc-arm.c (do_vfp_nsyn_push_pop_check): New function.
(do_vfp_nsyn_pop): Use the new function.
(do_vfp_nsyn_push): Use the new function.
* testsuite/gas/arm/v8_1m-mve.s: Add new instructions.
* testsuite/gas/arm/v8_1m-mve.d: Updated expected disassembly.
Unaligned load/store instructions on aligned memory or register are as
fast as aligned load/store instructions on modern Intel processors. Add
a command-line option, -muse-unaligned-vector-move, to x86 assembler to
encode encode aligned vector load/store instructions as unaligned
vector load/store instructions.
* NEWS: Mention -muse-unaligned-vector-move.
* config/tc-i386.c (use_unaligned_vector_move): New.
(encode_with_unaligned_vector_move): Likewise.
(md_assemble): Call encode_with_unaligned_vector_move for
-muse-unaligned-vector-move.
(OPTION_MUSE_UNALIGNED_VECTOR_MOVE): New.
(md_longopts): Add -muse-unaligned-vector-move.
(md_parse_option): Handle -muse-unaligned-vector-move.
(md_show_usage): Add -muse-unaligned-vector-move.
* doc/c-i386.texi: Document -muse-unaligned-vector-move.
* testsuite/gas/i386/i386.exp: Run unaligned-vector-move and
x86-64-unaligned-vector-move.
* testsuite/gas/i386/unaligned-vector-move.d: New file.
* testsuite/gas/i386/unaligned-vector-move.s: Likewise.
* testsuite/gas/i386/x86-64-unaligned-vector-move.d: Likewise.
Add aliases for the non-immediate mnemonics of b{set,clr,inv,ext} to
yencode the respective immediate insn b{set,clr,inv,ext}i when the
second source operand is an immediate.
2021-01-11 Philipp Tomsich <philipp.tomsich@vrull.eu>
gas/
* testsuite/gas/riscv/b-ext.d: Add tests.
* testsuite/gas/riscv/b-ext.s: Likewise.
* testsuite/gas/riscv/b-ext-64.d: Likewise.
* testsuite/gas/riscv/b-ext-64.s: Likewise.
opcodes/
* riscv-opc.c (riscv_opcodes): Add aliases for Zbs.
Suggested-by: Jan Beulich <jbeulich@suse.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Patch is adding Cortex-R52+ as 'cortex-r52plus' command line
flag for -mcpu option.
bfd/
* cpu-arm.c: New Cortex-R52+ CPU.
gas/
* NEWS: Update docs.
* config/tc-arm.c: New Cortex-R52+ CPU.
* doc/c-arm.texi: Update docs.
* testsuite/gas/arm/cpu-cortex-r52plus.d: New test.
We need to allow adding numbers in the prefixed extension names, since
the zve<32,64><d,f,x> extensions are included in the forzen rvv v1.0 spec
recently. But there are two restrictions as follows,
* The extension name ends with <number>p is invalid, since this may
be confused with extension with <number>.0 version. We report errors
for this case.
Invalid format: [z|h|s|zvm|x][0-9a-z]+[0-9]+p
* The extension name ends with numbers is valid, but the numbers will
be parsed as major version, so try to avoid naming extensions like this.
bfd/
* elfxx-riscv.c (riscv_recognized_prefixed_ext): Renamed from
riscv_valid_prefixed_ext/
(riscv_parsing_subset_version): The extensions end with <number>p
is forbidden, we already report the detailed errors in the
riscv_parse_prefixed_ext, so clean the code and unused parameters.
(riscv_parse_std_ext): Updated.
(riscv_parse_prefixed_ext): Rewrite the parser to allow numbers
in the prefixed extension names.
gas/
* testsuite/gas/riscv/march-fail-invalid-x-01.d: New testcases.
* testsuite/gas/riscv/march-fail-invalid-x-02.d: Likewise.
* testsuite/gas/riscv/march-fail-invalid-z-01.d: Likewise.
* testsuite/gas/riscv/march-fail-invalid-z-02.d: Likewise.
* testsuite/gas/riscv/march-fail-invalid.l: Likewise.
* testsuite/gas/riscv/march-fail-version-x.d: Removed.
* testsuite/gas/riscv/march-fail-version-z.d: Likewise.
* testsuite/gas/riscv/march-fail-version.l: Likewise.
Don't print broadcast for scalar_mode, and print {bad} for invalid broadcast.
gas/
PR binutils/28381
* testsuite/gas/i386/bad-bcast.s: Add a new testcase.
* testsuite/gas/i386/bad-bcast.d: Likewise.
* testsuite/gas/i386/bad-bcast-intel.d: New.
opcodes/
PR binutils/28381
* i386-dis.c (static struct): Add no_broadcast.
(OP_E_memory): Mark invalid broadcast with no_broadcast=1 and Print "{bad}"for it.
(intel_operand_size): mark invalid broadcast with no_broadcast=1.
(OP_XMM): Mark scalar_mode with no_broadcast=1.
SPR 896 and the mfppr mfppr32, mtppr and mtppr32 extended mnemonics were added
in ISA 2.03, so enable them on POWER5 and later.
opcodes/
* ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
on POWER5 and later.
gas/
* testsuite/gas/ppc/power5.s: New test.
* testsuite/gas/ppc/power5.d: Likewise.
* testsuite/gas/ppc/ppc.exp: Run it.
* testsuite/gas/ppc/power7.s: Remove tests for mfppr, mfppr32, mtppr
and mtppr32.
* testsuite/gas/ppc/power7.d: Likewise.
Required for the expected "CU:" to be emitted for long
source-paths. See binutils/dwarf.c:
if (do_wide || strlen (directory) < 76)
printf (_("CU: %s/%s:\n"), directory, file_table[0].name);
else
printf ("%s:\n", file_table[0].name);
See also commit 5f410aa50c, "testsuite/ld-elf/pr26936.d:
Pass -W."
gas/ChangeLog:
* testsuite/ld-elf/dwarf2-21.d: Pass -W.
This is a testcase for the bug fixed by commit 5b4846283c. When
running the testcase on ia64 targets I found timeouts along with lots
of memory being consumed, due to ia64 gas not tracking text
sub-sections. Trying to add nops for ".nop 16" in ".text 1" resulting
in them being added to subsegment 0, with no increase to subsegment 1
size. This patch also fixes that problem.
Note that the testcase fails on ft32-elf, mn10200-elf, score-elf,
tic5x-elf, and xtensa-elf. The first two are relocation errors, the
last three appear to be the .nop directive failing to emit the right
number of nops. I didn't XFAIL any of them.
* config/tc-ia64.c (md): Add last_text_subseg.
(ia64_flush_insns, dot_endp): Use last_text_subseg.
(ia64_frob_label, md_assemble): Set last_text_subseg.
* testsuite/gas/elf/dwarf2-21.d,
* testsuite/gas/elf/dwarf2-21.s: New test.
* testsuite/gas/elf/elf.exp: Run it.
Mixing compiler generated line info with gas generated line info is
generally just confusing. Also .loc directives with non-zero view
fields might reference a previous .loc. It becomes a little more
tricky to locate that previous .loc if there might be gas generated
line info present too. Mind you, we turn off gas generation of line
info on seeing compiler generated line info, so any reference back
won't hit gas generated line info. At least, if the view info is
sane. Unfortunately, gas needs to handle mangled source.
PR 28149
* dwarf2dbg.c (purge_generated_debug): New function.
(dwarf2_directive_filename): Call the above.
(out_debug_line): Don't segfault after purging.
* testsuite/gas/i386/dwarf2-line-4.d: Update expected output.
* testsuite/gas/i386/dwarf4-line-1.d: Likewise.
* testsuite/gas/i386/dwarf5-line-1.d: Likewise.
* testsuite/gas/i386/dwarf5-line-2.d: Likewise.
gcc-11 and gcc-12 pass -gdwarf-5 to gas, in order to prime gas for
DWARF 5 level debug info. Unfortunately it seems there are cases
where the compiler does not emit a .file or .loc dwarf debug directive
before any machine instructions. (Note that the .file directive
typically emitted as the first line of assembly output doesn't count as
a dwarf debug directive. The dwarf .file has a file number before the
file name string.)
This patch delays allocation of file numbers for gas generated line
debug info until the end of assembly, thus avoiding any clashes with
compiler generated file numbers. Two fixes for test case source are
necessary; A .loc can't use a file number that hasn't already been
specified with .file.
A followup patch will remove all the gas generated line info on
seeing a .file directive.
PR 28149
* dwarf2dbg.c (num_of_auto_assigned): Delete.
(current): Update initialisation.
(set_or_check_view): Replace all accesses to view with u.view.
(dwarf2_consume_line_info): Likewise.
(dwarf2_directive_loc): Likewise. Assert that we aren't generating
line info.
(dwarf2_gen_line_info_1): Don't call set_or_check_view on
gas generated line entries.
(dwarf2_gen_line_info): Set and track filenames for gas generated
line entries. Simplify generation of labels.
(get_directory_table_entry): Use filename_cmp when comparing dirs.
(do_allocate_filenum): New function.
(dwarf2_where): Set u.filename and filenum to -1 for gas generated
line entries.
(dwarf2_directive_filename): Remove num_of_auto_assigned handling.
(process_entries): Update view field access. Call
do_allocate_filenum.
* dwarf2dbg.h (struct dwarf2_line_info): Add filename field in
union aliasing view.
* testsuite/gas/i386/dwarf2-line-3.s: Add .file directive.
* testsuite/gas/i386/dwarf2-line-4.s: Likewise.
* testsuite/gas/i386/dwarf2-line-4.d: Update expected output.
* testsuite/gas/i386/dwarf4-line-1.d: Likewise.
* testsuite/gas/i386/dwarf5-line-1.d: Likewise.
* testsuite/gas/i386/dwarf5-line-2.d: Likewise.
Since the 0x57 is preserved for the vadd.vv instruction in the integration
branch, remove it to make sure the testcase can work.
gas/
* testsuite/gas/riscv/insn.d: Remove 0x57 since it is preserved
for vadd.vv instruction.
* testsuite/gas/riscv/insn.s: Likewise.
DWARF5 allows .file 0 to take an optional directory name. Set the entry
0 of the directory table to the directory name in .file 0.
PR gas/28266
* dwarf2dbg.c (get_directory_table_entry): Add an argument for
the directory name in .file 0 and use it, instead of PWD.
(allocate_filenum): Pass NULL to get_directory_table_entry.
(allocate_filename_to_slot): Pass the incoming dirname to
get_directory_table_entry.
* testsuite/gas/elf/dwarf-5-file0-2.d: New file.
* testsuite/gas/elf/dwarf-5-file0-2.s: Likewise.
* testsuite/gas/elf/elf.exp: Run dwarf-5-file0-2.
The disassembler has support to pretty print values created by an lui/addi
pair, but there is no support for addiw. There is also no support for
c.addi and c.addiw. This patch extends the pretty printing support to
handle these 3 instructions in addition to addi. Existing testcases serve
as tests for the new feature.
opcodes/
* riscv-dis.c (maybe_print_address): New arg wide. Sign extend when
wide is true.
(print_insn_args): Fix calls to maybe_print_address. Add checks for
c.addi, c.addiw, and addiw, and call maybe_print_address for them.
gas/
* testsuite/gas/riscv/insn.d: Update for disassembler change.
* testsuite/gas/li32.d, testsuite/gas/li64.d: Likwise.
* testsuite/gas/lla64.d: Likewise.
PR 28292
gas * config/tc-v850.c (handle_lo16): Also accept
BFD_RELOC_V850_LO16_SPLIT_OFFSET.
* testsuite/gas/v850/split-lo16.s: Add extra line.
* testsuite/gas/v850/split-lo16.d: Update expected disassembly.
opcodes * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
of BFD_RELOC_16.
The .insn directive can let users use their own instructions, or
some new instruction, which haven't supported in the old binutils.
For example, if users want to use sifive cache instruction, they
cannot just write "cflush.d1.l1" in the assembly code, they should
use ".insn i SYSTEM, 0, x0, x10, -0x40". But the .insn directive
may not easy to use for some cases, and not so friendly to users.
Therefore, I believe most of the users will use ".word 0xfc050073",
to encode the instructions directly, rather than use .insn. But
once we have supported the mapping symbols, the .word directives
are marked as data, so disassembler won't dump them as instructions
as usual. I have discussed this with Kito many times, we all think
extend the .insn direcitve to support the hardcode encoding, is the
easiest way to resolve the problem. Therefore, there are two more
.insn formats are proposed as follows,
(original) .insn <type>, <operand1>, <operand2>, ...
.insn <insn-length>, <value>
.insn <value>
The <type> is string, and the <insn-length> and <value> are constants.
gas/
* config/tc-riscv.c (riscv_ip_hardcode): Similar to riscv_ip,
but assembles an instruction according to the hardcode values
of .insn directive.
* doc/c-riscv.texi: Document two new .insn formats.
* testsuite/gas/riscv/insn-fail.d: New testcases.
* testsuite/gas/riscv/insn-fail.l: Likewise.
* testsuite/gas/riscv/insn-fail.s: Likewise.
* testsuite/gas/riscv/insn.d: Updated.
* testsuite/gas/riscv/insn.s: Likewise.
Similar to ARM/AARCH64, we add mapping symbols in the symbol table,
to mark the start addresses of data and instructions. The $d means
data, and the $x means instruction. Then the disassembler uses these
symbols to decide whether we should dump data or instruction.
Consider the mapping-04 test case,
$ cat tmp.s
.text
.option norelax
.option norvc
.fill 2, 4, 0x1001
.byte 1
.word 0
.balign 8
add a0, a0, a0
.fill 5, 2, 0x2002
add a1, a1, a1
.data
.word 0x1 # No need to add mapping symbols.
.word 0x2
$ riscv64-unknown-elf-as tmp.s -o tmp.o
$ riscv64-unknown-elf-objdump -d tmp.o
Disassembly of section .text:
0000000000000000 <.text>:
0: 00001001 .word 0x00001001 # Marked $d, .fill directive.
4: 00001001 .word 0x00001001
8: 00000001 .word 0x00000001 # .byte + part of .word.
c: 00 .byte 0x00 # remaining .word.
d: 00 .byte 0x00 # Marked $d, odd byte of alignment.
e: 0001 nop # Marked $x, nops for alignment.
10: 00a50533 add a0,a0,a0
14: 20022002 .word 0x20022002 # Marked $d, .fill directive.
18: 20022002 .word 0x20022002
1c: 2002 .short 0x2002
1e: 00b585b3 add a1,a1,a1 # Marked $x.
22: 0001 nop # Section tail alignment.
24: 00000013 nop
* Use $d and $x to mark the distribution of data and instructions.
Alignments of code are recognized as instructions, since we usually
fill nops for them.
* If the alignment have odd bytes, then we cannot just fill the nops
into the spaces. We always fill an odd byte 0x00 at the start of
the spaces. Therefore, add a $d mapping symbol for the odd byte,
to tell disassembler that it isn't an instruction. The behavior
is same as Arm and Aarch64.
The elf/linux toolchain regressions all passed. Besides, I also
disable the mapping symbols internally, but use the new objudmp, the
regressions passed, too. Therefore, the new objudmp should dump
the objects corretly, even if they don't have any mapping symbols.
bfd/
pr 27916
* cpu-riscv.c (riscv_elf_is_mapping_symbols): Define mapping symbols.
* cpu-riscv.h: extern riscv_elf_is_mapping_symbols.
* elfnn-riscv.c (riscv_maybe_function_sym): Do not choose mapping
symbols as a function name.
(riscv_elf_is_target_special_symbol): Add mapping symbols.
binutils/
pr 27916
* testsuite/binutils-all/readelf.s: Updated.
* testsuite/binutils-all/readelf.s-64: Likewise.
* testsuite/binutils-all/readelf.s-64-unused: Likewise.
* testsuite/binutils-all/readelf.ss: Likewise.
* testsuite/binutils-all/readelf.ss-64: Likewise.
* testsuite/binutils-all/readelf.ss-64-unused: Likewise.
gas/
pr 27916
* config/tc-riscv.c (make_mapping_symbol): Create a new mapping symbol.
(riscv_mapping_state): Decide whether to create mapping symbol for
frag_now. Only add the mapping symbols to text sections.
(riscv_add_odd_padding_symbol): Add the mapping symbols for the
riscv_handle_align, which have odd bytes spaces.
(riscv_check_mapping_symbols): Remove any excess mapping symbols.
(md_assemble): Marked as MAP_INSN.
(riscv_frag_align_code): Marked as MAP_INSN.
(riscv_init_frag): Add mapping symbols for frag, it usually called
by frag_var. Marked as MAP_DATA for rs_align and rs_fill, and
marked as MAP_INSN for rs_align_code.
(s_riscv_insn): Marked as MAP_INSN.
(riscv_adjust_symtab): Call riscv_check_mapping_symbols.
* config/tc-riscv.h (md_cons_align): Defined to riscv_mapping_state
with MAP_DATA.
(TC_SEGMENT_INFO_TYPE): Record mapping state for each segment.
(TC_FRAG_TYPE): Record the first and last mapping symbols for the
fragments. The first mapping symbol must be placed at the start
of the fragment.
(TC_FRAG_INIT): Defined to riscv_init_frag.
* testsuite/gas/riscv/mapping-01.s: New testcase.
* testsuite/gas/riscv/mapping-01a.d: Likewise.
* testsuite/gas/riscv/mapping-01b.d: Likewise.
* testsuite/gas/riscv/mapping-02.s: Likewise.
* testsuite/gas/riscv/mapping-02a.d: Likewise.
* testsuite/gas/riscv/mapping-02b.d: Likewise.
* testsuite/gas/riscv/mapping-03.s: Likewise.
* testsuite/gas/riscv/mapping-03a.d: Likewise.
* testsuite/gas/riscv/mapping-03b.d: Likewise.
* testsuite/gas/riscv/mapping-04.s: Likewise.
* testsuite/gas/riscv/mapping-04a.d: Likewise.
* testsuite/gas/riscv/mapping-04b.d: Likewise.
* testsuite/gas/riscv/mapping-norelax-04a.d: Likewise.
* testsuite/gas/riscv/mapping-norelax-04b.d: Likewise.
* testsuite/gas/riscv/no-relax-align.d: Updated.
* testsuite/gas/riscv/no-relax-align-2.d: Likewise.
include/
pr 27916
* opcode/riscv.h (enum riscv_seg_mstate): Added.
opcodes/
pr 27916
* riscv-dis.c (last_map_symbol, last_stop_offset, last_map_state):
Added to dump sections with mapping symbols.
(riscv_get_map_state): Get the mapping state from the symbol.
(riscv_search_mapping_symbol): Check the sorted symbol table, and
then find the suitable mapping symbol.
(riscv_data_length): Decide which data size we should print.
(riscv_disassemble_data): Dump the data contents.
(print_insn_riscv): Handle the mapping symbols.
(riscv_symbol_is_valid): Marked mapping symbols as invalid.
Put back 3 aborts where invalid lengths should have been filtered out.
gas/
PR binutils/28247
* testsuite/gas/i386/bad-bcast.s: Add a comment.
opcodes/
PR binutils/28247
* * i386-dis.c (OP_E_memory): Put back 3 aborts.
Some targets, typically embedded without shared libraries, replace the
relocation symbol with a section symbol (see tc_fix_adjustable).
Allow the test to pass for such targets. Fixes the following.
avr-elf +FAIL: symver symver16
d10v-elf +FAIL: symver symver16
dlx-elf +FAIL: symver symver16
ip2k-elf +FAIL: symver symver16
m68k-elf +FAIL: symver symver16
mcore-elf +FAIL: symver symver16
pj-elf +FAIL: symver symver16
s12z-elf +FAIL: symver symver16
visium-elf +FAIL: symver symver16
z80-elf +FAIL: symver symver16
PR gas/28157
* testsuite/gas/symver/symver16.d: Relax reloc match.
Always run fp tests since the size of .tfloat, .ds.x, .dc.x and .dcb.x
directive outputs is always 10 bytes. There is no need for fp-elf32 nor
fp-elf64.
PR gas/28230
* testsuite/gas/i386/fp-elf32.d: Removed.
* testsuite/gas/i386/fp-elf64.d: Likewise.
* testsuite/gas/i386/fp.s: Remove NO_TFLOAT_PADDING codes.
* testsuite/gas/i386/i386.exp: Don't run fp-elf32 nor fp-elf64.
Always run fp.
.tfloat output should always be 10 bytes without padding, independent
of psABIs. In glibc, x86 assembly codes expect 10-byte .tfloat output.
This also reduces .ds.x output and .tfloat output with hex input from
12 bytes to 10 bytes to match .tfloat output.
PR gas/28230
* NEWS: Mention changes of .ds.x output and .tfloat output with
hex input.
* config/tc-i386.c (x86_tfloat_pad): Removed.
* config/tc-i386.h (X_PRECISION_PAD): Changed to 0.
(x86_tfloat_pad): Removed.
* testsuite/gas/i386/fp.s: If NO_TFLOAT_PADDING isn't defined,
add explicit paddings after .tfloat, .ds.x, .dc.x and .dcb.x
directives.
* testsuite/gas/i386/i386.exp (ASFLAGS): Append
"--defsym NO_TFLOAT_PADDING=1" when running the fp test.
When a symbol removed by .symver is used in relocation and there is one
and only one versioned symbol, don't remove the symbol. Instead, mark
it to be removed and replace the removed symbol used in relocation with
the versioned symbol before generating relocation.
PR gas/28157
* symbols.c (symbol_flags): Add removed.
(symbol_entry_find): Updated.
(symbol_mark_removed): New function.
(symbol_removed_p): Likewise.
* symbols.h (symbol_mark_removed): New prototype.
(symbol_removed_p): Likewise.
* write.c (write_relocs): Call obj_fixup_removed_symbol on
removed fixp->fx_addsy and fixp->fx_subsy if defined.
(set_symtab): Don't add a symbol if symbol_removed_p returns true.
* config/obj-elf.c (elf_frob_symbol): Don't remove the symbol
if it is used on relocation. Instead, mark it as to be removed
and issue an error if the symbol has more than one versioned name.
(elf_fixup_removed_symbol): New function.
* config/obj-elf.h (elf_fixup_removed_symbol): New prototype.
(obj_fixup_removed_symbol): New.
* testsuite/gas/symver/symver11.d: Updated expected error
message.
* testsuite/gas/symver/symver16.d: New file.
* testsuite/gas/symver/symver16.s: Likewise.
PR 28168:
Stack overflow with a large float. %f is not a goot choice for this.
%f should be replaced with %.7g.
gas/
* testsuite/gas/csky/pr28168.d: New testcase for PR 28168.
* testsuite/gas/csky/pr28168.s: Likewise.
* testsuite/gas/csky/v2_float_part2.d: Following the new format.
* opcodes/csky-dis.c (csky_output_operand): %.7g replaces %f.
As discussed previously, a.out support is now quite deprecated, and in
some cases removed, in both Binutils itself and NetBSD, so this legacy
default makes little sense. `netbsdelf*` and `netbsdaout*` still work
allowing the user to be explicit about there choice. Additionally, the
configure script warns about the change as Nick Clifton requested.
One possible concern was the status of NetBSD on NS32K, where only a.out
was supported. But per [1] NetBSD has removed support, and if it were to
come back, it would be with ELF. The binutils implementation is
therefore marked obsolete, per the instructions in the last message.
With that patch and this one applied, I have confirmed the following:
--target=i686-unknown-netbsd
--target=i686-unknown-netbsdelf
builds completely
--target=i686-unknown-netbsdaout
properly fails because target is deprecated.
--target=vax-unknown-netbsdaout builds completely except for gas, where
the target is deprecated.
[1]: https://mail-index.netbsd.org/tech-toolchain/2021/07/19/msg004025.html
---
bfd/config.bfd | 43 +++++++++++++--------
bfd/configure.ac | 5 +--
binutils/testsuite/binutils-all/nm.exp | 2 +-
binutils/testsuite/lib/binutils-common.exp | 7 +---
config/picflag.m4 | 4 +-
gas/configure.tgt | 9 +++--
gas/testsuite/gas/arm/blx-bl-convert.d | 2 +-
gas/testsuite/gas/arm/blx-local-thumb.d | 2 +-
gas/testsuite/gas/sh/basic.exp | 2 +-
gdb/configure.host | 34 +++++++----------
gdb/configure.tgt | 2 +-
gdb/testsuite/gdb.asm/asm-source.exp | 6 +--
intl/configure | 2 +-
ld/configure.tgt | 44 +++++++++++-----------
ld/testsuite/ld-arm/arm-elf.exp | 4 +-
ld/testsuite/ld-elf/elf.exp | 2 +-
ld/testsuite/ld-elf/shared.exp | 4 +-
libiberty/configure | 4 +-
Like for infinity, there isn't just a single NaN. The sign bit may be
of interest and, going beyond infinity, whether the value is quiet or
signalling may be even more relevant to be able to encode.
Note that an anomaly with x86'es double extended precision NaN values
gets taken care of at the same time: For all other formats a positive
value with all mantissa bits set was used, while here a negative value
with all non-significant mantissa bits clear was chose for an unknown
reason.
For m68k, since I don't know their X_PRECISION floating point value
layout, a warning gets issued if any of the new flavors was attempted
to be encoded that way. However likely it may be that, given that the
code lives in a source file supposedly implementing IEEE-compliant
formats, the bit patterns of the individual words match x86'es, I didn't
want to guess so. And my very, very old paper doc doesn't even mention
floating point formats other than single and double.
Unlike the forms consuming/producing integer data, the floating point
ones so far required the 2nd argument to be present, contrary to
documentation. To avoid code duplication, split float_length() out of
hex_float() (taking the opportunity to adjust error message wording).
This is to be able to generate data acted upon by AVX512-BF16 and
AMX-BF16 insns. While not part of the IEEE standard, the format is
sufficiently standardized to warrant handling in config/atof-ieee.c.
Arm, where custom handling was implemented, may want to leverage this as
well. To be able to also use the hex forms supported for other floating
point formats, a small addition to the generic hex_float() is needed.
Extend existing x86 testcases.
This is to be able to generate data passed to {,V}CVTPH2PS and acted
upon by AVX512-FP16 insns. To be able to also use the hex forms
supported for other floating point formats, a small addition to the
generic hex_float() is needed.
Extend existing x86 testcases.
The ELF psABI-s are quite clear here: On 32-bit the data type is 12
bytes long (with 2 bytes of trailing padding), while on 64-bit it is 16
bytes long (with 6 bytes of padding). Make hex_float() capable of
handling such padding.
Note that this brings the emitted data size of .dc.x / .dcb.x in line
also for non-ELF targets; so far they were different depending on input
format (dec vs hex).
Extend the existing x86 testcases.
The ELF psABI-s are quite clear here: On 32-bit the underlying data type
is 12 bytes long (with 2 bytes of trailing padding), while on 64-bit it
is 16 bytes long (with 6 bytes of padding). Make s_space() capable of
handling 'x' (and 'p') type floating point being other than 12 bytes
wide (also adjusting documentation). This requires duplicating the
definition of X_PRECISION in the target speciifc header; the compiler
would complain if this was out of sync with config/atof-ieee.c.
Note that for now padding space doesn't get separated from actual
storage, which means that things will work correctly only for little-
endian cases, and which also means that by specifying large enough
numbers padding space can be set to non-zero. Since the logic is needed
for a single little-endian architecture only for now, I'm hoping that
this might be acceptable for the time being; otherwise the change will
become more intrusive.
Note also that this brings the emitted data size of .ds.x vs .tfloat in
line for non-ELF targets as well; the issue will be even more obvious
when further taking into account a subsequent patch fixing .dc.x/.dcb.x
(where output sizes currently differ depending on input format).
Extend existing x86 testcases.
The ELF psABI-s are quite clear here: On 32-bit the data type is 12
bytes long (with 2 bytes of trailing padding), while on 64-bit it is 16
bytes long (with 6 bytes of padding). Make ieee_md_atof() capable of
handling such padding, and specify the needed padding for x86 (leaving
non-ELF targets alone for now). Split the existing x86 testcase.
* dwarf2dbg.c (get_directory_table_entry): Ensure that dir[0]
contains current working directory.
(out_dir_and_file_list): Likewise.
* testsuite/gas/elf/dwarf-5-dir0.s: New test source file.
* testsuite/gas/elf/dwarf-5-dir0.d: New test driver.
* testsuite/gas/elf/elf.exp: Run the new test.
* testsuite/gas/elf/dwarf-5-file0.d: Adjust expected output.
* testsuite/gas/i386/dwarf5-line-1.d: Likewise.
* testsuite/gas/i386/dwarf5-line-2.d: Likewise.
Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits
in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32
in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx).
There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8
operands predated our current conventions; those instructions moved to map 3.
FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3
is very sparsely populated. Most of the FP16 instructions share opcodes and
prefix (EVEX.pp) bits with the related FP32 operations.
Intel AVX512 FP16 instructions has new displacements scaling rules, please refer
to the public software developer manual for detail information.
gas/
2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
H.J. Lu <hongjiu.lu@intel.com>
Wei Xiao <wei3.xiao@intel.com>
Lili Cui <lili.cui@intel.com>
* testsuite/gas/i386/i386.exp: Run FP16 tests.
* testsuite/gas/i386/avx512_fp16-intel.d: New test.
* testsuite/gas/i386/avx512_fp16-inval-bcast.l: Ditto.
* testsuite/gas/i386/avx512_fp16-inval-bcast.s: Ditto.
* testsuite/gas/i386/avx512_fp16.d: Ditto.
* testsuite/gas/i386/avx512_fp16.s: Ditto.
* testsuite/gas/i386/avx512_fp16_pseudo_ops.d: Ditto.
* testsuite/gas/i386/avx512_fp16_pseudo_ops.s: Ditto.
* testsuite/gas/i386/avx512_fp16_vl-intel.d: Ditto.
* testsuite/gas/i386/avx512_fp16_vl.d: Ditto.
* testsuite/gas/i386/avx512_fp16_vl.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_fp16-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_fp16-inval-bcast.l: Ditto.
* testsuite/gas/i386/x86-64-avx512_fp16-inval-bcast.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_fp16.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_fp16.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_fp16_pseudo_ops.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_fp16_pseudo_ops.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_fp16_vl-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_fp16_vl.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_fp16_vl.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_fp16-inval-register.l: Ditto.
* testsuite/gas/i386/x86-64-avx512_fp16-inval-register.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_fp16-bad.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_fp16-bad.s: Ditto.
* testsuite/gas/i386/x86-64-default-suffix-avx.d: Add new testcase.
* testsuite/gas/i386/x86-64-default-suffix.d: Ditto.
* testsuite/gas/i386/x86-64-default-suffix.s: Ditto.
* testsuite/gas/i386/xmmword.l: Ditto.
* testsuite/gas/i386/xmmword.s: Ditto.
opcodes/
* s390-opc.c (INSTR_SIY_RD): New instruction format.
(MASK_SIY_RD): New instruction mask.
* s390-opc.txt: Change instruction format of lpswey to SIY_RD.
gas/
* testsuite/gas/s390/zarch-arch14.d: Remove last operand of
lpswey.
* testsuite/gas/s390/zarch-arch14.s: Likewise.
A C_BSTAT debug symbol specifies the beginning of a static block.
Its n_value is the index of the csect containing static symbols.
A C_STSYM debug symbol represents the stabstring of a statically
allocated symbol. Its n_value is the offset in the csect pointed
by the containing C_BSTAT.
These two special n_value were not correctly handled both when
generating object files with gas or when reading them with objdump.
This patch tries to improve that and, above all, to allow gas-generated
object files with such symbols to be accepted by AIX ld.
bfd/
* coff-bfd.c (bfd_coff_get_syment): Adjust n_value of symbols
having fix_value = 1 in order to be an index and not a memory
offset.
* coffgen.c (coff_get_symbol_info): Likewize.
(coff_print_symbol): Likewize.
gas/
* config/tc-ppc.c (ppc_frob_label): Don't change within if
already set.
(ppc_stabx): Remove workaround changing exp.X_add_symbol's
within.
* config/tc-ppc.h (struct ppc_tc_sy): Update comments.
* symbols.c (resolve_symbol_value): Remove symbol update
when final_val is 0 and it's an AIX debug symbol.
* testsuite/gas/ppc/aix.exp: Add new tests.
* testsuite/gas/ppc/xcoff-stsym-32.d: New test.
* testsuite/gas/ppc/xcoff-stsym-64.d: New test.
* testsuite/gas/ppc/xcoff-stsym.s: New test.
