PR 28436
* config/tc-arm.c (do_vfp_nsyn_push_pop_check): New function.
(do_vfp_nsyn_pop): Use the new function.
(do_vfp_nsyn_push): Use the new function.
* testsuite/gas/arm/v8_1m-mve.s: Add new instructions.
* testsuite/gas/arm/v8_1m-mve.d: Updated expected disassembly.
This patch adds support for encoding the Return Address Authentication pseudo
register - '.save {ra_auth_code}' as defined by the DWARF ABI - in the
exception tables where the opcode is defined by the EHABI
gas/Changelog:
* config/tc-arm.c (arm_reg_type): Add new type REG_TYPE_PSEUDO.
(reg_expected_msgs): Add message for pseudo reg type.
(reg_list_els): Add new reg list type REGLIST_PSEUDO.
(parse_reg_list): Handle new REGLIST_PSEUDO type.
(s_arm_unwind_save_pseudo): Encode pseudo reg list save in exception
tables.
(s_arm_unwind_save): Handle new REG_TYPE_PSEUDO.
(reg_names): Add ra_auth_code pseudo register.
* testsuite/gas/arm/unwind-pacbti-m.s: New test.
* testsuite/gas/arm/unwind-pacbti-m.d: New test.
* testsuite/gas/arm/unwind-pacbti-m-readelf.d: New test.
Tidy the gas/config/tc-riscv.c and opcodes/riscv-dis.c, to prepare for
moving the released extensions (including released vendor extensions)
from integration branch back to mainline.
* Added parts of missing comments.
* Updated md_show_usage.
* For validate_riscv_insn, riscv_ip and print_insn_args, unify the
following pointer names,
- oparg: pointed to the parsed operand defined in the riscv_opcodes.
- asarg: pointed to the parsed operand from assembly.
- opargStart: recorded the parsed operand name from riscv_opcodes.
- asargStart: recorded the parsed operand name from assembly.
gas/
* config/tc-riscv.c: Added parts of missind comments and updated
the md_show_usage.
(riscv_multi_subset_supports): Tidy codes.
(validate_riscv_insn): Unify the pointer names, oparg, asarg,
opargStart and asargStart, to prepare for moving the released
extensions from integration branch back to mainline.
(riscv_ip): Likewise.
(macro_build): Added fmtStart, also used to prepare for moving
released extensions.
(md_show_usage): Added missing descriptions for new options.
opcodes/
* riscv-dis.c (print_insn_args): Unify the pointer names,
oparg and opargStart, to prepare for moving the released
extensions from integration branch back to mainline.
Unaligned load/store instructions on aligned memory or register are as
fast as aligned load/store instructions on modern Intel processors. Add
a command-line option, -muse-unaligned-vector-move, to x86 assembler to
encode encode aligned vector load/store instructions as unaligned
vector load/store instructions.
* NEWS: Mention -muse-unaligned-vector-move.
* config/tc-i386.c (use_unaligned_vector_move): New.
(encode_with_unaligned_vector_move): Likewise.
(md_assemble): Call encode_with_unaligned_vector_move for
-muse-unaligned-vector-move.
(OPTION_MUSE_UNALIGNED_VECTOR_MOVE): New.
(md_longopts): Add -muse-unaligned-vector-move.
(md_parse_option): Handle -muse-unaligned-vector-move.
(md_show_usage): Add -muse-unaligned-vector-move.
* doc/c-i386.texi: Document -muse-unaligned-vector-move.
* testsuite/gas/i386/i386.exp: Run unaligned-vector-move and
x86-64-unaligned-vector-move.
* testsuite/gas/i386/unaligned-vector-move.d: New file.
* testsuite/gas/i386/unaligned-vector-move.s: Likewise.
* testsuite/gas/i386/x86-64-unaligned-vector-move.d: Likewise.
Add aliases for the non-immediate mnemonics of b{set,clr,inv,ext} to
yencode the respective immediate insn b{set,clr,inv,ext}i when the
second source operand is an immediate.
2021-01-11 Philipp Tomsich <philipp.tomsich@vrull.eu>
gas/
* testsuite/gas/riscv/b-ext.d: Add tests.
* testsuite/gas/riscv/b-ext.s: Likewise.
* testsuite/gas/riscv/b-ext-64.d: Likewise.
* testsuite/gas/riscv/b-ext-64.s: Likewise.
opcodes/
* riscv-opc.c (riscv_opcodes): Add aliases for Zbs.
Suggested-by: Jan Beulich <jbeulich@suse.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Patch is adding Cortex-R52+ as 'cortex-r52plus' command line
flag for -mcpu option.
bfd/
* cpu-arm.c: New Cortex-R52+ CPU.
gas/
* NEWS: Update docs.
* config/tc-arm.c: New Cortex-R52+ CPU.
* doc/c-arm.texi: Update docs.
* testsuite/gas/arm/cpu-cortex-r52plus.d: New test.
Patch is adding new 'armv9-a` command line flag to -march for AArch64.
gas/
* config/tc-aarch64.c: Add 'armv9-a' command line flag.
* docs/c-aarch64.text: Update docs.
* NEWS: Update docs.
include/
* opcode/aarch64.h (AARCH64_FEATURE_V9): New define.
(AARCH64_ARCH_V9): New define.
We need to allow adding numbers in the prefixed extension names, since
the zve<32,64><d,f,x> extensions are included in the forzen rvv v1.0 spec
recently. But there are two restrictions as follows,
* The extension name ends with <number>p is invalid, since this may
be confused with extension with <number>.0 version. We report errors
for this case.
Invalid format: [z|h|s|zvm|x][0-9a-z]+[0-9]+p
* The extension name ends with numbers is valid, but the numbers will
be parsed as major version, so try to avoid naming extensions like this.
bfd/
* elfxx-riscv.c (riscv_recognized_prefixed_ext): Renamed from
riscv_valid_prefixed_ext/
(riscv_parsing_subset_version): The extensions end with <number>p
is forbidden, we already report the detailed errors in the
riscv_parse_prefixed_ext, so clean the code and unused parameters.
(riscv_parse_std_ext): Updated.
(riscv_parse_prefixed_ext): Rewrite the parser to allow numbers
in the prefixed extension names.
gas/
* testsuite/gas/riscv/march-fail-invalid-x-01.d: New testcases.
* testsuite/gas/riscv/march-fail-invalid-x-02.d: Likewise.
* testsuite/gas/riscv/march-fail-invalid-z-01.d: Likewise.
* testsuite/gas/riscv/march-fail-invalid-z-02.d: Likewise.
* testsuite/gas/riscv/march-fail-invalid.l: Likewise.
* testsuite/gas/riscv/march-fail-version-x.d: Removed.
* testsuite/gas/riscv/march-fail-version-z.d: Likewise.
* testsuite/gas/riscv/march-fail-version.l: Likewise.
Don't print broadcast for scalar_mode, and print {bad} for invalid broadcast.
gas/
PR binutils/28381
* testsuite/gas/i386/bad-bcast.s: Add a new testcase.
* testsuite/gas/i386/bad-bcast.d: Likewise.
* testsuite/gas/i386/bad-bcast-intel.d: New.
opcodes/
PR binutils/28381
* i386-dis.c (static struct): Add no_broadcast.
(OP_E_memory): Mark invalid broadcast with no_broadcast=1 and Print "{bad}"for it.
(intel_operand_size): mark invalid broadcast with no_broadcast=1.
(OP_XMM): Mark scalar_mode with no_broadcast=1.
SPR 896 and the mfppr mfppr32, mtppr and mtppr32 extended mnemonics were added
in ISA 2.03, so enable them on POWER5 and later.
opcodes/
* ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
on POWER5 and later.
gas/
* testsuite/gas/ppc/power5.s: New test.
* testsuite/gas/ppc/power5.d: Likewise.
* testsuite/gas/ppc/ppc.exp: Run it.
* testsuite/gas/ppc/power7.s: Remove tests for mfppr, mfppr32, mtppr
and mtppr32.
* testsuite/gas/ppc/power7.d: Likewise.
Required for the expected "CU:" to be emitted for long
source-paths. See binutils/dwarf.c:
if (do_wide || strlen (directory) < 76)
printf (_("CU: %s/%s:\n"), directory, file_table[0].name);
else
printf ("%s:\n", file_table[0].name);
See also commit 5f410aa50c, "testsuite/ld-elf/pr26936.d:
Pass -W."
gas/ChangeLog:
* testsuite/ld-elf/dwarf2-21.d: Pass -W.
This is a testcase for the bug fixed by commit 5b4846283c. When
running the testcase on ia64 targets I found timeouts along with lots
of memory being consumed, due to ia64 gas not tracking text
sub-sections. Trying to add nops for ".nop 16" in ".text 1" resulting
in them being added to subsegment 0, with no increase to subsegment 1
size. This patch also fixes that problem.
Note that the testcase fails on ft32-elf, mn10200-elf, score-elf,
tic5x-elf, and xtensa-elf. The first two are relocation errors, the
last three appear to be the .nop directive failing to emit the right
number of nops. I didn't XFAIL any of them.
* config/tc-ia64.c (md): Add last_text_subseg.
(ia64_flush_insns, dot_endp): Use last_text_subseg.
(ia64_frob_label, md_assemble): Set last_text_subseg.
* testsuite/gas/elf/dwarf2-21.d,
* testsuite/gas/elf/dwarf2-21.s: New test.
* testsuite/gas/elf/elf.exp: Run it.
Fixes segfaults when building aarch64-linux kernel, due to only doing
part of the work necessary when allocating file numbers late. I'd
missed looping over subsegments, which resulted in some u.filename
entries left around and later interpreted as u.view.
PR 28149
* dwarf2dbg.c (purge_generated_debug): Iterate over subsegs too.
(dwarf2_finish): Call do_allocate_filenum for all subsegs too,
in a separate loop before subsegs are chained.
Mixing compiler generated line info with gas generated line info is
generally just confusing. Also .loc directives with non-zero view
fields might reference a previous .loc. It becomes a little more
tricky to locate that previous .loc if there might be gas generated
line info present too. Mind you, we turn off gas generation of line
info on seeing compiler generated line info, so any reference back
won't hit gas generated line info. At least, if the view info is
sane. Unfortunately, gas needs to handle mangled source.
PR 28149
* dwarf2dbg.c (purge_generated_debug): New function.
(dwarf2_directive_filename): Call the above.
(out_debug_line): Don't segfault after purging.
* testsuite/gas/i386/dwarf2-line-4.d: Update expected output.
* testsuite/gas/i386/dwarf4-line-1.d: Likewise.
* testsuite/gas/i386/dwarf5-line-1.d: Likewise.
* testsuite/gas/i386/dwarf5-line-2.d: Likewise.
gcc-11 and gcc-12 pass -gdwarf-5 to gas, in order to prime gas for
DWARF 5 level debug info. Unfortunately it seems there are cases
where the compiler does not emit a .file or .loc dwarf debug directive
before any machine instructions. (Note that the .file directive
typically emitted as the first line of assembly output doesn't count as
a dwarf debug directive. The dwarf .file has a file number before the
file name string.)
This patch delays allocation of file numbers for gas generated line
debug info until the end of assembly, thus avoiding any clashes with
compiler generated file numbers. Two fixes for test case source are
necessary; A .loc can't use a file number that hasn't already been
specified with .file.
A followup patch will remove all the gas generated line info on
seeing a .file directive.
PR 28149
* dwarf2dbg.c (num_of_auto_assigned): Delete.
(current): Update initialisation.
(set_or_check_view): Replace all accesses to view with u.view.
(dwarf2_consume_line_info): Likewise.
(dwarf2_directive_loc): Likewise. Assert that we aren't generating
line info.
(dwarf2_gen_line_info_1): Don't call set_or_check_view on
gas generated line entries.
(dwarf2_gen_line_info): Set and track filenames for gas generated
line entries. Simplify generation of labels.
(get_directory_table_entry): Use filename_cmp when comparing dirs.
(do_allocate_filenum): New function.
(dwarf2_where): Set u.filename and filenum to -1 for gas generated
line entries.
(dwarf2_directive_filename): Remove num_of_auto_assigned handling.
(process_entries): Update view field access. Call
do_allocate_filenum.
* dwarf2dbg.h (struct dwarf2_line_info): Add filename field in
union aliasing view.
* testsuite/gas/i386/dwarf2-line-3.s: Add .file directive.
* testsuite/gas/i386/dwarf2-line-4.s: Likewise.
* testsuite/gas/i386/dwarf2-line-4.d: Update expected output.
* testsuite/gas/i386/dwarf4-line-1.d: Likewise.
* testsuite/gas/i386/dwarf5-line-1.d: Likewise.
* testsuite/gas/i386/dwarf5-line-2.d: Likewise.
There are two main reasons for this patch,
* In the past we had two extension tables, one is used to record all
supported extensions in bfd/elfxx-riscv.c, another is used to get the
default extension versions in gas/config/tc-riscv.c. It is hard to
maintain lots of tables in different files, but in fact we can merge
them into just one table. Therefore, we now define many riscv_supported_std*
tables, which record names and versions for all supported extensions.
We not only use these tables to initialize the riscv_ext_order, but
also use them to get the default versions of extensions, and decide if
the extensions should be enbaled by default.
* We add a new filed `default_enable' for the riscv_supported_std* tables,
to decide if the extension should be enabled by default. For now if the
`default_enable' field of the extension is set to EXT_DEFAULT, then we
should enable the extension when the -march and elf architecture attributes
are not set. In the future, I suppose the `default_enable' can be set
to lots of EXT_<VENDOR>, each vendor can decide to open which extensions,
when the target triple of vendor is chosen.
The elf/linux regression tests of riscv-gnu-toolchain are passed.
bfd/
* elfnn-riscv.c (cpu-riscv.h): Removed sine it is included in
bfd/elfxx-riscv.h.
(riscv_merge_std_ext): Updated since the field of rpe is changed.
* elfxx-riscv.c (cpu-riscv.h): Removed.
(riscv_implicit_subsets): Added implicit extensions for g.
(struct riscv_supported_ext): Used to be riscv_ext_version. Moved
from gas/config/tc-riscv.c, and added new field `default_enable' to
decide if the extension should be enabled by default.
(EXT_DEFAULT): Defined for `default_enable' field.
(riscv_supported_std_ext): It used to return the supported standard
architecture string, but now we move ext_version_table from
gas/config/tc-riscv.c to here, and rename it to riscv_supported_std_ext.
Currently we not only use the table to initialize riscv_ext_order, but
also get the default versions of extensions, and decide if the extensions
should be enbaled by default.
(riscv_supported_std_z_ext): Likewise, but is used for z* extensions.
(riscv_supported_std_s_ext): Likewise, but is used for s* extensions.
(riscv_supported_std_h_ext): Likewise, but is used for h* extensions.
(riscv_supported_std_zxm_ext): Likewise, but is used for zxm* extensions.
(riscv_all_supported_ext): Includes all supported extension tables.
(riscv_known_prefixed_ext): Updated.
(riscv_valid_prefixed_ext): Updated.
(riscv_init_ext_order): Init the riscv_ext_order table according to
riscv_supported_std_ext.
(riscv_get_default_ext_version): Moved from gas/config/tc-riscv.c.
Get the versions of extensions from riscv_supported_std* tables.
(riscv_parse_add_subset): Updated.
(riscv_parse_std_ext): Updated.
(riscv_set_default_arch): Set the default subset list according to
the default_enable field of riscv_supported_*ext tables.
(riscv_parse_subset): If the input ARCH is NULL, then we call
riscv_set_default_arch to set the default subset list.
* elfxx-riscv.h (cpu-riscv.h): Included.
(riscv_parse_subset_t): Removed get_default_version field, and added
isa_spec field to replace it.
(extern riscv_supported_std_ext): Removed.
gas/
* (bfd/cpu-riscv.h): Removed.
(struct riscv_ext_version): Renamed and moved to bfd/elfxx-riscv.c.
(ext_version_table): Likewise.
(riscv_get_default_ext_version): Likewise.
(ext_version_hash): Removed.
(init_ext_version_hash): Removed.
(riscv_set_arch): Updated since the field of rps is changed. Besides,
report error when the architecture string is empty.
(riscv_after_parse_args): Updated.
Since the 0x57 is preserved for the vadd.vv instruction in the integration
branch, remove it to make sure the testcase can work.
gas/
* testsuite/gas/riscv/insn.d: Remove 0x57 since it is preserved
for vadd.vv instruction.
* testsuite/gas/riscv/insn.s: Likewise.
DWARF5 allows .file 0 to take an optional directory name. Set the entry
0 of the directory table to the directory name in .file 0.
PR gas/28266
* dwarf2dbg.c (get_directory_table_entry): Add an argument for
the directory name in .file 0 and use it, instead of PWD.
(allocate_filenum): Pass NULL to get_directory_table_entry.
(allocate_filename_to_slot): Pass the incoming dirname to
get_directory_table_entry.
* testsuite/gas/elf/dwarf-5-file0-2.d: New file.
* testsuite/gas/elf/dwarf-5-file0-2.s: Likewise.
* testsuite/gas/elf/elf.exp: Run dwarf-5-file0-2.
The disassembler has support to pretty print values created by an lui/addi
pair, but there is no support for addiw. There is also no support for
c.addi and c.addiw. This patch extends the pretty printing support to
handle these 3 instructions in addition to addi. Existing testcases serve
as tests for the new feature.
opcodes/
* riscv-dis.c (maybe_print_address): New arg wide. Sign extend when
wide is true.
(print_insn_args): Fix calls to maybe_print_address. Add checks for
c.addi, c.addiw, and addiw, and call maybe_print_address for them.
gas/
* testsuite/gas/riscv/insn.d: Update for disassembler change.
* testsuite/gas/li32.d, testsuite/gas/li64.d: Likwise.
* testsuite/gas/lla64.d: Likewise.
PR 28292
gas * config/tc-v850.c (handle_lo16): Also accept
BFD_RELOC_V850_LO16_SPLIT_OFFSET.
* testsuite/gas/v850/split-lo16.s: Add extra line.
* testsuite/gas/v850/split-lo16.d: Update expected disassembly.
opcodes * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
of BFD_RELOC_16.
The .insn directive can let users use their own instructions, or
some new instruction, which haven't supported in the old binutils.
For example, if users want to use sifive cache instruction, they
cannot just write "cflush.d1.l1" in the assembly code, they should
use ".insn i SYSTEM, 0, x0, x10, -0x40". But the .insn directive
may not easy to use for some cases, and not so friendly to users.
Therefore, I believe most of the users will use ".word 0xfc050073",
to encode the instructions directly, rather than use .insn. But
once we have supported the mapping symbols, the .word directives
are marked as data, so disassembler won't dump them as instructions
as usual. I have discussed this with Kito many times, we all think
extend the .insn direcitve to support the hardcode encoding, is the
easiest way to resolve the problem. Therefore, there are two more
.insn formats are proposed as follows,
(original) .insn <type>, <operand1>, <operand2>, ...
.insn <insn-length>, <value>
.insn <value>
The <type> is string, and the <insn-length> and <value> are constants.
gas/
* config/tc-riscv.c (riscv_ip_hardcode): Similar to riscv_ip,
but assembles an instruction according to the hardcode values
of .insn directive.
* doc/c-riscv.texi: Document two new .insn formats.
* testsuite/gas/riscv/insn-fail.d: New testcases.
* testsuite/gas/riscv/insn-fail.l: Likewise.
* testsuite/gas/riscv/insn-fail.s: Likewise.
* testsuite/gas/riscv/insn.d: Updated.
* testsuite/gas/riscv/insn.s: Likewise.
Similar to ARM/AARCH64, we add mapping symbols in the symbol table,
to mark the start addresses of data and instructions. The $d means
data, and the $x means instruction. Then the disassembler uses these
symbols to decide whether we should dump data or instruction.
Consider the mapping-04 test case,
$ cat tmp.s
.text
.option norelax
.option norvc
.fill 2, 4, 0x1001
.byte 1
.word 0
.balign 8
add a0, a0, a0
.fill 5, 2, 0x2002
add a1, a1, a1
.data
.word 0x1 # No need to add mapping symbols.
.word 0x2
$ riscv64-unknown-elf-as tmp.s -o tmp.o
$ riscv64-unknown-elf-objdump -d tmp.o
Disassembly of section .text:
0000000000000000 <.text>:
0: 00001001 .word 0x00001001 # Marked $d, .fill directive.
4: 00001001 .word 0x00001001
8: 00000001 .word 0x00000001 # .byte + part of .word.
c: 00 .byte 0x00 # remaining .word.
d: 00 .byte 0x00 # Marked $d, odd byte of alignment.
e: 0001 nop # Marked $x, nops for alignment.
10: 00a50533 add a0,a0,a0
14: 20022002 .word 0x20022002 # Marked $d, .fill directive.
18: 20022002 .word 0x20022002
1c: 2002 .short 0x2002
1e: 00b585b3 add a1,a1,a1 # Marked $x.
22: 0001 nop # Section tail alignment.
24: 00000013 nop
* Use $d and $x to mark the distribution of data and instructions.
Alignments of code are recognized as instructions, since we usually
fill nops for them.
* If the alignment have odd bytes, then we cannot just fill the nops
into the spaces. We always fill an odd byte 0x00 at the start of
the spaces. Therefore, add a $d mapping symbol for the odd byte,
to tell disassembler that it isn't an instruction. The behavior
is same as Arm and Aarch64.
The elf/linux toolchain regressions all passed. Besides, I also
disable the mapping symbols internally, but use the new objudmp, the
regressions passed, too. Therefore, the new objudmp should dump
the objects corretly, even if they don't have any mapping symbols.
bfd/
pr 27916
* cpu-riscv.c (riscv_elf_is_mapping_symbols): Define mapping symbols.
* cpu-riscv.h: extern riscv_elf_is_mapping_symbols.
* elfnn-riscv.c (riscv_maybe_function_sym): Do not choose mapping
symbols as a function name.
(riscv_elf_is_target_special_symbol): Add mapping symbols.
binutils/
pr 27916
* testsuite/binutils-all/readelf.s: Updated.
* testsuite/binutils-all/readelf.s-64: Likewise.
* testsuite/binutils-all/readelf.s-64-unused: Likewise.
* testsuite/binutils-all/readelf.ss: Likewise.
* testsuite/binutils-all/readelf.ss-64: Likewise.
* testsuite/binutils-all/readelf.ss-64-unused: Likewise.
gas/
pr 27916
* config/tc-riscv.c (make_mapping_symbol): Create a new mapping symbol.
(riscv_mapping_state): Decide whether to create mapping symbol for
frag_now. Only add the mapping symbols to text sections.
(riscv_add_odd_padding_symbol): Add the mapping symbols for the
riscv_handle_align, which have odd bytes spaces.
(riscv_check_mapping_symbols): Remove any excess mapping symbols.
(md_assemble): Marked as MAP_INSN.
(riscv_frag_align_code): Marked as MAP_INSN.
(riscv_init_frag): Add mapping symbols for frag, it usually called
by frag_var. Marked as MAP_DATA for rs_align and rs_fill, and
marked as MAP_INSN for rs_align_code.
(s_riscv_insn): Marked as MAP_INSN.
(riscv_adjust_symtab): Call riscv_check_mapping_symbols.
* config/tc-riscv.h (md_cons_align): Defined to riscv_mapping_state
with MAP_DATA.
(TC_SEGMENT_INFO_TYPE): Record mapping state for each segment.
(TC_FRAG_TYPE): Record the first and last mapping symbols for the
fragments. The first mapping symbol must be placed at the start
of the fragment.
(TC_FRAG_INIT): Defined to riscv_init_frag.
* testsuite/gas/riscv/mapping-01.s: New testcase.
* testsuite/gas/riscv/mapping-01a.d: Likewise.
* testsuite/gas/riscv/mapping-01b.d: Likewise.
* testsuite/gas/riscv/mapping-02.s: Likewise.
* testsuite/gas/riscv/mapping-02a.d: Likewise.
* testsuite/gas/riscv/mapping-02b.d: Likewise.
* testsuite/gas/riscv/mapping-03.s: Likewise.
* testsuite/gas/riscv/mapping-03a.d: Likewise.
* testsuite/gas/riscv/mapping-03b.d: Likewise.
* testsuite/gas/riscv/mapping-04.s: Likewise.
* testsuite/gas/riscv/mapping-04a.d: Likewise.
* testsuite/gas/riscv/mapping-04b.d: Likewise.
* testsuite/gas/riscv/mapping-norelax-04a.d: Likewise.
* testsuite/gas/riscv/mapping-norelax-04b.d: Likewise.
* testsuite/gas/riscv/no-relax-align.d: Updated.
* testsuite/gas/riscv/no-relax-align-2.d: Likewise.
include/
pr 27916
* opcode/riscv.h (enum riscv_seg_mstate): Added.
opcodes/
pr 27916
* riscv-dis.c (last_map_symbol, last_stop_offset, last_map_state):
Added to dump sections with mapping symbols.
(riscv_get_map_state): Get the mapping state from the symbol.
(riscv_search_mapping_symbol): Check the sorted symbol table, and
then find the suitable mapping symbol.
(riscv_data_length): Decide which data size we should print.
(riscv_disassemble_data): Dump the data contents.
(print_insn_riscv): Handle the mapping symbols.
(riscv_symbol_is_valid): Marked mapping symbols as invalid.
Put back 3 aborts where invalid lengths should have been filtered out.
gas/
PR binutils/28247
* testsuite/gas/i386/bad-bcast.s: Add a comment.
opcodes/
PR binutils/28247
* * i386-dis.c (OP_E_memory): Put back 3 aborts.
Some targets, typically embedded without shared libraries, replace the
relocation symbol with a section symbol (see tc_fix_adjustable).
Allow the test to pass for such targets. Fixes the following.
avr-elf +FAIL: symver symver16
d10v-elf +FAIL: symver symver16
dlx-elf +FAIL: symver symver16
ip2k-elf +FAIL: symver symver16
m68k-elf +FAIL: symver symver16
mcore-elf +FAIL: symver symver16
pj-elf +FAIL: symver symver16
s12z-elf +FAIL: symver symver16
visium-elf +FAIL: symver symver16
z80-elf +FAIL: symver symver16
PR gas/28157
* testsuite/gas/symver/symver16.d: Relax reloc match.
Always run fp tests since the size of .tfloat, .ds.x, .dc.x and .dcb.x
directive outputs is always 10 bytes. There is no need for fp-elf32 nor
fp-elf64.
PR gas/28230
* testsuite/gas/i386/fp-elf32.d: Removed.
* testsuite/gas/i386/fp-elf64.d: Likewise.
* testsuite/gas/i386/fp.s: Remove NO_TFLOAT_PADDING codes.
* testsuite/gas/i386/i386.exp: Don't run fp-elf32 nor fp-elf64.
Always run fp.
