* config/tc-arm.c: Changed INSN_SIZE to variable insn_size, as
pre-cursor to adding Thumb support. Also added cpu_variant flag
information to each of the asm_flg structures.
(md_parse_option): Updated ARM7 parsing to allow 't' for
thumb/halfword support, aswell as 'm' for long multiply.
(md_show_usage): Updated help message.
(md_assemble): Check that instruction flags are applicated to the
current cpu variant.
(md_apply_fix3, tc_gen_reloc): Add BFD_RELOC_ARM_OFFSET_IMM8 and
BFD_RELOC_ARM_HWLITERAL relocation support for new halfword and
signextension instructions.
(do_ldst): Generate halfword and signextension variants if
mnemonic flags match.
(ldst_extend): Do not allow shifts in the offset field of halfword
or signextension instructions.
(validate_offset_imm): Provide check on halfword and signextension
immediate range.
(add_to_lit_pool): Merge identical literal pool values.
Wed Jul 31 15:55:12 1996 James G. Smith <jsmith@cygnus.co.uk>
* gas/arm/arm7t.s: Added.
* gas/arm/arm7t.d: Added.
* gas/arm/arm.exp: Updated to run the new test.
(cons_fix_new_hppa): Don't coke on e_esel.
(tc_gen_reloc, SOM version): Handle R_COMP2 when used
to help generate exception handling tables.
(md_apply_fix): Don't try to apply fixups with an e_esel
selector.
(hppa_fix_adjustable): Fixups with e_esel selectors
are not adjustable.
Another stab at EH on the PA.
* config/tc-d10v.c: Fix packaging bug. Added range checking.
Added kludge for divs instruction. Fixed minor problem with
multiple text sections.
* config/tc-d10v.h (d10v_cleanup): Change prototype.
Tue Jul 23 10:49:36 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* config/tc-d10v.c (md_apply_fix3): Fix all instruction
addresses to be right-shifted by 2.
end-sanitize-d10v
Mon Jul 22 11:32:36 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* config/tc-d10v.c: Many changes to get relocs working.
(register_name): No longer creates a symbol for register names.
(pre_defined_registers): moved to opcodes/d10v-opc.c.
(d10v_insert_operand): Now works correctly for either container.
* config/tc-d10v.h (d10v_cleanup): Declare.
end-sanitize-d10v
* tc-alpha.c: Patches to track current minimum alignment to reduce
the number of fragments created with frag_align.
(alpha_current_align): New static variable.
(s_alpha_text): Reset alignment to 0.
(s_alpha_data, s_alpha_rdata, s_alpha_sdata): Likewise.
(s_alpha_stringer, s_alpha_space): New functions.
(s_alpha_cons, alpha_flush_pending_output): Remove functions.
(alpha_cons_align): New function to replace both of them.
(emit_insn): Only align if alpha_current_align is less than 2;
reset alpha_current_align to 2.
(s_alpha_gprel32): Likewise.
(s_alpha_section): New function. Basically duplicate the other
alpha section change hooks. Only define for ELF.
(s_alpha_float_cons): Simplify alignment handling.
(md_pseudo_table): Only define "rdata" and "sdata" if OBJ_ECOFF.
If OBJ_ELF, define "section", "section.s", "sect", and "sect.s".
Don't define the s_alpha_cons pseudo-ops. Do define
s_alpha_stringer and s_alpha_space pseudo-ops.
(alpha_align): Skip if less than current default alignment. Set
default alignment.
* tc-alpha.h (md_flush_pending_output): Remove.
(md_cons_align): Add.
* tc-alpha.c: Add oodles of function description comments.
(md_bignum_to_chars): Remove; there are no callers.
(md_show_usage): Mention some more variants.
uaxword to use s_uacons.
(sparc_no_align_cons): New static variable.
(s_uacons): New static function.
(sparc_cons_align): If sparc_no_align_cons is set, just clear it
and return.
Wed Jul 17 14:25:13 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* config/tc-d10v.c: New file.
* config/tc-d10v.h: New file.
* configure (d10v-*-elf): New target.
* configure.in (d10v-*-elf): New target.
end-sanitize-d10v
* config/tc-alpha.c (alpha_align): Change fill parameter
to a pointer. Take NULL as 0 or nop depending on section. Change
all callers.
(s_alpha_align): Rename local variables.
* doc/as.texinfo (.align): Document action of omitted
fill parameter.
if fx_pcrel is set. Correct setting the addend case in the
OBJ_ELF case (from Andreas Schwab
<schwab@issan.informatik.uni-dortmund.de>).
(md_show_usage): Correct -mfc5200 to -m5200.
* config/tc-mips.c (mips_ip): Only perform range check when
dealing with O_constant expressions.
Problem noticed by QMS, where "%lo(SYM + LARGEOFFSET)" would complain
about the OFFSET being greater than 16bits or not absolute, when it
should really just be taking the lo-16bits of the final address value.
registers.
* config/tc-m68k.c (mcf5200_control_regs): New variable,
array of control registers for the coldfire.
(cpu_of_arch): Added mcf5200.
(archs): Added mcf5200.
(init_table): Add new control registers.
(m68k_ip): Added support for new control registers.
(m68k_init_after_args): Likewise.
* config/tc-m68k.c (md_show_usage): Add -m5200 to usage text.
(sparc_cons_align): Declare.
(HANDLE_ALIGN): Define.
(sparc_handle_align): Declare.
* config/tc-sparc.c (sparc_cons_align): New function.
(sparc_handle_align): New function.
* read.c (cons_worker): Call md_cons_align if it is defined.
* config/tc-mips.c: Added cop_interlocks, to avoid NOP insertion
between co-processor comparisons and branches for the VR4300.
The preliminary documentation was slightly unclear on this issue, but
NEC have confirmed that there is an interlock within the CPU.
