Commit Graph

6271 Commits

Author SHA1 Message Date
Palmer Dabbelt
c41cf6fdf5 RISC-V: Avoid a const warning
2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>

       * config/tc-riscv.c (riscv_clear_subsets): Cast argument to free to
       avoid const warnings.
2017-04-03 09:14:50 -07:00
Palmer Dabbelt
fecb9c4665 RISC-V: Allow ISA subsets to be disabled
Without this patch, passing "-march=rv64ic -march=rv64i" results in
you getting a "RV64IC" toolchain, which isn't expected.

gas/ChangeLog:

2017-03-30  Palmer Dabbelt  <palmer@dabbelt.com>

       * config/tc-riscv.c (riscv_clear_subsets): New function.
       (riscv_add_subset): Call riscv_clear_subsets and riscv_set_rvc to
       clear RVC when it's been previously set.
2017-03-31 09:35:21 -07:00
Nick Clifton
dc1e4d6ded Reduce the size of s390 symbol tables by allowing relocations in mergeable string sections (eg .debug_str) to be made section relative rather than symbol relative.
PR gas/21333
	* config/tc-s390.c (tc_s390_fix_adjustable): Allow non pc-relative
	fixups in mergeable sections to be adjusted.
2017-03-31 12:54:38 +01:00
Pip Cet
f96bd6c2d7 Add support for the WebAssembly file format and the wasm32 ELF conversion to gas and the binutils.
binutils * readelf.c: Add support for wasm32 ELF format WebAssembly files.
	(guess_is_rela): Likewise.
	(dump_relocations): Likewise.
	(is_32bit_abs_reloc): Likewise.
	(is_none_reloc_): Likewise.
	* NEWS: Mention the new support.
	* testsuite/lib/binutils-common.exp (is_elf_format): Mark wasm32
	as ELF target.
	(supports_gnu_unique): Mark wasm32 as supporting STB_GNU_UNIQUE.
	* testsuite/binutils-all/nm.exp: Mark wasm32 as requiring .size annotations.
	* testsuite/binutils-all/wasm32: New directory.
	* testsuite/binutils-all/wasm32/create-wasm.d: New file.
	* testsuite/binutils-all/wasm32/create-wasm.s: Likewise.
	* testsuite/binutils-all/wasm32/custom-section.d: Likewise.
	* testsuite/binutils-all/wasm32/custom-section.s: Likewise.
	* testsuite/binutils-all/wasm32/invalid-wasm-1.d: Likewise.
	* testsuite/binutils-all/wasm32/invalid-wasm-1.s: Likewise.
	* testsuite/binutils-all/wasm32/long-sections.d: Likewise.
	* testsuite/binutils-all/wasm32/long-sections.s: Likewise.
	* testsuite/binutils-all/wasm32/parse-wasm.d: Likewise.
	* testsuite/binutils-all/wasm32/parse-wasm.s: Likewise.
	* testsuite/binutils-all/wasm32/parse-wasm-2.d: Likewise.
	* testsuite/binutils-all/wasm32/parse-wasm-2.s: Likewise.
	* testsuite/binutils-all/wasm32/prepared-section.d: Likewise.
	* testsuite/binutils-all/wasm32/prepared-section.s: Likewise.
	* testsuite/binutils-all/wasm32/wasm32.exp: New file, run tests.

gas	* config/tc-wasm32.h: New file: Add WebAssembly assembler target.
	* config/tc-wasm32.c: New file: Add WebAssembly assembler target.
	* Makefile.am: Add WebAssembly assembler target.
	* configure.tgt: Add WebAssembly assembler target.
	* doc/c-wasm32.texi: New file: Start documenting WebAssembly
	assembler.
	* doc/all.texi: Define WASM32.
	* doc/as.texinfo: Add WebAssembly entries.
	* NEWS: Mention the new support.
	* Makefile.in: Regenerate.
	* po/gas.pot: Regenerate.
	* po/POTFILES.in: Regenerate.
	* testsuite/gas/wasm32: New directory.
	* testsuite/gas/wasm32/allinsn.d: New file.
	* testsuite/gas/wasm32/allinsn.s: New file.
	* testsuite/gas/wasm32/illegal.l: New file.
	* testsuite/gas/wasm32/illegal.s: New file.
	* testsuite/gas/wasm32/illegal-2.l: New file.
	* testsuite/gas/wasm32/illegal-2.s: New file.
	* testsuite/gas/wasm32/illegal-3.l: New file.
	* testsuite/gas/wasm32/illegal-3.s: New file.
	* testsuite/gas/wasm32/illegal-4.l: New file.
	* testsuite/gas/wasm32/illegal-4.s: New file.
	* testsuite/gas/wasm32/illegal-5.l: New file.
	* testsuite/gas/wasm32/illegal-5.s: New file.
	* testsuite/gas/wasm32/illegal-6.l: New file.
	* testsuite/gas/wasm32/illegal-6.s: New file.
	* testsuite/gas/wasm32/illegal-7.l: New file.
	* testsuite/gas/wasm32/illegal-7.s: New file.
	* testsuite/gas/wasm32/illegal-8.l: New file.
	* testsuite/gas/wasm32/illegal-8.s: New file.
	* testsuite/gas/wasm32/illegal-9.l: New file.
	* testsuite/gas/wasm32/illegal-9.s: New file.
	* testsuite/gas/wasm32/illegal-10.l: New file.
	* testsuite/gas/wasm32/illegal-10.s: New file.
	* testsuite/gas/wasm32/illegal-11.l: New file.
	* testsuite/gas/wasm32/illegal-11.s: New file.
	* testsuite/gas/wasm32/illegal-12.l: New file.
	* testsuite/gas/wasm32/illegal-12.s: New file.
	* testsuite/gas/wasm32/illegal-13.l: New file.
	* testsuite/gas/wasm32/illegal-13.s: New file.
	* testsuite/gas/wasm32/illegal-14.l: New file.
	* testsuite/gas/wasm32/illegal-14.s: New file.
	* testsuite/gas/wasm32/illegal-15.l: New file.
	* testsuite/gas/wasm32/illegal-15.s: New file.
	* testsuite/gas/wasm32/illegal-16.l: New file.
	* testsuite/gas/wasm32/illegal-16.s: New file.
	* testsuite/gas/wasm32/illegal-17.l: New file.
	* testsuite/gas/wasm32/illegal-17.s: New file.
	* testsuite/gas/wasm32/illegal-18.l: New file.
	* testsuite/gas/wasm32/illegal-18.s: New file.
	* testsuite/gas/wasm32/illegal-19.l: New file.
	* testsuite/gas/wasm32/illegal-19.s: New file.
	* testsuite/gas/wasm32/illegal-20.l: New file.
	* testsuite/gas/wasm32/illegal-20.s: New file.
	* testsuite/gas/wasm32/illegal-21.l: New file.
	* testsuite/gas/wasm32/illegal-21.s: New file.
	* testsuite/gas/wasm32/illegal-22.l: New file.
	* testsuite/gas/wasm32/illegal-22.s: New file.
	* testsuite/gas/wasm32/illegal-24.l: New file.
	* testsuite/gas/wasm32/illegal-24.s: New file.
	* testsuite/gas/wasm32/illegal-25.l: New file.
	* testsuite/gas/wasm32/illegal-25.s: New file.
	* testsuite/gas/wasm32/reloc.d: New file.
	* testsuite/gas/wasm32/reloc.s: New file.
	* testsuite/gas/wasm32/wasm32.exp: New tests for WebAssembly
	architecture.

opcodes * configure.ac: Add (empty) bfd_wasm32_arch target.
	* configure: Regenerate
	* po/opcodes.pot: Regenerate.

include	* opcode/wasm.h: New file to support wasm32 architecture.
	* elf/wasm32.h: Add R_WASM32_32 relocation.

bfd	* elf32-wasm32.c: Add relocation code, two relocs.
	* reloc.c: Add wasm32 relocations.
	* libbfd.h: Regenerate.
	* bfd-in2.h: Regenerate.
	* bfd/po/bfd.pot: Regenerate.
2017-03-30 10:57:21 +01:00
Alan Modra
52be03fd13 PowerPC -Mraw disassembly
This adds -Mraw for PowerPC objdump, a disassembler option to display
the underlying machine instruction rather than aliases.  For example,
"rlwinm" always rather than "rotlwi" when the instruction is
performing a simple rotate.

binutils/
	* doc/binutils.texi (objdump): Document PowerPC -M options.
gas/
	* config/tc-ppc.c (md_parse_option): Reject -mraw.
include/
	* opcode/ppc.h (PPC_OPCODE_RAW): Define.
	(PPC_OPCODE_*): Make them all unsigned long long constants.
opcodes/
	* ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
	"raw" option.
	(lookup_powerpc): Don't special case -1 dialect.  Handle
	PPC_OPCODE_RAW.
	(print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
	lookup_powerpc call, pass it on second.
2017-03-29 22:55:18 +10:30
Alan Modra
9b75393746 PR21303, objdump doesn't show e200z4 insns
PR 21303
opcodes/
	* ppc-dis.c (struct ppc_mopt): Comment.
	(ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
gas/
	* testsuite/gas/ppc/pr21303.d,
	* testsuite/gas/ppc/pr21303.s: New test
	* testsuite/gas/ppc/ppc.exp: Run it.
2017-03-27 21:49:32 +10:30
Rinat Zelig
c0c31e91ad Implement ARC NPS-400 Ultra Ip and Miscellaneous instructions.
opcodes	* arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
	* arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR, F_NPS_M, F_NPS_CORE, F_NPS_ALL.
	(insert_nps_misc_imm_offset): New function.
	(extract_nps_misc imm_offset): New function.
	(arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
	(arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.

include * opcode/arc.h (insn_class_t): Add ULTRAIP and MISC class.

gas     * testsuite/gas/arc/nps400-12.s: New file.
        * testsuite/gas/arc/nps400-12.d: New file.
2017-03-27 11:14:30 +01:00
Thomas Preud'homme
62785b0998 [GAS/ARM] Fix selected_cpu with default CPU and -mcpu
When GAS is compiled with DEFAULT_CPU set and then run with a -mcpu or
-march option, selected_cpu will be set to the default CPU. This means
the -mcpu is ignored which is surprising behavior. This commit instead
sets selected_cpu from the value passed to -mcpu/-march.

2017-03-24  Thomas preud'homme  <thomas.preudhomme@arm.com>

gas/
	* config/tc-arm.: (md_begin): Set selected_cpu from *mcpu_cpu_opt when
	CPU_DEFAULT is defined.
2017-03-24 13:23:36 +00:00
Palmer Dabbelt
19683c0408 Sanitize RISC-V GAS help text, documentation
It looks like I missed the GAS help text when going through all the
documentation last time, so it printed some of the old-format (never
upstream) arguments.  I fixed this, and when I went to check doc/ I
noticed it was missing the '-fpic'/'-fno-pic' options.
2017-03-22 15:46:52 -07:00
Max Filippov
24e5b4e682 gas: xtensa: make trampolines relaxation work with jumps in slots other than 0
add_jump_to_trampoline assumes that jump instruction is in slot 0,
when it's in other slot that results in fixup that references NULL symbol,
which results in segfault later in xtensa_make_cached_fixup.
Search for the non-NULL symbol in the tc_frag_data.slot_symbols and check
that there's exactly one such slot.

xtensa_relax_frag for RELAX_TRAMPOLINE reassigns fixup from the original
instruction with jump to generated jump in the trampoline frag, but does not
fix its fx_r_type or fx_size. That results in "undecodable fix" or
"fixup not contained within frag" error messages during relaxation.
Fix both these fields.

gas/
2017-03-22  Max Filippov  <jcmvbkbc@gmail.com>

	* config/tc-xtensa.c (xtensa_relax_frag): Change fx_size of the
	reassigned fixup to size of jump instruction (3) and fx_r_type
	to BFD_RELOC_XTENSA_SLOT0_OP, as there's only one slot.
	(add_jump_to_trampoline): Search
	origfrag->tc_frag_data.slot_symbols for the slot with non-NULL
	symbol and use that slot instead of slot 0.
2017-03-22 10:35:18 -07:00
Andreas Krebbel
2253c8f089 S/390: Remove vx2 facility flag
This patch removes the vx2 facility flag.  It will not be used by GCC
and was a misnomer anyway.

Committed to mainline and 2.28 branch.

include/ChangeLog:

2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* opcode/s390.h (S390_INSTR_FLAG_VX2): Remove.
	(S390_INSTR_FLAG_FACILITY_MASK): Adjust value.

gas/ChangeLog:

2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* config/tc-s390.c (s390_parse_cpu): Remove S390_INSTR_FLAG_VX2
	from cpu_table.  Remove vx2, and novx2 from cpu_flags.

opcodes/ChangeLog:

2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-mkopc.c (main): Remove vx2 check.
	* s390-opc.txt: Remove vx2 instruction flags.
2017-03-21 14:21:02 +01:00
Rinat Zelig
645d3342ba arc/nps400: Add cp16/cp32 instructions to opcodes library
Instructions for loading or storing 16/32B data from one address type to
another.

gas/ChangeLog

	* testsuite/gas/arc/nps400-11.s: New file.
	* testsuite/gas/arc/nps400-11.d: New file.

include/ChangeLog

	* opcode/arc.h (insn_class_t): Add DMA class.

opcodes/ChangeLog

	* arc-nps400-tbl.h: Add cp32/cp16 instructions format.
	* arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
	(insert_nps_imm_offset): New function.
	(extract_nps_imm_offset): New function.
	(insert_nps_imm_entry): New function.
	(extract_nps_imm_entry): New function.
2017-03-21 11:51:49 +00:00
Nick Clifton
e406e428df Update descriptions of the .2byte, .4byte and .8byte directives.
* doc/as.texinfo (2byte): Note that if no expressions are present
	the directive does nothing.  Emphasize that the output is
	unaligned, and that this can have an effect on the relocations
	generated.
	(4byte): Simplify description.  Refer back to the 2byte
	description.
	(8byte): Likewise.
2017-03-20 16:57:07 +00:00
Richard Earnshaw
d5e0ba9cdb [arm] Document missing -mfpu entries.
Nick pointed out that I hadn't documented the new -mfpu option
neon-vfpv3 and mentioned that some others were missing.

Having looked through the list only one (neon-fp16) really should be
documented; the other two entries in the real table should not be
documented as they are aliases kept for legacy compatibility reasons.
This patch adds the missing entries and notes in the main table that
the other two entries should not be documented.

I've also fixed a small spelling error in the accompanying text.

	* config/tc-arm.c (arm_fpus): Note entires that should not be
	documented.
	* doc/c-arm.texi (-mfpu): Add missing FPU entries for neon-vfpv3 and
	neon-fp16.  Fix spelling error.
2017-03-20 14:56:22 +00:00
Richard Earnshaw
d3375ddde4 [arm] Add neon-vfp3 as an alias for neon to -mfpu.
GCC recently added neon-vfpv3 as an alias for neon in -mfpu.  This patch adds a similar alias in GAS.

* config/tc-arm.c (arm_fpus): Add neon-vfpv3 as an alias for neon.
2017-03-20 10:03:15 +00:00
Rinat Zelig
2c52e2e8c9 gas/arc: Limit special handling of t/nt flag to ARCv2
In a later commit I'll be adding a new version of the ".nt" flag for an
ARC700 extension (NPS400) which does not require this same special
handling.

In this commit I have restricted the special flag handling to only apply
if we are assembling for ARCv2.  This is a restructuring commit, and
there should be no user visible changes after this commit.

gas/ChangeLog:

	* config/tc-arc.c (assemble_insn): Only handle ".t" and ".nt"
	specially for ARCv2.
2017-03-16 10:07:22 +00:00
Kito Cheng
b416fe873e RISC-V: Fix assembler for c.li, c.andi and c.addiw
- They can accept 0 in imm field

 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>

       * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
       <c.andi>: Likewise.
       <c.addiw> Likewise.
2017-03-15 07:47:52 -07:00
Nick Clifton
7cb7b948ce Fix building riscv targets with gcc v6.3.1
* config/tc-riscv.c (riscv_pre_output_hook): Fix compile time
	warning about discarding a const qualifier.
2017-03-15 09:19:42 +00:00
Kuan-Lin Chen
d47c3ff7d5 RISC-V: Define DWARF2_USE_FIXED_ADVANCE_PC.
gas/ChangeLog

2017-03-02  Kuan-Lin Chen  <rufus@andestech.com>

        * config/tc-riscv.h (HWARD2_USE_FIXED_ADVANCE_PC): New define.
2017-03-14 09:51:29 -07:00
Kuan-Lin Chen
2aece2ba02 RISC-V: Fix DW_CFA_advance_loc relocation.
gas/ChangeLog:

2017-03-02  Kuan-Lin Chen  <rufus@andestech.com>

        * config/tc-riscv.c (md_apply_fix): Set fx_frag and
        fx_next->fx_frag for CFA_advance_loc relocations.
2017-03-14 09:51:29 -07:00
Kuan-Lin Chen
c1b465c94e RISC-V: Fix the offset of CFA relocation.
gas/ChangeLog:

2017-03-02  Kuan-Lin Chen  <rufus@andestech.com>

        * config/tc-riscv.c (md_apply_fix): Compute the correct offsets
        for CFA relocations.
2017-03-14 09:51:29 -07:00
Nick Clifton
f955cccff3 Rename R_AARCH64_TLSDESC_LD64_LO12_NC to R_AARCH64_TLSDESC_LD64_LO12 and R_AARCH64_TLSDESC_ADD_LO12_NC to R_AARCH64_TLSDESC_ADD_LO12.
PR binutils/21202
include	* elf/aarch64.h (R_AARCH64_TLSDESC_LD64_LO12_NC): Rename to
	R_AARCH64_TLSDESC_LD64_LO12.
	(R_AARCH64_TLSDESC_ADD_LO12_NC): Rename to
	R_AARCH64_TLSDESC_ADD_LO12_NC.

bfd	* reloc.c (BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC): Rename to
	BFD_RELOC_AARCH64_TLSDESC_LD64_LO12.
	(BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC): Rename to
	BFD_RELOC_AARCH64_TLSDESC_ADD_LO12.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.
	* elfnn-aarch64.c (IS_AARCH64_TLS_RELAX_RELOC): Update reloc
	names.
	(IS_AARCH64_TLSDESC_RELOC): Likewise.
	(elfNN_aarch64_howto_table): Likewise.
	(aarch64_tls_transition_without_check): Likewise.
	(aarch64_reloc_got_type): Likewise.
	(elfNN_aarch64_final_link_relocate): Likewise.
	(elfNN_aarch64_tls_relax): Likewise.
	(elfNN_aarch64_relocate_section): Likewise.
	(elfNN_aarch64_gc_sweep_hook): Likewise.
	(elfNN_aarch64_check_relocs): Likewise.
	* elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Likewise.
	(_bfd_aarch64_elf_resolve_relocation): Likewise.

gas	* config/tc-aarch64.c (reloc_table): Rename
	BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC to
	BFD_RELOC_AARCH64_TLSDESC_LD64_LO12.  Rname
	BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC to
	BFD_RELOC_AARCH64_TLSDESC_ADD_LO12.
	(md_apply_fix): Likewise.
	(aarch64_force_relocation): Likewise.
	* testsuite/gas/aarch64/tls.d: Update regexp.

ld	* testsuite/ld-aarch64/ifunc-5r-local.d: Update regexp.
2017-03-13 09:58:04 +00:00
Nick Clifton
8b1e5da10a Document that the .2byte and .4byte directives warn about overlarge values.
* doc/as.texinfo (2byte): Tidy up wording.  Add note that
	overlarge values will produce a warning message and be trunacted.
	(4byte): Likewise.
2017-03-10 15:42:04 +00:00
H.J. Lu
86fa6981e7 X86: Add pseudo prefixes to control encoding
Many x86 instructions have more than one encodings.  Assembler picks
the default one, usually the shortest one.  Although the ".s", ".d8"
and ".d32" suffixes can be used to swap register operands or specify
displacement size, they aren't very flexible.  This patch adds pseudo
prefixes, {xxx}, to control instruction encoding.  The available
pseudo prefixes are {disp8}, {disp32}, {load}, {store}, {vex2}, {vex3}
and {evex}.  Pseudo prefixes are preferred over the ".s", ".d8" and
".d32" suffixes, which are deprecated.

gas/

	* config/tc-i386.c (_i386_insn): Add dir_encoding and
	vec_encoding.  Remove swap_operand and need_vrex.
	(extra_symbol_chars): Add '}'.
	(md_begin): Mark '}' with LEX_BEGIN_NAME.  Allow '}' in
	mnemonic.
	(build_vex_prefix): Don't use 2-byte VEX encoding with
	{vex3}.  Check dir_encoding and load.
	(parse_insn): Check pseudo prefixes.  Set dir_encoding.
	(VEX_check_operands): Likewise.
	(match_template): Check dir_encoding and load.
	(parse_real_register): Set vec_encoding instead of need_vrex.
	(parse_register): Likewise.
	* doc/c-i386.texi: Document {disp8}, {disp32}, {load}, {store},
	{vex2}, {vex3} and {evex}.  Remove ".s", ".d8" and ".d32"
	* testsuite/gas/i386/i386.exp: Run pseudos and x86-64-pseudos.
	* testsuite/gas/i386/pseudos.d: New file.
	* testsuite/gas/i386/pseudos.s: Likewise.
	* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
	* testsuite/gas/i386/x86-64-pseudos.s: Likewise.

opcodes/

	* i386-gen.c (opcode_modifiers): Replace S with Load.
	* i386-opc.h (S): Removed.
	(Load): New.
	(i386_opcode_modifier): Replace s with load.
	* i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
	and {evex}.  Replace S with Load.
	* i386-tbl.h: Regenerated.
2017-03-09 09:59:00 -08:00
Peter Bergner
4b8b687e88 Update -maltivec and -mvsx options to only enable their oldest instructions.
Currently, the -maltivec and -mvsx GAS options enable *all* of the altivec
and vsx instructions respecitively that have ever been added.  This is in
constract to GCC's -maltivec and -mvsx options, which only enable the oldest
(ie, first) set of altivec and vsx instructions.  This patch changes GAS to
mimic GCC's behaviour with respect to -maltivec and -mvsx and it solves a
problem with trying to assemble the lxvx instruction which is different
between POWER8 and POWER9.

opcodes/
	* ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
	<vsx>: Do not use PPC_OPCODE_VSX3;

gas/
	* testsuite/gas/ppc/altivec2.d (as): Use the -mpower8 option.
	(objdump): Use the -Mpower8 option.
2017-03-08 20:49:03 -06:00
Peter Bergner
1437d0631b Add support for the new 'lnia' extended mnemonic.
opcodes/
	* ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.

gas/
	* testsuite/gas/ppc/power9.d <lnia> New test.
	* testsuite/gas/ppc/power9.s: Likewise.
2017-03-08 14:02:18 -06:00
Alan Modra
ea86f53442 Correct @section placement for makeinfo 4.13
* doc/as.texinfo (2byte, 4byte, 8byte): Correct @section placement.
2017-03-07 19:41:56 +10:30
Alan Modra
2b841ec206 Document .Nbyte assembler directives
* doc/as.texinfo (2byte, 4byte, 8byte): Document.
	* doc/c-arm.texi (2byte, 4byte, 8byte): Omit if ELF.
2017-03-07 17:00:57 +10:30
H.J. Lu
603555e563 Add support for Intel CET instructions
Support Intel Control-flow Enforcement Technology (CET) instructions:

https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf

gas/

	* config/tc-i386.c (cpu_arch): Add .cet.
	* doc/c-i386.texi: Document cet.
	* testsuite/gas/i386/cet-intel.d: New file.
	* testsuite/gas/i386/cet.d: Likewise.
	* testsuite/gas/i386/cet.s: Likewise.
	* testsuite/gas/i386/x86-64-cet-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-cet.d: Likewise.
	* testsuite/gas/i386/x86-64-cet.s: Likewise.
	* testsuite/gas/i386/i386.exp: Run Intel CET tests.

opcodes/

	* i386-dis.c (REG_0F1E_MOD_3): New enum.
	(MOD_0F1E_PREFIX_1): Likewise.
	(MOD_0F38F5_PREFIX_2): Likewise.
	(MOD_0F38F6_PREFIX_0): Likewise.
	(RM_0F1E_MOD_3_REG_7): Likewise.
	(PREFIX_MOD_0_0F01_REG_5): Likewise.
	(PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
	(PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
	(PREFIX_0F1E): Likewise.
	(PREFIX_MOD_0_0FAE_REG_5): Likewise.
	(PREFIX_0F38F5): Likewise.
	(dis386_twobyte): Use PREFIX_0F1E.
	(reg_table): Add REG_0F1E_MOD_3.
	(prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
	PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
	PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
	PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
	(three_byte_table): Use PREFIX_0F38F5.
	(mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
	Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
	(rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
	RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
	PREFIX_MOD_3_0F01_REG_5_RM_2.
	* i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
	(cpu_flags): Add CpuCET.
	* i386-opc.h (CpuCET): New enum.
	(CpuUnused): Commented out.
	(i386_cpu_flags): Add cpucet.
	* i386-opc.tbl: Add Intel CET instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
2017-03-06 15:26:37 -08:00
H.J. Lu
1cccfb31f5 Update x86-64-mpx-inval-2 test for COFF
Assembler displays upper case hex numbers and we need to force a good
alignment to avoid matching NOPs at the end.

	* testsuite/gas/i386/x86-64-mpx-inval-2.s: Force a good alignment.
	* testsuite/gas/i386/x86-64-mpx-inval-2.l: Expect [0-9A-F]+.
2017-03-06 15:00:52 -08:00
Alan Modra
ea0de82ec2 dw2gencfi.c DWARF2_FDE_RELOC_SIZE
Add asserts that reloc size matches encoding size, and tidy.

	* dw2gencfi.c (encoding_size): Return unsigned int.
	(emit_expr_encoded): Assert size matches reloc bitsize.
	(output_fde): Use unsigned for offset_size and addr_size.  Set
	addr_size earlier and use in place of constant 4 and uses of
	DWARF2_FDE_RELOC_SIZE.  Assert it matches reloc bitsize.
2017-03-06 20:43:45 +10:30
Alan Modra
9e1a8675d4 gas/dw2gencfi.c formatting
* dw2gencfi.c: Wrap overlong lines.  Add parens for emacs
	auto reformat.  Formatting and whitespace fixes.
2017-03-06 20:36:59 +10:30
Mark Wielaard
49fced1206 gas: Emit name, comp_dir and producer strings in .debug_str.
Putting the name, comp_dir and producer strings in the .debug_str section
makes it possible to share them across CUs. This saves a small amount of
space (about ~20K on a glibc libc.so.6 build with debuginfo). And makes
it easier for tools like rpm debugedit to adjust the source paths when
generating separate debuginfo files.

gas/
       * dwarf2dbg.c (out_debug_abbrev): Use DW_FORM_strp instead of
       DW_FORM_string for DW_AT_name, DW_AT_comp_dir and DW_AT_producer.
       (out_debug_info): Accept symbols to name, comp_dir and producer
       in the .debug_str section and emit those offsets not full strings.
       (out_debug_str): New function that outputs the strings for name,
       comp_dir and producer in .debug_str and generates symbols to
       those strings.
       (out_debug_line): Create a .debug_str section if necessary and
       call out_debug_str before calling out_debug_info.
       * testsuite/gas/aarch64/dwarf.d: Add extra section symbol to
       expected output.
2017-03-05 23:37:54 +01:00
Maciej W. Rozycki
9875b36538 GAS: Fix bogus "attempt to move .org backwards" relaxation errors
Fix a commit 6afe8e98a6 ("internal error for backwards .org"),
<https://www.sourceware.org/ml/binutils/2008-06/msg00212.html>,
GAS regression that caused legitimate code to fail assembly with an
"attempt to move .org backwards" error.

For example with the `mips-linux' target we get:

$ cat org.s
	.set	mips16
	la	$2, foo
	.org	0x1000
	.align	2
foo:
	.half	0
$ as -o org.o org.s
org.s: Assembler messages:
org.s:3: Error: attempt to move .org backwards
$

where the location pointer is obviously not moved backwards with `.org'.

The cause is positive `stretch' in relaxation due to a PC-relative ADDIU
instruction (produced from the LA macro used) getting expanded from 2 to
4 bytes as `foo' is noticed to be out of range for the short encoding.
This in turn triggers logic in `relax_segment' which concludes in the
processing of an `rs_org' frag produced that the location pointer is
moved backwards while in fact only the amount to space forward to the
location requested has shrunk, resulting in a negative growth of the
frag.

Correct the bad logic then and instead verify that the fixed part of an
`rs_org' frag has not overrun the location requested, as per the comment
already included with the error message:

/* Growth may be negative, but variable part of frag
   cannot have fewer than 0 chars.  That is, we can't
   .org backwards.  */

which accurately describes the regression scenario.  Move the comment
ahead the conditional noted, for clarity.

Add generic and MIPS test cases for the `.org' pseudo-op, including the
test case discussed though not integrated with the offending commit in
particular, adjusted to work across all targets.

	gas/
	* write.c (relax_segment) <rs_org>: Only bail out if the fixed
	part of the frag has overrun the location requested.

	* testsuite/gas/all/org-1.d: New test.
	* testsuite/gas/all/org-2.d: New test.
	* testsuite/gas/all/org-3.d: New test.
	* testsuite/gas/all/org-4.d: New test.
	* testsuite/gas/all/org-5.d: New test.
	* testsuite/gas/all/org-6.d: New test.
	* testsuite/gas/all/org-1.l: New stderr output.
	* testsuite/gas/all/org-2.l: New stderr output.
	* testsuite/gas/all/org-3.l: New stderr output.
	* testsuite/gas/all/org-1.s: New test source.
	* testsuite/gas/all/org-2.s: New test source.
	* testsuite/gas/all/org-3.s: New test source.
	* testsuite/gas/all/org-4.s: New test source.
	* testsuite/gas/all/org-5.s: New test source.
	* testsuite/gas/all/org-6.s: New test source.
	* testsuite/gas/all/gas.exp: Run the new tests.

	* testsuite/gas/mips/org-1.d: New test.
	* testsuite/gas/mips/org-2.d: New test.
	* testsuite/gas/mips/org-3.d: New test.
	* testsuite/gas/mips/org-4.d: New test.
	* testsuite/gas/mips/org-5.d: New test.
	* testsuite/gas/mips/org-6.d: New test.
	* testsuite/gas/mips/org-7.d: New test.
	* testsuite/gas/mips/org-8.d: New test.
	* testsuite/gas/mips/org-9.d: New test.
	* testsuite/gas/mips/org-10.d: New test.
	* testsuite/gas/mips/org-11.d: New test.
	* testsuite/gas/mips/org-12.d: New test.
	* testsuite/gas/mips/org-1.l: New stderr output.
	* testsuite/gas/mips/org-4.l: New stderr output.
	* testsuite/gas/mips/org-5.l: New stderr output.
	* testsuite/gas/mips/org-6.l: New stderr output.
	* testsuite/gas/mips/org-10.l: New stderr output.
	* testsuite/gas/mips/org-1.s: New test source.
	* testsuite/gas/mips/org-2.s: New test source.
	* testsuite/gas/mips/org-3.s: New test source.
	* testsuite/gas/mips/org-4.s: New test source.
	* testsuite/gas/mips/org-5.s: New test source.
	* testsuite/gas/mips/org-6.s: New test source.
	* testsuite/gas/mips/org-7.s: New test source.
	* testsuite/gas/mips/org-8.s: New test source.
	* testsuite/gas/mips/org-9.s: New test source.
	* testsuite/gas/mips/org-10.s: New test source.
	* testsuite/gas/mips/org-11.s: New test source.
	* testsuite/gas/mips/org-12.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.
2017-03-02 01:44:07 +00:00
Szabolcs Nagy
01cca2f95e [AArch64] Document +rcpc weak release consistency extension
gas/
	* doc/c-aarch64.texi (AArch64 Extensions): Document rcpc.
2017-03-01 14:51:13 +00:00
Jan Beulich
15c7c1d8a5 x86: fix handling of 64-bit operand size VPCMPESTR{I,M}
Just like REX.W affects operand size of the implicit rAX/rDX inputs to
PCMPESTR{I,M}, VEX.W does for VPCMPESTR{I,M}. Allow Q or L suffixes on
the instructions.

Similarly the disassembler needs to be adjusted to no longer require
VEX.W to be zero for the instructions to be valid, and to emit proper
suffixes.

Note, however, that this doesn't address the problem of there being no
way to control (at least) {,E}VEX.W for 32- or 16-bit code. Nor does it
address the problem of the many WIG instructions not getting properly
disassembled when VEX.W=1.
2017-02-28 10:53:35 +01:00
Alan Modra
4ef97a1b45 Nios2 dynobj handling fixes
A number of places in elf32-nios.c created dynamic sections but didn't
set the hash table dynobj.  That meant we could have duplicate dynamic
sections connected to a number of bfds, so size_dynamic_sections
didn't properly discard or allocate contents.

Also, the entire set of dynamic sections was created in check_relocs
on seeing GOT relocs, when only .got related sections are needed,
probably done to hide segfaults later in finish_dynamic_sections.

The patch fixes these issues and makes the assembler emit errors when
nios2 lacks the necessary pc-relative relocs for subtraction
expressions, rather than silently generating bad code.
eg. ld-elf/merge.  I've also tidied uses of elf32_nios2_hash_table and
elf_hash_table.

bfd/
	PR 20995
	* elf32-nios2.c (nios2_elf32_relocate_section): Use htab
	rather than elf32_nios2_hash_table or elf_hash_table.
	(create_got_section): Likewise.
	(nios2_elf32_finish_dynamic_symbol): Likewise.
	(nios2_elf32_adjust_dynamic_symbol): Likewise.
	(nios2_elf32_size_dynamic_sections): Likewise.
	(nios2_elf32_check_relocs): Delete dynobj, sgot, and srelgot
	vars.  Use htab equivalents directly instead.  Don't create
	all dynamic sections on needing just the GOT.  Use a goto
	rather than a fall-through with reloc test.  Ensure
	htab->dynobj is set when making dynamic sreloc section.
	(nios2_elf32_finish_dynamic_sections): Delete dynobj, use htab
	equivalent directly instead.  Don't segfault on looking for
	.dynamic when dynamic sections have not been created.  Don't
	segfault on .got.plt being discarded.
	(nios2_elf32_size_dynamic_sections): Delete plt and got vars.
	Don't set "relocs" on .rela.plt.  Do handle .sbss.  Delete
	fixme and another not so relevant comment.
	(nios2_elf_add_symbol_hook): Delete dynobj var.  If not
	already set, set hash table dynobj on creating .sbss.
gas/
	* config/tc-nios2.h (TC_FORCE_RELOCATION_SUB_LOCAL): Define.
ld/
	* testsuite/ld-elf/merge.d: xfail for nios.
2017-02-28 13:20:21 +10:30
Alan Modra
7ba71655a4 PowerPC addpcis fix
This came up because I was looking at ld/tmpdir/addpcis.o and noticed
the odd addends on REL16DX_HA.  They ought to both be -4.  The error
crept in due REL16DX_HA howto being pc-relative (as indeed it should
be), and code at gas/write.c:1001 after this comment
	      /* Make it pc-relative.  If the back-end code has not
		 selected a pc-relative reloc, cancel the adjustment
		 we do later on all pc-relative relocs.  */
*not* cancelling the pc-relative adjustment.  So I've made a dummy
non-relative split reloc so that the generic code handles this, rather
than attempting to add hacks later in md_apply_fix which would not be
very robust.  Having the new internal reloc also makes it easy to
support

 addpcis rx,sym@ha

as an equivalent to

 addpcis rx,(sym-0f)@ha
0:

The patch also fixes overflow checking, which must test whether the
addi will overflow too since @l relocs don't have any overflow check.

Lastly, since I was poking at md_apply_fix, I arranged to have the
generic gas/write.c code emit errors for subtraction expressions where
we lack reloc support.

include/
	* elf/ppc64.h (R_PPC64_16DX_HA): New.  Expand fake reloc comment.
	* elf/ppc.h (R_PPC_16DX_HA): Likewise.
bfd/
	* reloc.c (BFD_RELOC_PPC_16DX_HA): New.
	* elf64-ppc.c (ppc64_elf_howto_raw <R_PPC64_16DX_HA>): New howto.
	(ppc64_elf_reloc_type_lookup): Translate new bfd reloc.
	(ppc64_elf_ha_reloc): Correct overflow test on REL16DX_HA.
	(ppc64_elf_relocate_section): Likewise.
	* elf32-ppc.c (ppc_elf_howto_raw <R_PPC_16DX_HA>): New howto.
	(ppc_elf_reloc_type_lookup): Translate new bfd reloc.
	(ppc_elf_check_relocs): Handle R_PPC_16DX_HA to pacify gcc.
	* libbfd.h: Regenerate.
	* bfd-in2.h: Regenerate.
gas/
	* config/tc-ppc.c (md_assemble): Use BFD_RELOC_PPC_16DX_HA for addpcis.
	(md_apply_fix): Remove fx_subsy check.  Move code converting to
	pcrel reloc earlier and handle BFD_RELOC_PPC_16DX_HA.  Remove code
	emiiting errors on seeing fx_pcrel set on unexpected relocs, as
	that is done now by the generic code via..
	* config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): ..this. Define.
	(TC_VALIDATE_FIX_SUB): Define.
ld/
	* testsuite/ld-powerpc/addpcis.d: Define ext1 and ext2 at
	limits of addpcis range.
2017-02-28 11:59:47 +10:30
Maciej W. Rozycki
0e39210161 MIPS/BFD: Also handle `jalr $0, $25' with R_MIPS_JALR
Interpret the `jalr $0, $25' instruction encoding with an R_MIPS_JALR
relocation attached as an alias to `jr $25' and convert the jump to an
equivalent branch where possible, consequently covering the MIPSr6
architecture for the purpose of this optimization too.

	bfd/
	* elfxx-mips.c (mips_elf_perform_relocation): Also handle the
	`jalr $0, $25' instruction encoding.

	gas/
	* testsuite/gas/mips/jalr4.s: Add `jalr $0, $25' instructions.
	* testsuite/gas/mips/jalr4.d: Adjust accordingly.  Remove MIPSr6
	encoding patterns.
	* testsuite/gas/mips/jalr4-n64.d: Likewise.
	* testsuite/gas/mips/mipsr6@jalr4.d: New test.
	* testsuite/gas/mips/mipsr6@jalr4-n32.d: New test.
	* testsuite/gas/mips/mipsr6@jalr4-n64.d: New test.

	ld/
	* testsuite/ld-mips-elf/jalr4.dd: Adjust for `jalr $0, $25'
	instructions.
	* testsuite/ld-mips-elf/jalr4-r6.dd: New test.
	* testsuite/ld-mips-elf/mips-elf.exp: Run the new test.
2017-02-28 00:22:36 +00:00
Alan Modra
dd803a2430 Testsuite fixes for hppa64-hpux
HPUX has a different .comm syntax, and anything in the first column
is a label.

gas/
	* testsuite/gas/elf/strtab.s: Don't put directives on first
	column or continuation with labels not in first column.
ld/
	* testsuite/ld-elf/elf.exp: Xfail pr20995 tests on hppa64-hpux.
	Set up HPUX defsym.  Run pr14170 tests and build symbol3 objects,
	defining HPUX where necessary.  Define HPUX for implib tests.
	* testsuite/ld-elf/comm-data4.d: Run for hpux.
	* testsuite/ld-elf/endsym.d: Likewise.
	* testsuite/ld-elf/linkoncerdiff.d: Likewise.
	* testsuite/ld-elf/comm-data4.s: Add alternate .comm when HPUX.
	* testsuite/ld-elf/comm-data5.s: Likewise.
	* testsuite/ld-elf/endsym.s: Likewise.
	* testsuite/ld-elf/pr14170c.s: Likewise.
	* testsuite/ld-elf/symbol3.s: Likewise.
	* testsuite/ld-elf/implib.s: Likewise.  Don't start directives
	in first column.
	* testsuite/ld-elf/linkoncerdiff2.s: Don't use numeric labels.
	* testsuite/ld-elf/warn3.d: Run for hpux.
	* testsuite/ld-scripts/rgn-at10.d: Xfail for hpux.
	* testsuite/ld-scripts/rgn-at11.d: Likewise.
	* testsuite/ld-scripts/size-2.d: Remove xfail for hpux.
2017-02-25 19:13:34 +10:30
Richard Sandiford
582e12bf76 [AArch64] Additional SVE instructions
This patch supports some additions to the SVE architecture prior to
its public release.

include/
	* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16)
	(AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2)
	(AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX)
	(AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds.

opcodes/
	* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
	(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
	(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
	(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
	(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
	(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
	(OP_SVE_V_HSD): New macros.
	(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
	(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
	(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
	(aarch64_opcode_table): Add new SVE instructions.
	(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
	for rotation operands.  Add new SVE operands.
	* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
	(ins_sve_quad_index): Likewise.
	(ins_imm_rotate): Split into...
	(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
	* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
	(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
	functions.
	(aarch64_ins_sve_addr_ri_s4): New function.
	(aarch64_ins_sve_quad_index): Likewise.
	(do_misc_encoding): Handle "MOV Zn.Q, Qm".
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
	(ext_sve_quad_index): Likewise.
	(ext_imm_rotate): Split into...
	(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
	* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
	(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
	functions.
	(aarch64_ext_sve_addr_ri_s4): New function.
	(aarch64_ext_sve_quad_index): Likewise.
	(aarch64_ext_sve_index): Allow quad indices.
	(do_misc_decoding): Likewise.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
	aarch64_field_kinds.
	(OPD_F_OD_MASK): Widen by one bit.
	(OPD_F_NO_ZR): Bump accordingly.
	(get_operand_field_width): New function.
	* aarch64-opc.c (fields): Add new SVE fields.
	(operand_general_constraint_met_p): Handle new SVE operands.
	(aarch64_print_operand): Likewise.
	* aarch64-opc-2.c: Regenerate.

gas/
	* doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum.
	* config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q
	to be used with SVE registers.
	(parse_operands): Handle new SVE operands.
	(aarch64_features): Make "sve" require F16 rather than FP.  Also
	require COMPNUM.
	* testsuite/gas/aarch64/sve.s: Add tests for new instructions.
	Include compnum tests.
	* testsuite/gas/aarch64/sve.d: Update accordingly.
	* testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions.
	* testsuite/gas/aarch64/sve-invalid.l: Update accordingly.  Also
	update expected output for new FMOV and MOV alternatives.
2017-02-24 18:29:00 +00:00
Richard Sandiford
f482d30447 [AArch64] Add a "compnum" feature
This patch adds a named "compnum" feature for the ARMv8.3-A FCADD
and FCMLA extensions.

include/
	* opcode/aarch64.h (AARCH64_FEATURE_COMPNUM): New macro.
	(AARCH64_ARCH_V8_3): Include AARCH64_FEATURE_COMPNUM.

opcodes/
	* aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
	(aarch64_feature_compnum): ...this.
	(SIMD_V8_3): Replace with...
	(COMPNUM): ...this.
	(CNUM_INSN): New macro.
	(aarch64_opcode_table): Use it for the complex number instructions.

gas/
	* doc/c-aarch64.texi: Add a "compnum" entry.
	* config/tc-aarch64.c (aarch64_features): Likewise,
	* testsuite/gas/aarch64/advsimd-compnum.s: New test.
	* testsuite/gas/aarch64/advsimd-compnum.d: Likewise.
2017-02-24 18:27:26 +00:00
Jan Beulich
7db2c58848 x86: also correctly support TEST opcode aliases
Opcodes F6/1 and F7/1 are aliases of F6/0 and F7/0 in all modes. This
complements commit 8b89fe14b5 ("X86: Decode opcode 0x82 as opcode 0x80
in 32-bit mode"), just that here 64-bit mode is also covered.
2017-02-24 10:04:26 +01:00
Sheldon Lobo
1b3cee563c gas: test cases for the architecture level aware SPARC ASI work.
gas/ChangeLog:

	Test cases for the architecture level aware SPARC ASI work.
	* gas/testsuite/gas/sparc/sparc.exp: 2 new tests
	* gas/testsuite/gas/sparc/asi-bump-warn.s: New test
	* gas/testsuite/gas/sparc/asi-bump-warn.l: Likewise
	* gas/testsuite/gas/sparc/asi-arch-error.s: Likewise
	* gas/testsuite/gas/sparc/asi-arch-error.l: Likewise
2017-02-24 00:23:50 -08:00
Maciej W. Rozycki
c1556ecd78 MIPS/BFD: Discard ineligible JALR relocations right away
Discard R_MIPS_JALR and R_MICROMIPS_JALR relocations associated with
jumps that cannot be converted to an equivalent branch right away in
`mips_elf_calculate_relocation' rather than letting them through to
`mips_elf_perform_relocation'.  This includes cross-mode jumps which
need to flip the ISA bit or jumps to a misaligned location that cannot
be encoded with a branch, in addition to preemptible symbol references
already handled.

Cross-mode jumps are actually already rejected as the conversion is made
in `mips_elf_perform_relocation', so in this case this change only saves
some processing.  Jumps to a misaligned location are however converted,
with bits causing misalignment lost, making resulting code functionally
different even if the lone effect is avoiding an address error exception
with an instruction fetch at the jump destination requested.

Add test cases suitable, also including GAS verification to confirm that
the JALR relocations explicitly requested have indeed been output in the
intermediate objects used.

	bfd/
	* elfxx-mips.c (mips_elf_calculate_relocation) <R_MIPS_JALR>
	<R_MICROMIPS_JALR>: Discard relocation if `cross_mode_jump_p'
	or misaligned.

	gas/
	* testsuite/gas/mips/jalr4.d: New test.
	* testsuite/gas/mips/jalr4-n32.d: New test.
	* testsuite/gas/mips/jalr4-n64.d: New test.
	* testsuite/gas/mips/jalr4.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.

	ld/
	* testsuite/ld-mips-elf/jalr4.dd: New test.
	* testsuite/ld-mips-elf/mips-elf.exp: Run the new test.
2017-02-23 23:45:14 +00:00
Sheldon Lobo
1e9d41d49f opcodes,gas: associate SPARC ASIs with an architecture level.
With this change an architecture level bump due to assembly ASIs will show
up as a warning/error depending on options passed to gas.

Tested with sparc64-linux-gnu, and it does not introduce any regressions.

gas/ChangeLog:

	Add support for associating SPARC ASIs with an architecture level.
	* config/tc-sparc.c (parse_sparc_asi): New encode SPARC ASIs.

opcodes/ChangeLog:

	Add support for associating SPARC ASIs with an architecture level.
	* include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
	* opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
	decoding of SPARC ASIs.
2017-02-23 07:53:16 -08:00
Jan Beulich
946416fc5a gas: slightly relax .startof.()/.sizeof.() testcase 2017-02-23 11:21:10 +01:00
Jan Beulich
4c5b8d1e01 x86: extend 64-bit invalid MPX insn forms testcase 2017-02-23 11:00:44 +01:00
Maciej W. Rozycki
5ff6a06c21 GAS: Consistently fix labels at the `.end' pseudo-op
Fix a functional regression with the `.end' pseudo-op, introduced with
commit ecb4347ade ("Last take: approval for MIPS_STABS_ELF killing"),
<https://sourceware.org/ml/binutils/2002-06/msg00443.html>, and commit
dcd410fe15 ("GNU as 2.14 on IRIX 6: crashes with shared libs"),
<https://sourceware.org/ml/binutils/2003-07/msg00415.html>, which caused
symbol values for labels placed between the end of a function's contents
and its terminating `.end' followed by one of the alignment pseudo-ops
to be different depending on whether either `-mdebug', or `-mno-pdr', or
neither of the command-line options is in effect, be it implied or
specified.

Given debug-label-end.s as follows and the `mips-linux' target we have:

$ cat debug-label-end.s
	.text

	.globl	foo
	.globl	bar
	.align	4, 0
	.ent	foo
foo:
	nop
	.aent	bar
bar:
	.insn
	.end	foo
	.align	4, 0
	.space	16

	.globl	baz
	.ent	baz
baz:
	nop
	.end	baz
	.align	4, 0
	.space	16
$ as -o debug-label-end.o debug-label-end.s
$ readelf -s debug-label-end.o | grep bar
     9: 00000004     0 FUNC    GLOBAL DEFAULT    1 bar
$ as -mdebug -o debug-label-end.o debug-label-end.s
$ readelf -s debug-label-end.o | grep bar
     9: 00000010     0 FUNC    GLOBAL DEFAULT    1 bar
$ as -mno-pdr -o debug-label-end.o debug-label-end.s
$ readelf -s debug-label-end.o | grep bar
     8: 00000010     0 FUNC    GLOBAL DEFAULT    1 bar
$

The reason is the call to `md_flush_pending_output', which in the case
of `mips*-*-*' targets expands to `mips_emit_delays', which in turn
calls `mips_no_prev_insn', which calls `mips_clear_insn_labels', which
clears the list of outstanding labels.  That list is in turn consulted
in `mips_align', called in the interpretation of alignment directives,
and the labels adjusted to the current location.

A call to `md_flush_pending_output' is only made from `s_mips_end' and
then only if `-mpdr' is in effect, which is the default for `*-*-linux*'
and some other `mips*-*-*' targets.  A call to `md_flush_pending_output'
is never made from `ecoff_directive_end', which is used in place of
`s_mips_end' when `-mdebug' is in effect.  Consequently if `-mno-pdr' or
`-mdebug' is in effect the list of outstanding labels makes it through
to any alignment directive that follows and the labels are differently
interpreted depending on the command-lines options used.  And we want
code produced to be always the same.

Call `md_flush_pending_output' unconditionally then in `s_mips_end' and
add such a call from `ecoff_directive_end' as well, as long as the macro
is defined.  While `ecoff_directive_end' is shared among targets, the
only one other than `mips*-*-*' actually using it is `alpha*-*-*' and it
does not define `md_flush_pending_output'.  So the semantics isn't going
to change for it and neither it has to have its `s_alpha_end' updated
or have code in `ecoff_directive_end' conditionalized.

	gas/
	* ecoff.c (ecoff_directive_end) [md_flush_pending_output]: Call
	`md_flush_pending_output'.
	* config/tc-mips.c (s_mips_end) [md_flush_pending_output]: Call
	`md_flush_pending_output' unconditionally.
	* testsuite/gas/mips/debug-label-end-1.d: New test.
	* testsuite/gas/mips/debug-label-end-2.d: New test.
	* testsuite/gas/mips/debug-label-end-3.d: New test.
	* testsuite/gas/mips/debug-label-end.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.
2017-02-22 18:15:33 +00:00
Hans-Peter Nilsson
25890fc239 Fix gas/all/err-sizeof.s for cris*-*-* 2017-02-22 14:17:33 +01:00