2018-09-17 Kito Cheng <kito@andestech.com>
gas/
* testsuite/gas/riscv/bge.d: New.
* testsuite/gas/riscv/bge.s: Likewise.
opcodes/
* riscv-opc.c (riscv_opcodes): Adjust the order of ble and
bleu.
Add -mvexwig=[0|1] option to x86 assembler to control how the assembler
should encode the VEX.W bit in WIG VEX instructions.
* gas/NEWS: Mention -mvexwig=[0|1] option.
* config/tc-i386.c (vexwig): New.
(build_vex_prefix): Set the VEX.W bit for -mvexwig=1 for WIG
VEX instructions.
(OPTION_MVEXWIG): New.
(md_longopts): Add -mvexwig=.
(md_parse_option): Handle OPTION_MVEXWIG.
(md_show_usage): Show -mvexwig=[0|1].
* doc/c-i386.texi: Document -mvexwig=[0|1].
* testsuite/gas/i386/avx-wig.d: New file.
* testsuite/gas/i386/avx-wig.s: Likewise.
* testsuite/gas/i386/avx2-wig.d: Likewise.
* testsuite/gas/i386/avx2-wig.s: Likewise.
* testsuite/gas/i386/x86-64-avx-wig.d: Likewise.
* testsuite/gas/i386/x86-64-avx-wig.s: Likewise.
* testsuite/gas/i386/x86-64-avx2-wig.d: Likewise.
* testsuite/gas/i386/x86-64-avx2-wig.s: Likewise.
* testsuite/gas/i386/i386.exp: Run avx-wig, avx2-wig,
x86-64-avx-wig and x86-64-avx2-wig.
binutils* testsuite/binutils-all/compress.exp: Rename second "objcopy
zlib-gnu compress debug sections 3" test to "objcopy zlib-gabi
compress debug sections 3" and use gabi object files instead
of gnu object files.
* testsuite/binutils-all/objcopy.exp: Add suffix to the names
of the "ELF group" tests.
* testsuite/binutils-all/readelf.exp (proc readelf_find_size):
Add an iteration parameter and include it in the name of the
test. Update callers to include an iteration count.
gas * testuite/gas/elf/group0a.d: Add extra details to the test
name.
* testuite/gas/elf/group0b.d: Likewise.
* testuite/gas/elf/group1a.d: Likewise.
* testuite/gas/elf/group1b.d: Likewise.
* testuite/gas/elf/group0b.d: Likewise.
* testuite/gas/elf/section9.d: Likewise.
* testuite/gas/i386/ilp32/lns/lns-common-1.d: Likewise.
* testuite/gas/i386/ilp32/lns/lns-duplicate-1.d: Likewise.
ld * testuite/ld/ld-elf/audit.exp: Differentiate the names of the
two "Run with shared with --audit" tests.
* testuite/ld/ld-elf/compress.exp: Differentiate the zlib
compressed debug output test names.
* testuite/ld/ld-i386/tlspie1.d: Add extra details to the test
name.
* testuite/ld/ld-i386/tlspie2.d: Likewise.
* testuite/ld/ld-size/size.exp: Add missing escapes to the end
of lines in the size-3e test.
* testuite/ld/ld-unique/unique.exp: Differentiate the names of
the two "Checking unique PIC object" tests.
* testuite/ld/ld-x86-64/tlspie1.d: Add extra details to the test
name.
AVX "VMOVQ xmm1, xmm2/m64" and "VMOVQ xmm1/m64, xmm2" can only be
encoded with VEX.128. Set Vex=1 on VEX.128 only vmovq and update
assembler tests.
gas/
PR gas/23665
* testsuite/gas/i386/avx-scalar-intel.d: Updated.
* testsuite/gas/i386/avx-scalar.d: Likewise.
* testsuite/gas/i386/x86-64-avx-scalar-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx-scalar.d: Likewise.
opcodes/
PR gas/23665
* i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
VEX_LEN_0FD6_P_2 entries.
* i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
* i386-tbl.h: Regenerated.
This merges the three versions of run_dump_test. Improved warning
handling versus the old gas version shows up a number of tests that
need their disassembly updating:
arm-linuxeabi +FAIL: ARM v1 instructions
arm-linuxeabi +FAIL: Accepted v8-a with ARMv8.1 AdvSIMD.
arm-linuxeabi +FAIL: bl local instructions for v4t.
arm-linuxeabi +FAIL: UDF
and some that now fail due to detecting assembly warnings:
h8300-elf +FAIL: binutils-all/strip-13
h8300-elf +FAIL: binutils-all/strip-14
h8300-elf +FAIL: binutils-all/strip-15
I've generally kept the union of all run_dump_test features, except
that the ld target aliases "cfi" and "shared" have disappeared, as has
the binutils substitution of $srcdir as $scrdir/$subdir.
binutils/
* testsuite/binutils-all/add-symbol.d: Add "section_subst: no".
* testsuite/binutils-all/elfedit.exp: Don't set tempfile or copyfile.
* testsuite/binutils-all/symbols-1.d,
* testsuite/binutils-all/symbols-2.d,
* testsuite/binutils-all/symbols-3.d,
* testsuite/binutils-all/symbols-4.d: Quote '*' and '!'.
* testsuite/binutils-all/add-empty-section.d,
* testsuite/binutils-all/add-section.d,
* testsuite/binutils-all/elfedit.exp,
* testsuite/binutils-all/note-1.d,
* testsuite/binutils-all/pr23633.d: Add $subdir after $srcdir.
* testsuite/config/default.exp (AS, ASFLAGS): Define.
* testsuite/config/hppa.sed: Handle all common symbols.
* testsuite/lib/binutils-common.exp (run_dump_test): New proc,
merged from three other versions.
(slurp_options, file_contents, set_file_contents): Likewise.
(big_or_little_endian, get_standard_section_names): Likewise.
* testsuite/lib/utils-lib.exp (run_dump_test): Delete.
(slurp_options, proc file_contents): Delete.
(get_standard_section_names): Delete.
gas/
* testsuite/config/default.exp: Make tmpdir.
* testsuite/lib/gas-defs.exp (run_dump_test): Delete.
(get_standard_section_names, slurp_options): Delete.
ld/
* testsuite/ld-d10v/reloc-007.d,
* testsuite/ld-d10v/reloc-008.d,
* testsuite/ld-d10v/reloc-015.d,
* testsuite/ld-d10v/reloc-016.d: Remove "error:".
* testsuite/ld-elf/eh-frame-hdr.d,
* testsuite/ld-elf/eh5.d,
* testsuite/ld-gc/personality.d: Replace "cfi" and "shared" in
target list with appropriate proc.
* testsuite/ld-elf/frame.exp: Use check_shared_lib_support rather
than "istarget shared".
* testsuite/lib/ld-lib.exp (proc big_or_little_endian): Delete.
(run_dump_test, slurp_options, file_contents): Delete.
(set_file_contents, istarget): Delete.
We have three copies of run_dump_test in the testsuite. This is a first
step towards consolidating them.
A few tests use objcopy to convert to verilog or srec output, then
check that output is as expected. Those tests can just as easily use
objdump, keeping the set of dump programs (addr2line, nm, objdump,
readelf, size) separate from utilities under test. That in turn makes
auto-detecting the dump program possible in more places.
binutils/
* testsuite/binutils-all/group-7a.d,
* testsuite/binutils-all/group-7b.d,
* testsuite/binutils-all/group-7c.d,
* testsuite/binutils-all/symbols-1.d,
* testsuite/binutils-all/symbols-2.d,
* testsuite/binutils-all/symbols-3.d,
* testsuite/binutils-all/symbols-4.d: Remove DUMPPROG.
gas/
* testsuite/gas/mri/char.d: Don't objcopy to srec, objdump instead.
* testsuite/gas/mri/float.d: Likewise.
* testsuite/lib/gas-defs.exp (run_dump_test): Remove support
for objcopy as a dump tool.
ld/
* testsuite/ld-elf/interleave-0.d,
* testsuite/ld-elf/interleave-4.d: Don't objcopy to srec,
objdump instead.
* testsuite/ld-gc/all-debug-sections.d,
* testsuite/ld-scripts/provide-4.d,
* testsuite/ld-scripts/provide-5.d,
* testsuite/ld-scripts/provide-6.d,
* testsuite/ld-scripts/provide-7.d,
* testsuite/ld-scripts/provide-8.d,
* testsuite/ld-scripts/segment-start.d: Remove PROG, specify
nm instead.
* testsuite/lib/ld-lib.exp (run_dump_test): Remove support
for objcopy as a dump tool.
Verify that -mevexwig=1 has no impact on non-WIG EVEX instruction encoding.
PR gas/23642
* testsuite/gas/i386/evex-wig2.d: New file.
* testsuite/gas/i386/evex-wig2.s: Likewise.
* testsuite/gas/i386/x86-64-evex-wig2.d: Likewise.
* testsuite/gas/i386/x86-64-evex-wig2.s: Likewise.
* testsuite/gas/i386/i386.exp: Run evex-wig2 and
x86-64-evex-wig2.
Update x86 disassembler to ignore the EVEX.W bit in EVEX vcvt[u]si2s[sd]
instructions in 32-bit mode.
gas/
PR binutils/23655
* testsuite/gas/i386/evex.d: New file.
* testsuite/gas/i386/evex.s: Likewise.
* testsuite/gas/i386/i386.exp: Run evex.
opcodes/
PR binutils/23655
* i386-dis-evex.h (evex_table): Replace Eq with Edqa for
vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
* i386-dis.c (Edqa): New.
(dqa_mode): Likewise.
(intel_operand_size): Handle dqa_mode as m_mode.
(OP_E_register): Handle dqa_mode as dq_mode.
(OP_E_memory): Set shift for dqa_mode based on address_mode.
Various moves come in load and store forms, and just like on the GPR
and FPU sides there would better be only one pattern. In some cases this
is not feasible because the opcodes are too different, but quite a few
cases follow a similar standard scheme. Introduce Opcode_SIMD_FloatD and
Opcode_SIMD_IntD, generalize handling in operand_size_match() (reverse
operand handling there simply needs to match "straight" operand one),
and fix a long standing, but so far only latent bug with when to zap
found_reverse_match.
Also once again drop IgnoreSize where pointlessly applied to templates
touched anyway as well as *word when redundant with Reg*.
In quite a few cases the .s suffix or {load} / {store} prefixes did not
work as intended, or produced errors when they're supposed to be ignored
when it is not possible to carry out the request.
The change here re-purposes(?) the .s suffix to no longer mean "store"
(if that's what 's' did stand for), since the forms used in the base
templates are not consistently loads (and we unlikely want to change
that). The pseudo prefixes will now fulfill what their names say, i.e.
{load} now only ever produces a load form encoding (if available) while
{store} only ever produces a store form one (again if available). This
requires minimal test suite adjustments, while the majority of the
changes there are simply additions.
Sparc V8 does not allow fpop2 instructions (floating point
comparisons) immediately before floating point branches. From the
SPARC Architecture Manual Version 8, section B.22 "Branch on
Floating-point Condition Codes Instructions":
"If the instruction executed immediately before an FBfcc is an FPop2
instruction, the result of the FBfcc is undefined. Therefore, at
least one non FPop2 instruction should be executed between the FPop2
instruction and the FBfcc instruction."
The existing check in GAS, however, does not allow any kind of
floating point instruction before the branch. This patch adds an
extra condition to only disallow fpop2 instructions.
gas/ChangeLog:
2018-09-04 Daniel Cederman <cederman@gaisler.com>
* config/tc-sparc.c (md_assemble): Allow non-fpop2 instructions
before floating point branches for Sparc V8 and earlier.
* testsuite/gas/sparc/sparc.exp: Execute the new test.
* testsuite/gas/sparc/v8branch.d: New test.
* testsuite/gas/sparc/v8branch.s: New test.
We will get an XPASS when h8300 port peculiarities are fixed, and will
fix the testsuite too.
* testsuite/gas/elf/section14.d: Change skip to xfail.
* testsuite/lib/gas-defs.exp (run_dump_test): Add xfail support.
Since x86 assembler may generate .note.gnu.property section, pass
-mx86-used-note=no to assembler for section2 test on ELF/x86 targets
to avoid .note.gnu.property section.
* testsuite/gas/elf/elf.exp: Pass -mx86-used-note=no to
assembler for section2 test on ELF/x86 targets.
Since cfi/cfi-label.d is ELF/x86 specific, we can pass -mx86-used-note=no
to assembler.
* testsuite/gas/cfi/cfi-label.d: Pass -mx86-used-note=no to
assembler.
Skip elf/section14 test for h8300 targets since the h8300 port issues a
warning message for new sections created without atrributes.
* testsuite/gas/elf/section14.d: Skip h8300 targets.
Since SHT_FINI_ARRAY and SHT_PREINIT_ARRAY sections are relocatable,
this patch fixes readelf and adds a testcase.
binutils/
* readelf.c (process_section_headers): Treat SHT_FINI_ARRAY and
SHT_PREINIT_ARRAY as relocatable sections.
gas/
* testsuite/gas/elf/elf.exp: Run section14.
* testsuite/gas/elf/section14.d: New file.
* testsuite/gas/elf/section14.s: Likewise.
Partial write %PSR (PWRPSR) is a SPARC V8e option that allows the WRPSR
instruction to only affect the %PSR.ET field. When available it is enabled
by setting the rd field of the WRPSR instruction to a value other than 0.
For Leon processors with support for partial write %PSR (currently GR740
and GR716) the rd value must be 1.
opcodes/ChangeLog:
2018-08-29 Martin Aberg <maberg@gaisler.com>
* sparc-opc.c (sparc_opcodes): Add Leon specific partial write
psr (PWRPSR) instruction.
gas/ChangeLog:
2018-08-29 Daniel Cederman <cederman@gaisler.com>
* testsuite/gas/sparc/leon.d: New test.
* testsuite/gas/sparc/leon.s: New test.
* testsuite/gas/sparc/sparc.exp: Execute the pwrpsr test.
Since only the GNU_PROPERTY_X86_UINT32_VALID bit may be set in data-only
relocatable objects which don't contain any instructions, linker
shouldn't mask out the GNU_PROPERTY_X86_UINT32_VALID bit when merging
GNU_PROPERTY_X86_XXX bits. Otherwise, linker output doesn't contain
GNU_PROPERTY_X86_XXX property with any data-only relocatable inputs.
This patch keeps the GNU_PROPERTY_X86_UINT32_VALID bit and updates
readelf to print "<None>" if GNU_PROPERTY_X86_XXX property only has
the GNU_PROPERTY_X86_UINT32_VALID bit.
bfd/
* elfxx-x86.c (_bfd_x86_elf_parse_gnu_properties): Don't mask
out the GNU_PROPERTY_X86_UINT32_VALID bit.
binutils/
* readelf.c (decode_x86_isa): Print <None> if bitmask only
contains the GNU_PROPERTY_X86_UINT32_VALID bit.
(decode_x86_feature_1): Likewise.
(decode_x86_feature_2): Likewise.
(print_gnu_property_note): Don't mask out the
GNU_PROPERTY_X86_UINT32_VALID bit.
* testsuite/binutils-all/i386/pr21231b.d: Updated.
* testsuite/binutils-all/x86-64/pr21231b.d: Likewise.
gas/
* testsuite/gas/i386/i386.exp: Run property-1 and
x86-64-property-1.
* testsuite/gas/i386/property-1.d: New file.
* testsuite/gas/i386/property-1.s: Likewise.
* testsuite/gas/i386/x86-64-property-1.d: Likewise.
ld/
* testsuite/ld-i386/i386.exp: Run property-x86-5.
* testsuite/ld-i386/property-x86-5.d: New file.
* testsuite/ld-x86-64/property-x86-5-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-5.d: Likewise.
* testsuite/ld-x86-64/property-x86-5a.s: Likewise.
* testsuite/ld-x86-64/property-x86-5b.s: Likewise.
* testsuite/ld-x86-64/x86-64.exp: Run property-x86-5 and
property-x86-5-x32.
Bit manipulation instructions which are not normally generated by the
assembler, should nevertheless be decoded by the disassembler.
opcodes/
* s12z-dis.c: BM_RESERVED1 to behave like BM_OPR_REG, and
BM_RESERVED0 like BM_REG_IMM.
In 64-bit mode, display eiz for address with the addr32 prefix and without
base nor index registers. For
mov -0xccddef(,%eiz,), %rax
disassembler now displays:
67 48 8b 04 25 11 22 33 ff mov -0xccddef(,%eiz,1),%rax
instead of
67 48 8b 04 25 11 22 33 ff addr32 mov 0xffffffffff332211,%rax
gas/
* testsuite/gas/i386/evex-no-scale-64.d: Updated.
* testsuite/gas/i386/x86-64-addr32-intel.d: Likewise.
* testsuite/gas/i386/x86-64-addr32.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-addr32-intel.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-addr32.d: Likewise.
* testsuite/gas/i386/x86-64-addr32.s: Add %eiz tests.
opcodes/
* i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
address with the addr32 prefix and without base nor index
registers.
For 32-bit x86 assembler, --64 and --x32 are unsupported if BFD64 is
undefined. Even if BFD64 is defined, --64 and --x32 still may not be
supported if x86-64 support isn't compiled in:
[hjl@gnu-hsw-1 gas]$ ./as-new --64 -o x.o x.s
Assembler messages:
Fatal error: no compiled in support for x86_64
[hjl@gnu-hsw-1 gas]$ ./as-new --x32 -o x.o x.s
Assembler messages:
Fatal error: no compiled in support for 32bit x86_64
[hjl@gnu-hsw-1 gas]$
This patch removes --32/--64/--x32 from md_show_usage if BFD64 is
undefined and runs code64-inval only if BFD64 is undefined.
* config/tc-i386.c (md_show_usage): Don't display --32/--64/--x32
if BFD64 is undefined.
* testsuite/gas/i386/i386.exp (gas_bfd64_check): New.
Run code64-inval if gas_bfd64_check fails.
PR 23481
* config/tc-pdp11.c (parse_op_noreg): Check for deferred register
addressing before assuming non-deferred addressing.
* testsuite/gas/pdp11/pr23481.s: New test source file.
* testsuite/gas/pdp11/pr23481.d: New test driver file.
* testsuite/gas/pdp11/pdp11.exp: Run the new test.
Check if an input asm file is rf16 compliant; if not, and the tag says
otherwise, fix the tag and emit a warning.
gas/
2017-09-20 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (rf16_only): New static variable.
(autodetect_attributes): Check if we are rf16 compliant.
(arc_set_public_attributes): Fix and emit the warning is required.
* testsuite/gas/arc/attr-rf16.d: New file.
* testsuite/gas/arc/attr-rf16.err: Likewise.
* testsuite/gas/arc/attr-rf16.s: Likewise.
evex-no-scale.s has ELF directive:
.section .probe, "", @progbits
and non-ELF targets may pad text sections.
* testsuite/gas/i386/i386.exp: Run evex-no-scale-32 and
evex-no-scale-64 only for ELF targets.
* testsuite/gas/i386/prefix32.s: Append ".p2align 4,0".
* testsuite/gas/i386/prefix64.s: Likewise.
* testsuite/gas/i386/prefix32.l: Updated.
* testsuite/gas/i386/prefix64.l: Likewise.
PR 14480
* config/tc-pdp11.c (parse_op_noreg): Check for and handle auto
increment deferred.
* testsuite/gas/pdp11/pr14480.d: New test driver file.
* testsuite/gas/pdp11/pr14480.s: New test source file file.
* testsuite/gas/pdp11/pdp11.exp: Run the new test.
