Interpret the `jalr $0, $25' instruction encoding with an R_MIPS_JALR
relocation attached as an alias to `jr $25' and convert the jump to an
equivalent branch where possible, consequently covering the MIPSr6
architecture for the purpose of this optimization too.
bfd/
* elfxx-mips.c (mips_elf_perform_relocation): Also handle the
`jalr $0, $25' instruction encoding.
gas/
* testsuite/gas/mips/jalr4.s: Add `jalr $0, $25' instructions.
* testsuite/gas/mips/jalr4.d: Adjust accordingly. Remove MIPSr6
encoding patterns.
* testsuite/gas/mips/jalr4-n64.d: Likewise.
* testsuite/gas/mips/mipsr6@jalr4.d: New test.
* testsuite/gas/mips/mipsr6@jalr4-n32.d: New test.
* testsuite/gas/mips/mipsr6@jalr4-n64.d: New test.
ld/
* testsuite/ld-mips-elf/jalr4.dd: Adjust for `jalr $0, $25'
instructions.
* testsuite/ld-mips-elf/jalr4-r6.dd: New test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new test.
HPUX has a different .comm syntax, and anything in the first column
is a label.
gas/
* testsuite/gas/elf/strtab.s: Don't put directives on first
column or continuation with labels not in first column.
ld/
* testsuite/ld-elf/elf.exp: Xfail pr20995 tests on hppa64-hpux.
Set up HPUX defsym. Run pr14170 tests and build symbol3 objects,
defining HPUX where necessary. Define HPUX for implib tests.
* testsuite/ld-elf/comm-data4.d: Run for hpux.
* testsuite/ld-elf/endsym.d: Likewise.
* testsuite/ld-elf/linkoncerdiff.d: Likewise.
* testsuite/ld-elf/comm-data4.s: Add alternate .comm when HPUX.
* testsuite/ld-elf/comm-data5.s: Likewise.
* testsuite/ld-elf/endsym.s: Likewise.
* testsuite/ld-elf/pr14170c.s: Likewise.
* testsuite/ld-elf/symbol3.s: Likewise.
* testsuite/ld-elf/implib.s: Likewise. Don't start directives
in first column.
* testsuite/ld-elf/linkoncerdiff2.s: Don't use numeric labels.
* testsuite/ld-elf/warn3.d: Run for hpux.
* testsuite/ld-scripts/rgn-at10.d: Xfail for hpux.
* testsuite/ld-scripts/rgn-at11.d: Likewise.
* testsuite/ld-scripts/size-2.d: Remove xfail for hpux.
This patch supports some additions to the SVE architecture prior to
its public release.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16)
(AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2)
(AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX)
(AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
(OP_SVE_V_HSD): New macros.
(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
(aarch64_opcode_table): Add new SVE instructions.
(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
for rotation operands. Add new SVE operands.
* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
(ins_sve_quad_index): Likewise.
(ins_imm_rotate): Split into...
(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
functions.
(aarch64_ins_sve_addr_ri_s4): New function.
(aarch64_ins_sve_quad_index): Likewise.
(do_misc_encoding): Handle "MOV Zn.Q, Qm".
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
(ext_sve_quad_index): Likewise.
(ext_imm_rotate): Split into...
(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
functions.
(aarch64_ext_sve_addr_ri_s4): New function.
(aarch64_ext_sve_quad_index): Likewise.
(aarch64_ext_sve_index): Allow quad indices.
(do_misc_decoding): Likewise.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
aarch64_field_kinds.
(OPD_F_OD_MASK): Widen by one bit.
(OPD_F_NO_ZR): Bump accordingly.
(get_operand_field_width): New function.
* aarch64-opc.c (fields): Add new SVE fields.
(operand_general_constraint_met_p): Handle new SVE operands.
(aarch64_print_operand): Likewise.
* aarch64-opc-2.c: Regenerate.
gas/
* doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum.
* config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q
to be used with SVE registers.
(parse_operands): Handle new SVE operands.
(aarch64_features): Make "sve" require F16 rather than FP. Also
require COMPNUM.
* testsuite/gas/aarch64/sve.s: Add tests for new instructions.
Include compnum tests.
* testsuite/gas/aarch64/sve.d: Update accordingly.
* testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions.
* testsuite/gas/aarch64/sve-invalid.l: Update accordingly. Also
update expected output for new FMOV and MOV alternatives.
This patch adds a named "compnum" feature for the ARMv8.3-A FCADD
and FCMLA extensions.
include/
* opcode/aarch64.h (AARCH64_FEATURE_COMPNUM): New macro.
(AARCH64_ARCH_V8_3): Include AARCH64_FEATURE_COMPNUM.
opcodes/
* aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
(aarch64_feature_compnum): ...this.
(SIMD_V8_3): Replace with...
(COMPNUM): ...this.
(CNUM_INSN): New macro.
(aarch64_opcode_table): Use it for the complex number instructions.
gas/
* doc/c-aarch64.texi: Add a "compnum" entry.
* config/tc-aarch64.c (aarch64_features): Likewise,
* testsuite/gas/aarch64/advsimd-compnum.s: New test.
* testsuite/gas/aarch64/advsimd-compnum.d: Likewise.
Opcodes F6/1 and F7/1 are aliases of F6/0 and F7/0 in all modes. This
complements commit 8b89fe14b5 ("X86: Decode opcode 0x82 as opcode 0x80
in 32-bit mode"), just that here 64-bit mode is also covered.
gas/ChangeLog:
Test cases for the architecture level aware SPARC ASI work.
* gas/testsuite/gas/sparc/sparc.exp: 2 new tests
* gas/testsuite/gas/sparc/asi-bump-warn.s: New test
* gas/testsuite/gas/sparc/asi-bump-warn.l: Likewise
* gas/testsuite/gas/sparc/asi-arch-error.s: Likewise
* gas/testsuite/gas/sparc/asi-arch-error.l: Likewise
Discard R_MIPS_JALR and R_MICROMIPS_JALR relocations associated with
jumps that cannot be converted to an equivalent branch right away in
`mips_elf_calculate_relocation' rather than letting them through to
`mips_elf_perform_relocation'. This includes cross-mode jumps which
need to flip the ISA bit or jumps to a misaligned location that cannot
be encoded with a branch, in addition to preemptible symbol references
already handled.
Cross-mode jumps are actually already rejected as the conversion is made
in `mips_elf_perform_relocation', so in this case this change only saves
some processing. Jumps to a misaligned location are however converted,
with bits causing misalignment lost, making resulting code functionally
different even if the lone effect is avoiding an address error exception
with an instruction fetch at the jump destination requested.
Add test cases suitable, also including GAS verification to confirm that
the JALR relocations explicitly requested have indeed been output in the
intermediate objects used.
bfd/
* elfxx-mips.c (mips_elf_calculate_relocation) <R_MIPS_JALR>
<R_MICROMIPS_JALR>: Discard relocation if `cross_mode_jump_p'
or misaligned.
gas/
* testsuite/gas/mips/jalr4.d: New test.
* testsuite/gas/mips/jalr4-n32.d: New test.
* testsuite/gas/mips/jalr4-n64.d: New test.
* testsuite/gas/mips/jalr4.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* testsuite/ld-mips-elf/jalr4.dd: New test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new test.
With this change an architecture level bump due to assembly ASIs will show
up as a warning/error depending on options passed to gas.
Tested with sparc64-linux-gnu, and it does not introduce any regressions.
gas/ChangeLog:
Add support for associating SPARC ASIs with an architecture level.
* config/tc-sparc.c (parse_sparc_asi): New encode SPARC ASIs.
opcodes/ChangeLog:
Add support for associating SPARC ASIs with an architecture level.
* include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
* opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
decoding of SPARC ASIs.
Fix a functional regression with the `.end' pseudo-op, introduced with
commit ecb4347ade ("Last take: approval for MIPS_STABS_ELF killing"),
<https://sourceware.org/ml/binutils/2002-06/msg00443.html>, and commit
dcd410fe15 ("GNU as 2.14 on IRIX 6: crashes with shared libs"),
<https://sourceware.org/ml/binutils/2003-07/msg00415.html>, which caused
symbol values for labels placed between the end of a function's contents
and its terminating `.end' followed by one of the alignment pseudo-ops
to be different depending on whether either `-mdebug', or `-mno-pdr', or
neither of the command-line options is in effect, be it implied or
specified.
Given debug-label-end.s as follows and the `mips-linux' target we have:
$ cat debug-label-end.s
.text
.globl foo
.globl bar
.align 4, 0
.ent foo
foo:
nop
.aent bar
bar:
.insn
.end foo
.align 4, 0
.space 16
.globl baz
.ent baz
baz:
nop
.end baz
.align 4, 0
.space 16
$ as -o debug-label-end.o debug-label-end.s
$ readelf -s debug-label-end.o | grep bar
9: 00000004 0 FUNC GLOBAL DEFAULT 1 bar
$ as -mdebug -o debug-label-end.o debug-label-end.s
$ readelf -s debug-label-end.o | grep bar
9: 00000010 0 FUNC GLOBAL DEFAULT 1 bar
$ as -mno-pdr -o debug-label-end.o debug-label-end.s
$ readelf -s debug-label-end.o | grep bar
8: 00000010 0 FUNC GLOBAL DEFAULT 1 bar
$
The reason is the call to `md_flush_pending_output', which in the case
of `mips*-*-*' targets expands to `mips_emit_delays', which in turn
calls `mips_no_prev_insn', which calls `mips_clear_insn_labels', which
clears the list of outstanding labels. That list is in turn consulted
in `mips_align', called in the interpretation of alignment directives,
and the labels adjusted to the current location.
A call to `md_flush_pending_output' is only made from `s_mips_end' and
then only if `-mpdr' is in effect, which is the default for `*-*-linux*'
and some other `mips*-*-*' targets. A call to `md_flush_pending_output'
is never made from `ecoff_directive_end', which is used in place of
`s_mips_end' when `-mdebug' is in effect. Consequently if `-mno-pdr' or
`-mdebug' is in effect the list of outstanding labels makes it through
to any alignment directive that follows and the labels are differently
interpreted depending on the command-lines options used. And we want
code produced to be always the same.
Call `md_flush_pending_output' unconditionally then in `s_mips_end' and
add such a call from `ecoff_directive_end' as well, as long as the macro
is defined. While `ecoff_directive_end' is shared among targets, the
only one other than `mips*-*-*' actually using it is `alpha*-*-*' and it
does not define `md_flush_pending_output'. So the semantics isn't going
to change for it and neither it has to have its `s_alpha_end' updated
or have code in `ecoff_directive_end' conditionalized.
gas/
* ecoff.c (ecoff_directive_end) [md_flush_pending_output]: Call
`md_flush_pending_output'.
* config/tc-mips.c (s_mips_end) [md_flush_pending_output]: Call
`md_flush_pending_output' unconditionally.
* testsuite/gas/mips/debug-label-end-1.d: New test.
* testsuite/gas/mips/debug-label-end-2.d: New test.
* testsuite/gas/mips/debug-label-end-3.d: New test.
* testsuite/gas/mips/debug-label-end.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Implement the ECOFF `.aent' pseudo-op for ECOFF-style `.mdebug' section
support with ELF objects and, for consistency, also with ECOFF objects.
This is so that the same MIPS source can be assembled without and with
`.mdebug' section generation enabled.
Taking the `gas/testsuite/gas/mips/aent.s' test case source as an
example and the `mips-linux' target we have:
$ as -o aent.o aent.s
$ as -mdebug -o aent.o aent.s
aent.s: Assembler messages:
aent.s:10: Error: unknown pseudo-op: `.aent'
$
because for the !ECOFF_DEBUGGING case (which is the default) the
pseudo-op is already handled by the MIPS backend with `s_mips_ent',
however no handler is present for the opposite case.
For the MIPS target this is a functional regression introduced with
commit ecb4347ade ("Last take: approval for MIPS_STABS_ELF killing"),
<https://sourceware.org/ml/binutils/2002-06/msg00443.html>, where
support for the `.mdebug' section was added along with its associated
`-mdebug'/`-no-mdebug' command-line options, bringing an inconsistency
between the assembly syntax supported for each of these options as far
as the `.aent' pseudo-op is concerned.
Assembly language documentation available describes the pseudo-op
respectively as follows[1]:
"
.aent name, symno Sets an alternate entry point for the current
procedure. Use this information when you want
to generate information for the debugger. It must
appear inside an .ent/.end pair."
and[2]:
"
.aent name [,symno]
Sets an alternate entry point for the current procedure. Use this
information when you want to generate information for the debugger.
This directive must appear between a pair of .ent and .end directives.
(The optional symno is for compiler use only. It refers to a dense
number in a .T file (symbol table).)"
Copy the approach from `s_mips_ent' then and add `.aent' support to the
`.ent' pseudo-op handler shared between the ELF and ECOFF object file
format backends, by setting BSF_FUNCTION for the symbol requested.
References:
[1] "MIPSpro Assembly Language Programmer's Guide", Silicon Graphics,
Inc., Document Number 007-2418-004, Section 8.1 "Op-Codes", p. 96
<http://techpubs.sgi.com/library/manuals/2000/007-2418-004/pdf/007-2418-004.pdf>
[2] "Digital UNIX Assembly Language Programmer's Guide", Digital
Equipment Corporation, Order Number: AA-PS31D-TE, March 1996,
Chapter 5 "Assembler Directives", p. 5-2
<http://h41361.www4.hpe.com/docs/base_doc/DOCUMENTATION/V40G_PDF/APS31DTE.PDF>
gas/
* ecoff.c (ecoff_directive_ent, add_procedure): Handle `.aent'.
* config/obj-ecoff.c (obj_pseudo_table): Add "aent" entry.
* config/obj-elf.c (ecoff_debug_pseudo_table): Likewise.
* testsuite/gas/mips/aent-2.d: New test.
* testsuite/gas/mips/aent-mdebug.d: New test.
* testsuite/gas/mips/aent-mdebug-2.d: New test.
* testsuite/gas/mips/mips.exp: Run the new tests.
This patch adds the SVE-specific system registers.
opcodes/
* aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
(aarch64_sys_reg_supported_p): Handle them.
gas/
* testsuite/gas/aarch64/sve-sysreg.s,
testsuite/gas/aarch64/sve-sysreg.d,
testsuite/gas/aarch64/sve-sysreg-invalid.d,
testsuite/gas/aarch64/sve-sysreg-invalid.l: New tests.
The documentation entry for the SVE feature incorrectly said that
it was enabled by default for ARMv8-A or later. This patch fixes
that and also mentions that +sve implies +simd. (It also implies
+fp, but that follows by transitivity.)
gas/
* doc/c-aarch64.texi: Fix sve entry.
opcodes * arc-regs.h: Distinguish some of the registers different on
ARC700 and HS38 cpus.
gas * testsuite/gas/arc/st.d: Update for 0xe having a name now
This stops powerpc gas blithely accepting such nonsense as
"addi %f4,%cr3,%r31".
PR 21118
gas/
* NEWS: Mention powerpc register checks.
* config/tc-ppc.c (struct pd_reg): Make value a short. Add flags.
(pre_defined_registers): Delete fpscr and pmr entries. Set
register type in flags.
(cr_names): Set type in flags.
(reg_name_search): Return pointer to struct pd_reg rather than value.
(register_name): Adjust to suit. Set X_md from flags.
(ppc_parse_name): Likewise.
(ppc_optimize_expr): New function.
(md_assemble): Verify expresion reg flags match operand.
* config/tc-ppc.h (md_optimize_expr): Define.
(ppc_optimize_expr): Declare.
include/
* opcode/ppc.h (PPC_OPERAND_*): Reassign values, regs first.
(PPC_OPERAND_SPR, PPC_OPERAND_GQR): Define.
opcodes/
* ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
PR 21118 work exposed these errors in the testsuite.
* testsuite/gas/ppc/cell.s: Correct invalid registers.
* testsuite/gas/ppc/vle-simple-1.s: Likewise.
* testsuite/gas/ppc/vle-simple-2.s: Likewise.
2017-02-13 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (parse_ifimm_zero): Make prefix optional in unified
syntax.
* testsuite/gas/arm/vcmp-noprefix-imm.d: New file.
* testsuite/gas/arm/vcmp-noprefix-imm.s: New file.
Include the detailed MIPS option description in the man page along with
other target descriptions and complementing the terse list earlier on.
gas/
* doc/as.texinfo (Overview): Select MIPS options for man page
inclusion.
Complement commit 9d862524f6 ("MIPS: Verify the ISA mode and alignment
of branch and jump targets") and add GAS and LD options to control the
checks for invalid branches between ISA modes introduced there, to help
with some handwritten code lacking `.insn' annotation for labels used as
branch targets and code produced by older versions of GCC which suffers
from the issue with branches to code that has been optimized away,
addressed with GCC commit 242424 ("MIPS/GCC: Mark trailing labels with
`.insn'"), <https://gcc.gnu.org/ml/gcc-patches/2016-11/msg01061.html>.
bfd/
* elfxx-mips.h (_bfd_mips_elf_insn32): Rename prototype to...
(_bfd_mips_elf_linker_flags): ... this. Add another parameter.
* elfxx-mips.c (mips_elf_link_hash_table): Add
`ignore_branch_isa' member.
(mips_elf_perform_relocation): Do not treat an ISA mode mismatch
in branch relocation calculation as an error if
`ignore_branch_isa' has been set.
(_bfd_mips_elf_insn32): Rename to...
(_bfd_mips_elf_linker_flags): ... this. Rename the `on'
parameter to `insn32' and add an `ignore_branch_isa' parameter.
Handle the new parameter.
gas/
* config/tc-mips.c (mips_ignore_branch_isa): New variable.
(options): Add OPTION_IGNORE_BRANCH_ISA and
OPTION_NO_IGNORE_BRANCH_ISA enum values.
(md_longopts): Add "mignore-branch-isa" and
"mno-ignore-branch-isa" options.
(md_parse_option): Handle OPTION_IGNORE_BRANCH_ISA and
OPTION_NO_IGNORE_BRANCH_ISA.
(fix_bad_cross_mode_branch_p): Return FALSE if
`mips_ignore_branch_isa' has been set.
(md_show_usage): Add `-mignore-branch-isa' and
`-mno-ignore-branch-isa'.
* doc/as.texinfo (Target MIPS options): Add
`-mignore-branch-isa' and `-mno-ignore-branch-isa' options.
(-mignore-branch-isa, -mno-ignore-branch-isa): New options.
* doc/c-mips.texi (MIPS Options): Add `-mignore-branch-isa' and
`-mno-ignore-branch-isa' options.
* testsuite/gas/mips/branch-local-ignore-2.d: New test.
* testsuite/gas/mips/branch-local-ignore-3.d: New test.
* testsuite/gas/mips/branch-local-ignore-n32-2.d: New test.
* testsuite/gas/mips/branch-local-ignore-n32-3.d: New test.
* testsuite/gas/mips/branch-local-ignore-n64-2.d: New test.
* testsuite/gas/mips/branch-local-ignore-n64-3.d: New test.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* emultempl/mipself.em (ignore_branch_isa): New variable.
(mips_create_output_section_statements): Rename
`_bfd_mips_elf_insn32' called to `_bfd_mips_elf_linker_flags',
add `ignore_branch_isa' argument.
(PARSE_AND_LIST_PROLOGUE): Add OPTION_IGNORE_BRANCH_ISA and
OPTION_NO_IGNORE_BRANCH_ISA enum values.
(PARSE_AND_LIST_LONGOPTS): Add "ignore-branch-isa" and
"no-ignore-branch-isa" options.
(PARSE_AND_LIST_OPTIONS): Add `--ignore-branch-isa' and
`--no-ignore-branch-isa'.
(PARSE_AND_LIST_ARGS_CASES): Handle OPTION_IGNORE_BRANCH_ISA and
OPTION_NO_IGNORE_BRANCH_ISA.
* ld.texinfo (Options specific to MIPS targets): Add
`--ignore-branch-isa' and `--no-ignore-branch-isa' options.
(ld and the MIPS family): Likewise.
* testsuite/ld-mips-elf/bal-jalx-pic-ignore.d: New test.
* testsuite/ld-mips-elf/bal-jalx-pic-ignore-n32.d: New test.
* testsuite/ld-mips-elf/bal-jalx-pic-ignore-n64.d: New test.
* testsuite/ld-mips-elf/unaligned-branch-ignore-2.d: New test.
* testsuite/ld-mips-elf/unaligned-branch-ignore-r6-1: New test.
* testsuite/ld-mips-elf/unaligned-branch-ignore-mips16: New
test.
* testsuite/ld-mips-elf/unaligned-branch-ignore-micromips: New
test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
gas/
* testsuite/gas/mips/branch-local-2.d: New test.
* testsuite/gas/mips/branch-local-3.d: New test.
* testsuite/gas/mips/branch-local-n32-2.d: New test.
* testsuite/gas/mips/branch-local-n32-3.d: New test.
* testsuite/gas/mips/branch-local-n64-2.d: New test.
* testsuite/gas/mips/branch-local-n64-3.d: New test.
* testsuite/gas/mips/mips.exp: Fold corresponding list tests
into the new tests.
PR 21056
opcodes * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
instructions when the previous fetch packet ends with a 32-bit
instruction.
gas * testsuite/gas/tic6x/insns16-parallel.s: New test case.
* testsuite/gas/tic6x/insns16-parallel.d: New test driver.
The use of te-linux.h is unnecessary since the TE_LINUX define is unused
and LOCAL_LABELS_FB is defined to 1 in tc-riscv.h as well.
gas/
* configure.tgt (riscv*-*-*): Remove em=linux.
Correct a regression from commit 8614eeee67 ("Traditional MIPS
patches"), <https://sourceware.org/ml/binutils/2000-07/msg00018.html>,
which caused symbols in linkonce or what is these days known as comdat
sections to be treated as external for the purpose of PIC relocation
generation even if their binding remains STB_LOCAL. This in turn
disabled GOT16/LO16 relocation pairing with references to such symbols,
as no complementing LO16 relocation is expected for external GOT16
references in the o32 ABI, which ultimately leads to link errors, e.g.:
ld: comdat-reloc.o: Can't find matching LO16 reloc against `foo' for R_MIPS_GOT16 at 0x24 in section `.text.bar[bar]'
as with the LD test case included with this change.
Revert the special case for symbols in comdat sections then, making code
actually match `adjust_reloc_syms' as indicated in its explanatory
comment, and adjust calling code accordingly. Also bring back the
corresponding description of what now is `s_is_linkonce', lost with
commit 5f0fe04bc5 ("Improved MIPS16/MIPS32 code intermixing for
gas."), <https://www.sourceware.org/ml/binutils/2006-07/msg00039.html>.
gas/
PR gas/20649
* config/tc-mips.c (pic_need_relax): Don't check for linkonce
symbols, remove the `segtype' parameter.
(mips_frob_file, md_estimate_size_before_relax): Adjust
accordingly.
(s_is_linkonce): Add an explanatory comment.
* testsuite/gas/mips/comdat-reloc.d: New test.
* testsuite/gas/mips/comdat-reloc.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
ld/
PR gas/20649
* testsuite/ld-mips-elf/mips-elf.exp: Add PIC comdat GOT16/LO16
relocation pairing link test.
Bit 24 of the indexed element vcmla decode mask was incorrectly
left unset. This could cause incorrect disassembly of some
currently undefined instructions as vcmla.
Rotatation immediates were not printed correctly in the disassembly
(could print 170 and 280 instead of 180 and 270).
opcodes/
* arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
gas/
* testsuite/gas/arm/armv8_3-a-simd.s: Add vcmla tests.
* testsuite/gas/arm/armv8_3-a-simd.d: Update.
PR 21059
binutils* arlex.l: Support processing with flex 2.6.3.
* deflex.l: Likewise.
gas * config/bfin-lex.l: Support processing with flex 2.6.3.
* itbl-lex.l: Likewise.
* read.c (temp_ilp): New function. Installs a temporary input
line pointer.
(restore_ilp): New function. Restores the original input line
pointer.
* read.h (temp_ilp): Prototype.
(restore_ilp): Prototype.
* stabs.c (dot_func_p): Use bfd_boolean type.
(generate_asm_file): Use temp_ilp and restore_ilp.
(stabs_generate_asm_lineno): Likewise.
(stabs_generate_asm_endfunc): Likewise.
bfd * config.bfd: Add entries for i686-redox and x86_64-redox.
gas * configure.tgt: Add entry for i386-redox.
ld * configure.tgt: Add entries for x86-redox and x86_64-redox.
gas/
* read.c (emit_leb128_expr): Extended unsigned big number for
sleb128.
* testsuite/gas/all/gas.exp (test_cond): Add sleb128-8 test.
* testsuite/gas/all/sleb128.d: New test.
* testsuite/gas/all/sleb128.s: New test source.
Previously, some pseudoinstructions like "call" only accepted
symbolic addresses and rejected constant addresses with an
esoteric internal error. This patch enables them by deferring
application of constant relocations to md_apply_fix, rather than
eagerly applying them during instruction assembly.
gas/ChangeLog
2017-01-09 Andrew Waterman <andrew@sifive.com>
* config/tc-riscv.c (append_insn): Don't eagerly apply relocations
against constants.
(md_apply_fix): Mark relocations against constants as "done."
TLS relocs against constants previously segfaulted, and illegal
symbol subtractions were silently ignored.
The previous behavior was to segfault.
gas/ChangeLog
2017-01-09 Andrew Waterman <andrew@sifive.com>
* config/tc-riscv.c (md_apply_fix): Report TLS relocations against
constants. Report disallowed symbol subtractions.
This was added so compressed loads could have smaller offsets for
accessing the data section, but the result was that writable sections
ended up in INITIAL_READONLY_SECTIONS. This is a bad idea. The fix is
to just remove this micro-optimization.
Thanks to Alan Morda for finding the problem!
ld/ChangeLog
2017-01-09 Palmer Dabbelt <palmer@dabbelt.com>
Kito Cheng <kito.cheng@gmail.com>
* emulparams/elf32lriscv-defs.sh (INITIAL_READONLY_SECTIONS):
Removed.
(SDATA_START_SYMBOLS): Likewise.
