2018-08-29 Kito Cheng <kito@andestech.com>
gas/
* config/tc-riscv.c (riscv_subset_supports): New argument:
xlen_required.
(riscv_multi_subset_supports): New function, able to check more
than one extension.
(riscv_ip): Use riscv_multi_subset_supports instead of
riscv_subset_supports.
(riscv_set_arch): Update call-site for riscv_subset_supports.
(riscv_after_parse_args): Likewise.
include/
*opcode/riscv.h (MAX_SUBSET_NUM): New.
(riscv_opcode): Add xlen_requirement field and change type of
subset.
opcodes/
* riscv-dis.c (riscv_disassemble_insn): Check XLEN by
riscv_opcode.xlen_requirement.
* riscv-opc.c (riscv_opcodes): Update for struct change.
Partial write %PSR (PWRPSR) is a SPARC V8e option that allows the WRPSR
instruction to only affect the %PSR.ET field. When available it is enabled
by setting the rd field of the WRPSR instruction to a value other than 0.
For Leon processors with support for partial write %PSR (currently GR740
and GR716) the rd value must be 1.
opcodes/ChangeLog:
2018-08-29 Martin Aberg <maberg@gaisler.com>
* sparc-opc.c (sparc_opcodes): Add Leon specific partial write
psr (PWRPSR) instruction.
gas/ChangeLog:
2018-08-29 Daniel Cederman <cederman@gaisler.com>
* testsuite/gas/sparc/leon.d: New test.
* testsuite/gas/sparc/leon.s: New test.
* testsuite/gas/sparc/sparc.exp: Execute the pwrpsr test.
Most optional operands to powerpc instructions use a default value of
zero, but there are a few exceptions. Those have been handled by
PPC_OPERAND_OPTIONAL_VALUE and an entry in the powerpc_operands table
for the default value, smuggled in the shift field. This patch
changes that to using the operand extract function to provide non-zero
defaults.
I've also moved the code determining whether optional operands are
provided or omitted, to the point the first optional operand is seen,
and allowed for the possibility of optional base register operands
in a future patch.
The patch does change the error you get on invalid assembly like
ld 3,4
You'll now see "missing operand" rather than
"syntax error; end of line, expected `('".
gas/
* config/tc-ppc.c (md_assemble): Delay counting of optional
operands until one is encountered. Allow for the possibility
of optional base regs, ie. PPC_OPERAND_PARENS. Call
ppc_optional_operand_value with extra args.
include/
* opcode/ppc.h (struct powerpc_operand): Correct "insert" comment.
Mention use of "extract" function to provide default value.
(PPC_OPERAND_OPTIONAL_VALUE): Delete.
(ppc_optional_operand_value): Rewrite to use extract function.
opcodes/
* ppc-dis.c (operand_value_powerpc): Init "invalid".
(skip_optional_operands): Count optional operands, and update
ppc_optional_operand_value call.
* ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
(extract_vlensi): Likewise.
(extract_fxm): Return default value for missing optional operand.
(extract_ls, extract_raq, extract_tbr): Likewise.
(insert_sxl, extract_sxl): New functions.
(insert_esync, extract_esync): Remove Power9 handling and simplify.
(powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
flag and extra entry.
(powerpc_operands <SXL>): Likewise, and use insert_sxl and
extract_sxl.
Bit manipulation instructions which are not normally generated by the
assembler, should nevertheless be decoded by the disassembler.
opcodes/
* s12z-dis.c: BM_RESERVED1 to behave like BM_OPR_REG, and
BM_RESERVED0 like BM_REG_IMM.
opcodes/
* s12z.h: Delete.
* s12z-dis.c: Adjust path of included file.
include/
* opcode/s12z.h: New file.
gas/
* config/tc-s12z.c: Adjust path of included file.
In 64-bit mode, display eiz for address with the addr32 prefix and without
base nor index registers. For
mov -0xccddef(,%eiz,), %rax
disassembler now displays:
67 48 8b 04 25 11 22 33 ff mov -0xccddef(,%eiz,1),%rax
instead of
67 48 8b 04 25 11 22 33 ff addr32 mov 0xffffffffff332211,%rax
gas/
* testsuite/gas/i386/evex-no-scale-64.d: Updated.
* testsuite/gas/i386/x86-64-addr32-intel.d: Likewise.
* testsuite/gas/i386/x86-64-addr32.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-addr32-intel.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-addr32.d: Likewise.
* testsuite/gas/i386/x86-64-addr32.s: Add %eiz tests.
opcodes/
* i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
address with the addr32 prefix and without base nor index
registers.
There are separate CPUID feature bits for fxsave/fxrstor and cmovCC
instructions. This patch adds CpuCMOV and CpuFXSR to replace Cpu686
on corresponding instructions.
gas/
* config/tc-i386.c (cpu_arch): Add .cmov and .fxsr.
(cpu_noarch): Add nocmov and nofxsr.
* doc/c-i386.texi: Document cmov and fxsr.
opcodes/
* i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
(cpu_flags): Add CpuCMOV and CpuFXSR.
* i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
There's no insn allowing ZEROING_MASKING alone. Re-purpose its value for
handling the not uncommon case of insns allowing either form of masking
with register operands, but only merging masking with a memory operand.
This patch series is a new binutils port for C-SKY processors, including support for both the V1 and V2 processor variants. V1 is derived from the MCore architecture while V2 is substantially different, with mixed 16- and 32-bit instructions, a larger register set, a different (but overlapping) ABI, etc. There is support for bare-metal ELF targets and Linux with both glibc and uClibc.
This code is being contributed jointly by C-SKY Microsystems and Mentor Graphics. C-SKY is responsible for the technical content and has proposed Lifang Xia and Yunhai Shang as port maintainers. (Note that C-SKY does have a corporate copyright assignment on file with the FSF.) Mentor Graphics' role has been cleaning up the code, adding documentation and additional test cases, etc, to address issues we anticipated reviewers would complain about.
bfd * Makefile.am (ALL_MACHINES, ALL_MACHINES_CFILES): Add C-SKY.
(BFD32_BACKENDS, BFD_BACKENDS_CFILES): Likewise.
* Makefile.in: Regenerated.
* archures.c (enum bfd_architecture): Add bfd_arch_csky and
related bfd_mach defines.
(bfd_csky_arch): Declare.
(bfd_archures_list): Add C-SKY.
* bfd-in.h (elf32_csky_build_stubs): Declare.
(elf32_csky_size_stubs): Declare.
(elf32_csky_next_input_section: Declare.
(elf32_csky_setup_section_lists): Declare.
* bfd-in2.h: Regenerated.
* config.bfd: Add C-SKY.
* configure.ac: Likewise.
* configure: Regenerated.
* cpu-csky.c: New file.
* elf-bfd.h (enum elf_target_id): Add C-SKY.
* elf32-csky.c: New file.
* libbfd.h: Regenerated.
* reloc.c: Add C-SKY relocations.
* targets.c (csky_elf32_be_vec, csky_elf32_le_vec): Declare.
(_bfd_target_vector): Add C-SKY target vector entries.
binutils* readelf.c: Include elf/csky.h.
(guess_is_rela): Handle EM_CSKY.
(dump_relocations): Likewise.
(get_machine_name): Likewise.
(is_32bit_abs_reloc): Likewise.
include * dis-asm.h (csky_symbol_is_valid): Declare.
* opcode/csky.h: New file.
opcodes * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
* Makefile.in: Regenerated.
* configure.ac: Add C-SKY.
* configure: Regenerated.
* csky-dis.c: New file.
* csky-opc.h: New file.
* disassemble.c (ARCH_csky): Define.
(disassembler, disassemble_init_for_target): Add case for ARCH_csky.
* disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
gas * Makefile.am (TARGET_CPU_CFILES): Add entry for C-SKY.
(TARGET_CPU_HFILES, TARGET_ENV_HFILES): Likewise.
* Makefile.in: Regenerated.
* config/tc-csky.c: New file.
* config/tc-csky.h: New file.
* config/te-csky_abiv1.h: New file.
* config/te-csky_abiv1_linux.h: New file.
* config/te-csky_abiv2.h: New file.
* config/te-csky_abiv2_linux.h: New file.
* configure.tgt: Add C-SKY.
* doc/Makefile.am (CPU_DOCS): Add entry for C-SKY.
* doc/Makefile.in: Regenerated.
* doc/all.texi: Set CSKY feature.
* doc/as.texi (Overview): Add C-SKY options.
(Machine Dependencies): Likewise.
* doc/c-csky.texi: New file.
* testsuite/gas/csky/*: New test cases.
ld * Makefile.am (ALL_EMULATION_SOURCES): Add C-SKY emulations.
(ecskyelf.c, ecskyelf_linux.c): New rules.
* Makefile.in: Regenerated.
* configure.tgt: Add C-SKY.
* emulparams/cskyelf.sh: New file.
* emulparams/cskyelf_linux.sh: New file.
* emultempl/cskyelf.em: New file.
* gen-doc.texi: Add C-SKY.
* ld.texi: Likewise.
(Options specific to C-SKY targets): New section.
* testsuite/ld-csky/*: New tests.
PowerPC has replaced use of "long" for insns with "int64_t", in
preparation for 64-bit power10 insns.
* ppc-opc.c (insert_sprbat): Correct function parameter and
return type.
(extract_sprbat): Likewise, variable too.
This is a relatively straightforward patch to improve support for the
IBM Gekko and IBM Broadway processors. Broadway is functionally
equivalent to the IBM 750CL, while Gekko's functionality is a subset
of theirs. The patch simplifies this reality and adds -mgekko and
-mbroadway as aliases for -m750cl. I didn't feel it was worth wasting
a PPC_OPCODE_* bit to differentiate Gekko. The patch adds a number of
simplified mnemonics for special purpose register access. Notably,
Broadway adds 4 additional IBAT and DBAT registers but these are not
assigned sequential SPR numbers.
gas/
* config/tc-ppc.c (md_show_usage): Add -mgekko and -mbroadway.
* doc/as.texi (Target PowerPC options): Add -mgekko and -mbroadway.
* doc/c-ppc.texi (PowerPC-Opts): Likewise.
* testsuite/gas/ppc/broadway.d,
* testsuite/gas/ppc/broadway.s: New test for broadway.
* testsuite/gas/ppc/ppc.exp: Run new test.
include/
* opcode/ppc.h (PPC_OPCODE_750): Adjust comment.
opcodes/
* ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
(powerpc_init_dialect): Handle bfd_mach_ppc_750.
* ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
support disjointed BAT.
(powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
(XSPRGQR_MASK, GEKKO, BROADWAY): Define.
(powerpc_opcodes): Add 750cl extended mnemonics for spr access.
Expand Broadcast to 3 bits so that the number of bytes to broadcast
can be computed as 1 << (Broadcast - 1). Use it to simplify x86
assembler.
gas/
* config/tc-i386.c (Broadcast_Operation): Add bytes.
(build_evex_prefix): Use i.broadcast->bytes.
(match_broadcast_size): New function.
(check_VecOperands): Use the broadcast field to compute the
number of bytes to broadcast directly. Set i.broadcast->bytes.
Use match_broadcast_size.
opcodes/
* i386-gen.c (adjust_broadcast_modifier): New function.
(process_i386_opcode_modifier): Add an argument for operands.
Adjust the Broadcast value based on operands.
(output_i386_opcode): Pass operand_types to
process_i386_opcode_modifier.
(process_i386_opcodes): Pass NULL as operands to
process_i386_opcode_modifier.
* i386-opc.h (BYTE_BROADCAST): New.
(WORD_BROADCAST): Likewise.
(DWORD_BROADCAST): Likewise.
(QWORD_BROADCAST): Likewise.
(i386_opcode_modifier): Expand broadcast to 3 bits.
* i386-tbl.h: Regenerated.
Just like for their AVX counterparts and CVTSI2S{D,S}, a memory source
here is ambiguous and hence
- in source files should be qualified with a suitable suffix or operand
size specifier (not doing so is an error in Intel mode, and will gain
a diagnostic in AT&T mode in the future),
- in disassembly should be properly suffixed (the Intel operand size
specifiers were emitted correctly already).
The MMI instruction set has been implemented in many Loongson
processors. There is a lot of software optimized for MMI. This patch
splits MMI from loongson2f/3a, and adds GAS and disassembler options for
MMI instructions.
2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
Maciej W. Rozycki <macro@mips.com>
bfd/
* elfxx-mips.c (print_mips_ases): Add MMI extension.
binutils/
* readelf.c (print_mips_ases): Add MMI extension.
gas/
* NEWS: Mention MultiMedia extensions Instructions (MMI)
support.
* config/tc-mips.c (options): Add OPTION_LOONGSON_MMI and
OPTION_NO_LOONGSON_MMI.
(md_longopts): Likewise.
(mips_ases): Define availability for MMI.
(mips_convert_ase_flags): Map ASE_LOONGSON_MMI to
AFL_ASE_LOONGSON_MMI.
(mips_cpu_info_table): Add ASE_LOONGSON_MMI for loongson2f/3a.
(md_show_usage): Add help for -mloongson-mmi and
-mno-loongson-mmi.
* doc/as.texi: Document -mloongson-mmi, -mno-loongson-mmi.
* doc/c-mips.texi: Document -mloongson-mmi, -mno-loongson-mmi,
.set loongson-mmi and .set noloongson-mmi.
* testsuite/gas/mips/loongson-2f.d: Move mmi test to ...
* testsuite/gas/mips/loongson-2f-mmi.d: Here. Add ISA/ASE
flag verification.
* testsuite/gas/mips/loongson-2f.s: Move mmi test to ...
* testsuite/gas/mips/loongson-2f-mmi.s: Here.
* testsuite/gas/mips/loongson-3a.d: Move mmi test to ...
* testsuite/gas/mips/loongson-3a-mmi.d: Here. Add ISA/ASE
flag verification.
* testsuite/gas/mips/loongson-3a.s: Move mmi test to ...
* testsuite/gas/mips/loongson-3a-mmi.s: Here.
* testsuite/gas/mips/mips.exp: Run loongson-2f-mmi and
loongson-3a-mmi tests.
include/
* elf/mips.h (AFL_ASE_MMI): New macro.
(AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_MMI.
* opcode/mips.h (ASE_LOONGSON_MMI): New macro.
opcodes/
* mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
loongson3a descriptors.
(parse_mips_ase_option): Handle -M loongson-mmi option.
(print_mips_disassembler_options): Document -M loongson-mmi.
* mips-opc.c (LMMI): New macro.
(mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
instructions.
The PPA instruction will be emitted by GCC transactional execution
builtins so it needs to be accepted with just -mhtm and without
-march=zEC12.
opcodes/ChangeLog:
2018-07-19 Andreas Krebbel <krebbel@linux.ibm.com>
* s390-opc.txt (PPA): Add the htm flag.
When multiple (here: two) forms of an insn take different width inputs
but produce identical size outputs (here: RegXMM), the templates can be
combined.
Also drop IgnoreSize (and the now redundant size specifiers) wherever
applicable.
These are special because they may not have a register operand to derive
the vector length from, which requires to also deal with the braodcast
case when determining vector length in build_evex_prefix().
Also drop IgnoreSize (and the now redundant size specifiers) from their
suffixed counterparts.
Instead of expanding macro-like constructs in i386-gen, have the C pre-
processor do this for us. Besides being a prerequisite for the next
template folding steps, this also paves the way for removing various
hidden dependencies between #define-s in i386-opc.h and plain literal
numbers used in i386-opc.tbl.
The #undef of None is solely to leave the generated i386-tbl.h entirely
unchanged.
After
commit 1b54b8d7e4
Author: Jan Beulich <jbeulich@novell.com>
Date: Mon Dec 18 09:36:14 2017 +0100
x86: fold RegXMM/RegYMM/RegZMM into RegSIMD
... qualified by their respective sizes, allowing to drop FirstXmm0 at
the same time.
folded RegXMM, RegYMM and RegZMM into RegSIMD, it's no longer impossible
to distinguish if Xmmword can represent a memory reference when operand
specification contains SIMD register. For example, template operands
specification like these
RegXMM|...|Xmmword|...
and
RegXMM|...
The Xmmword bitfield is always set by RegXMM which is represented by
"RegSIMD|Xmmword". This patch splits each of vcvtps2qq, vcvtps2uqq,
vcvttps2qq and vcvttps2uqq into 2 templates: one template only has
RegXMM source operand and the other only has mempry source operand.
gas/
PR gas/23418
* testsuite/gas/i386/xmmword.s: Add tests for vcvtps2qq,
vcvtps2uqq, vcvttps2qq and vcvttps2uqq.
* testsuite/gas/i386/xmmword.l: Updated.
opcodes/
PR gas/23418
* i386-opc.h (Byte): Update comments.
(Word): Likewise.
(Dword): Likewise.
(Fword): Likewise.
(Qword): Likewise.
(Tbyte): Likewise.
(Xmmword): Likewise.
(Ymmword): Likewise.
(Zmmword): Likewise.
* i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
vcvttps2uqq.
* i386-tbl.h: Regenerated.
For more details see: https://static.docs.arm.com/ddi0596/a/DDI_0596_ARM_a64_instruction_set_architecture.pdf
opcodes * aarch64-tbl.h (aarch64_opcode_table): Add entry for
ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
gas * testsuite/gas/aarch64/system.s: Add test for ssbb
and pssbb.
* testsuite/gas/aarch64/system.d: Update accordingly
and remove explicit addresses.
This adds the missing Em16 constraints the rest of the instructions requiring them
and also adds a testcase to test all the instructions so these are checked from
now on.
The Em16 operand constrains the valid registers to the lower 16 registers when used
with a half precision qualifier.
The list has been cross checked (by hand) through the Arm ARM version Ca.
opcodes/
PR binutils/23192
* aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
sqdmulh, sqrdmulh): Use Em16.
gas/
PR binutils/23192
* testsuite/gas/aarch64/illegal-by-element.s: New.
* testsuite/gas/aarch64/illegal-by-element.d: New.
* testsuite/gas/aarch64/illegal-by-element.l: New.
See:
https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability/download-the-whitepaper
opcodes * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
csdb together with them.
(thumb32_opcodes): Likewise.
gas * config/tc-arm.c (insns): Add new ssbb and pssbb instructions.
* testsuite/gas/arm/csdb.s: Add new tests for ssbb and pssbb.
* testsuite/gas/arm/csdb.d: Likewise
* testsuite/gas/arm/thumb2_it_bad.s: Likewise.
* testsuite/gas/arm/thumb2_it_bad.l: Likewise.
* testsuite/gas/arm/barrier.d: Update with ssbb.
* testsuite/gas/arm/barrier-thumb.d: Likewise.
Architecturally, MONITOR's and MONITORX'es memory operand is a 16- or
32-bit register outside of 64-bit mode, and a 64- or 32-bit register
inside 64-bit mode. The other register operands, including all of them
for MWAIT and MWAITX, are uniformly 32-bit, irrespective of mode. Retain
the original 64-bit MONITOR{,X} templates for compatibility only, and
fold the MWAIT{,X} ones.
