Commit Graph

9035 Commits

Author SHA1 Message Date
Srinath Parvathaneni
c4a23bf878 Add support for the MVE VMOV instruction to the ARM assembler. This instruction copies the value of one vector register to another vector register. The patch also modifies the decoding of VORR instruction which is effecting decoding of VMOV instruction.
gas     * config/tc-arm.c (parse_neon_mov): Add check to accept vector
	register to both the arguments in VMOV instruction.
	* testsuite/gas/arm/mve-vmov-1.d: Modify.
	* testsuite/gas/arm/mve-vmov-1.s: Likewise.
	* testsuite/gas/arm/mve-vorr.d: Likewise.

opcodes	* arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
	(is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
	(print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
2019-08-27 12:08:21 +01:00
Kito Cheng
db3b6ecc28 RISC-V: Improve li expansion for better code density.
li is a pseudo instruction in RISC-V, it might expand to more than one
instructions if the immediate value can't fit addi or lui, but the
assembler will always using 4-byte instructions during expansion.

For example:

 li a0, 0x12345001

will expand into

 12345537 lui a0,0x12345
 00150513 addi a0,a0,1

but addi could be compress into

 0505 addi a0,a0,1

It because load_const use macro_build to emit instructions,
and macro_build call append_insn, and expect it will compress
it if possible, but the fact is append_insn never compress anything,

So this patch redirect the li expansion flow to normal instruction
emission flow via md_assemble, added md_assemblef as an wrapper for
that for easier emit instruction with printf-style argument to build
instruction.

gas/ChangeLog:

	* tc-riscv.c (md_assemblef): New.
	(load_const) Use md_assemblef instead of macro_build to emit
	instructions.
	* testsuite/gas/riscv/li32.d: New.
	* testsuite/gas/riscv/li32.s: Ditto.
	* testsuite/gas/riscv/li64.d: Ditto.
	* testsuite/gas/riscv/li64.s: Ditto.
2019-08-25 19:16:43 -07:00
Nick Clifton
fe4b77d9e5 Updated Swedish translation for the gas sub-directory.
2019-08-23  Nick Clifton  <nickc@redhat.com>

	* po/sv.po: Updated Swedish translation.
2019-08-23 10:46:46 +01:00
Dennis Zhang
0535e5d74d Arm: Add support for missing CPUs
This patch adds support for following CPUs:
Cortex-M35P, Cortex-A77, Cortex-A76AE.

Related specifications can be found at https://developer.arm.com/ip-products/processors.

gas/ChangeLog:

	* config/tc-arm.c: New entries for Cortex-M35P, Cortex-A77,
	and Cortex-A76AE.
	* doc/c-arm.texi: Document new processors.
	* testsuite/gas/arm/cpu-cortex-a76ae.d: New test.
	* testsuite/gas/arm/cpu-cortex-a77.d: New test.
	* testsuite/gas/arm/cpu-cortex-m35p.d: New test.

bfd/ChangeLog:

	* cpu-arm.c: New entries for Cortex-M35P, Cortex-A77, Cortex-A76AE.
2019-08-22 15:35:43 +01:00
Bosco Garc?a
a3197745b1 Fix the assembler's floating point number parser so that it can correctly handle numbers encoded as a leading decimal point, followed by zeroes, followed by a non-zero sequence.
* atof-generic.c (atof_generic): Do not ignore leading zeros if
	they appear after a decimal point.
	* testsuite/gas/all/float.s: Extend test to include a number with
	a leading decimal point followed by several zeroes.
	* testsuite/gas/i386/fp.s: Likewise.
	* testsuite/gas/i386/fp.d: Update expected output.
2019-08-22 12:54:06 +01:00
Barnaby Wilks
b20d385926 Implement a float16 directive for assembling 16 bit IEEE 754 floating point numbers for the AArch64 assembler.
The syntax of the directive is:

     .float16 <0-n decimal numbers>
e.g.
     .float16 0.5
     .float16 10.2, NaN, 452.09

The floats will always be encoded using the binary16 format as described in the
IEEE 754-2008 standard. There is no need to support Arm's alternative half-precision
format since AArch64 only supports the IEEE format.

gas	* config/tc-aarch64.c: Add float16 directive and add "Hh" to
	acceptable float characters.
	* doc/c-aarch64.texi: Documentation for float16 directive.
	* testsuite/gas/aarch64/float16-be.d: New test.
	* testsuite/gas/aarch64/float16-le.d: New test.
	* testsuite/gas/aarch64/float16.s: New test.
	* NEWS: Add NEWS entry.
2019-08-22 11:13:23 +01:00
Kyrylo Tkachov
a051e2f3e0 [AArch64][gas] Update MTE system register encodings
The MTE specification adjusted the encoding of the TFSRE0_EL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12 system registers.
This patch brings binutils up to date.

The references for the encodings are at:
https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsre0_el1 (also contains TFSR_EL12 description)
https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsr_el1
https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsr_el2
https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsr_el3

Tested check-gas for aarch64-none-elf.

opcodes/

	* aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
	tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
	(aarch64_sys_reg_supported_p): Update checks for the above.

gas/

    * testsuite/gas/aarch64/sysreg-4.d: Update expected disassembly for
    tfsre0_el1, tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12 system registers.
2019-08-22 10:20:01 +01:00
Nick Clifton
722a298cca Remove test files for a different patch accidentally committed with patch for ARM CPU additions. 2019-08-20 17:33:44 +01:00
Dennis Zhang
546053acfa Adds support for following CPUs to the ARM and Aarch64 assemblers: Cortex-A77, Cortex-A76AE, Cortex-A34, Cortex-A65, and Cortex-A65AE.
Related specifications can be found at
https://developer.arm.com/ip-products/processors.

gas	* NEWS: Mention the Arm and AArch64 new processors.
	* config/tc-aarch64.c: New entries for Cortex-A34, Cortex-A65,
	Cortex-A77, cortex-A65AE, and Cortex-A76AE.
	* doc/c-aarch64.texi: Document new CPUs.
	* testsuite/gas/aarch64/cpu-cortex-a34.d: New test.
	* testsuite/gas/aarch64/cpu-cortex-a65.d: New test.
	* testsuite/gas/aarch64/cpu-cortex-a65ae.d: New test.
	* testsuite/gas/aarch64/cpu-cortex-a76ae.d: New test.
	* testsuite/gas/aarch64/cpu-cortex-a77.d: New test.
	* testsuite/gas/aarch64/nop-asm.s: New test.

bfd	* cpu-aarch64.c: New entries for Cortex-A34, Cortex-A65,
	 Cortex-A77, cortex-A65AE, and Cortex-A76AE.
2019-08-20 17:13:29 +01:00
Faraz Shahbazker
5203173819 MIPS/gas: Fix misaligned address errors to disregard ISA mode bit
gas/
	* config/tc-mips.c (fix_bad_misaligned_address): New function.
	(fix_validate_branch): Call fix_bad_misaligned address_to
	calculate the target address.
	(md_apply_fix): Likewise.
	(md_convert_frag): Update misaligned address calculation to
	disregard ISA mode bit.
2019-08-19 13:43:51 -07:00
Faraz Shahbazker
770c015139 MIPS/gas: Retain ISA mode bit for labels with .insn annotation
gas/
	* config/tc-mips.c (mips_move_labels): Retain ISA mode bit
	when moving labels in text segments.
	(mips_align): Indicate text mode when aligning labels in
	text segments.
	* gas/testsuite/gas/mips/insn-isa-mode.d: New test.
	* gas/testsuite/gas/mips/insn-isa-mode.s: New test source.
	* gas/testsuite/gas/mips/mips.exp: Run the new test.
2019-08-19 13:43:50 -07:00
Barnaby Wilks
72c03e30ae Float16: Fix test failures for non ELF targets
The tests were failing due to md_atof trying to do word-wise endian
switching on the float16 (for little-endian targets sometimes
multi word values have their word order changed).
However since a float16 is only 1 word wide, it would end up writing
incorrect data, as you cannot switch the word order of just one word.

	* config/tc-arm.c (md_atof): Add precision check.  Formatting.
2019-08-19 09:53:22 +09:30
Nick Clifton
6485977b89 Updatesd Swdish translation for the gas sub-directory.
* po/sv.po: Updated Swedish translation.
2019-08-15 12:41:24 +01:00
Srinath Parvathaneni
08132bdd87 Modify the ARM encoding and decoding of SQRSHRL and UQRSHLL MVE instructions.
This is a change to the first published specifications [1][a] but since there is no hardware
out there that uses the old instructions we do not want to support the old variant.
This changes are done based on the latest published specifications [1][b].

[1] https://developer.arm.com/architectures/cpu-architecture/m-profile/docs/ddi0553/latest/armv81-m-architecture-reference-manual
    [a] version bf
    [b] version bh

gas	* config/tc-arm.c (enum operand_parse_code): Add the entry OP_I48_I64.
	(po_imm1_or_imm2_or_fail): Marco to check the immediate is either of
        48 or 64.
	(parse_operands): Add case OP_I48_I64.
	(do_mve_scalar_shift1): Add function to encode the MVE shift
        instructions with 4 arguments.
	* testsuite/gas/arm/mve-shift-bad.l: Modify.
	* testsuite/gas/arm/mve-shift-bad.s: Likewise.
	* testsuite/gas/arm/mve-shift.d: Likewise.
	* testsuite/gas/arm/mve-shift.s: Likewise.

opcodes	* arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
	cases MVE_SQRSHRL and MVE_UQRSHLL.
	(print_insn_mve): Add case for specifier 'k' to check
	specific bit of the instruction.
2019-08-12 17:17:18 +01:00
Barnaby Wilks
5312fe52e9 Add generic and ARM specific support for half-precision IEEE 754 floating point numbers to the assembler.
Half precision floating point numbers will be encoded using the IEEE 754
half precision floating point format - 16 bits in total, 1 for sign, 5
for exponent and 10 bits of  mantissa.

This patch implements the float16 directive for both the IEEE 754 format
and the Arm alternative format for the Arm backend.

The syntax of the directive is:

  .float16 <0-n decimal numbers>
e.g.
  .float16 12.0
  .float16 0.23, 433.1, 0.06

The Arm alternative format is almost identical to the IEEE 754 format,
except that it doesn't encode for NaNs or Infinity (instead an exponent
of 0x1F represents a normalized number in the range 65536 to 131008).

The alternative format is documented in the reference manual:

  https://static.docs.arm.com/ddi0487/db/DDI0487D_b_armv8_arm.pdf?_ga=2.72318806.49764181.1561632697-999473562.1560847439

Which format is used is controlled by the .float16_format <format>
directive, where if <format> = ieee, then use the IEEE 754
half-precision format else if <format> = alternative, then use the
Arm alternative format

Or the format can be set on the command line via the -mfp16-format
option that has a similar syntax.  -mfp16-format=<ieee|alternative>.
This also fixes the format and it cannot be changed by any directives.

Once the format has been set (either by the command line option or a directive) it cannot be changed,
and any attempts to change it (i.e. with the float16_format directive) will result in a warning and the
line being ignored.

For ELF targets the appropriate EABI attribute will be written out at the end of assembling
if the format has been explicitly specified. If no format has been explicitly specified then no
EABI attributes will be written.

If the format is not explicitly specified then any float16 directives are encoding using the IEEE 754-2008
format by default until the format is fixed or changed with the float16_format directive.

gas	* config/tc-arm.c (enum fp_16bit_format): Add enum to represent the 2 float16 encodings.
	(md_atof): Set precision for float16 type.
	(arm_is_largest_exponent_ok): Check for whether to encode with the IEEE or alternative
	format.
	(set_fp16_format): Parse a float16_format directive.
	(arm_parse_fp16_opt): Parse the fp16-format command line option.
	(aeabi_set_public_attributes): For ELF encode the FP16 format EABI attribute.
	* config/tc-arm.h (TC_LARGEST_EXPONENT_IS_NORMAL): Macro that expands to
	arm_is_largest_exponent_ok.
	(arm_is_largest_exponent_ok): Add prototype for arm_is_largest_exponent_ok function.
	* doc/c-arm.texi: Add documentation for .float16, .float16_format and -mfp16-format=
	* testsuite/gas/arm/float16-bad.d: New test.
	* testsuite/gas/arm/float16-bad.l: New test.
	* testsuite/gas/arm/float16-bad.s: New test.
	* testsuite/gas/arm/float16-be.d: New test.
	* testsuite/gas/arm/float16-format-bad.d: New test.
	* testsuite/gas/arm/float16-format-bad.l: New test.
	* testsuite/gas/arm/float16-format-bad.s: New test.
	* testsuite/gas/arm/float16-format-opt-bad.d: New test.
	* testsuite/gas/arm/float16-format-opt-bad.l: New test.
	* testsuite/gas/arm/float16-le.d: New test.
	* testsuite/gas/arm/float16.s: New test.
	* testsuite/gas/arm/float16-eabi-alternative-format.d: New test.
	* testsuite/gas/arm/float16-eabi-ieee-format.d: New test.
	* testsuite/gas/arm/float16-eabi-no-format.d: New test.
	* testsuite/gas/arm/float16-eabi.s: New test.

	* config/atof-ieee.c (H_PRECISION): Macro for precision of float16
	type.
	(atof_ieee): Set precision and exponent bits for encoding float16
	types.
	(gen_to_words): NaN and Infinity encoding for float16.
	(ieee_md_atof): Set precision for encoding float16 type.
2019-08-12 11:08:36 +01:00
Alan Modra
9bb9c115cd PR24851, gas/testsuite/gas/epiphany/badrelax.s failure with MALLOC_PERTURB_=1
PR 24851
	* config/tc-epiphany.c (md_estimate_size_before_relax): Clear
	extra opcode bytes when changing from a 2-byte to a 4-byte insn.
2019-08-12 13:10:48 +09:30
Jan Beulich
678581fc78 x86-64: generalize SIMD test expectations
In order to be able to add/remove insns to/from the middle of these
tests, generalize the patterns for the symbol reference comments of RIP-
relative operands.
2019-08-09 09:57:57 +02:00
Nick Clifton
dbe15e4e1d Change the output of readelf's note display so that the "Data size" column header is left justified.
PR 24887
binutils* readelf.c (process_notes_at): Left justify the "Data size"
	column heading.
	* testsuite/binutils-all/i386/empty.d: Adjust for new output format.
	* testsuite/binutils-all/i386/ibt.d: Likewise.
	* testsuite/binutils-all/i386/pr21231a.d: Likewise.
	* testsuite/binutils-all/i386/pr21231b.d: Likewise.
	* testsuite/binutils-all/i386/shstk.d: Likewise.
	* testsuite/binutils-all/note-2-32.d: Likewise.
	* testsuite/binutils-all/note-2-64.d: Likewise.
	* testsuite/binutils-all/x86-64/empty-x32.d: Likewise.
	* testsuite/binutils-all/x86-64/empty.d: Likewise.
	* testsuite/binutils-all/x86-64/ibt-x32.d: Likewise.
	* testsuite/binutils-all/x86-64/ibt.d: Likewise.
	* testsuite/binutils-all/x86-64/pr21231a.d: Likewise.
	* testsuite/binutils-all/x86-64/pr21231b.d: Likewise.
	* testsuite/binutils-all/x86-64/pr23494a-x32.d: Likewise.
	* testsuite/binutils-all/x86-64/pr23494a.d: Likewise.
	* testsuite/binutils-all/x86-64/pr23494c-x32.d: Likewise.
	* testsuite/binutils-all/x86-64/pr23494c.d: Likewise.
	* testsuite/binutils-all/x86-64/pr23494d-x32.d: Likewise.
	* testsuite/binutils-all/x86-64/pr23494d.d: Likewise.
	* testsuite/binutils-all/x86-64/pr23494e-x32.d: Likewise.
	* testsuite/binutils-all/x86-64/pr23494e.d: Likewise.
	* testsuite/binutils-all/x86-64/shstk-x32.d: Likewise.
	* testsuite/binutils-all/x86-64/shstk.d: Likewise.

ld	* testsuite/ld-aarch64/bti-plt-2.d: Adjust for new output format
	from readelf.
	* testsuite/ld-aarch64/bti-plt-4.d: Likewise.
	* testsuite/ld-aarch64/bti-plt-6.d: Likewise.
	* testsuite/ld-aarch64/bti-plt-7.d: Likewise.
	* testsuite/ld-aarch64/bti-warn.d: Likewise.
	* testsuite/ld-aarch64/property-bti-pac1.d: Likewise.
	* testsuite/ld-aarch64/property-bti-pac2.d: Likewise.
	* testsuite/ld-aarch64/property-bti-pac3.d: Likewise.
	* testsuite/ld-elf/x86-feature-1a.rd: Likewise.
	* testsuite/ld-elf/x86-feature-1b.rd: Likewise.
	* testsuite/ld-elf/x86-feature-1c.rd: Likewise.
	* testsuite/ld-elf/x86-feature-1d.rd: Likewise.
	* testsuite/ld-elf/x86-feature-1e.rd: Likewise.
	* testsuite/ld-i386/ibt-plt-2d.d: Likewise.
	* testsuite/ld-i386/ibt-plt-3d.d: Likewise.
	* testsuite/ld-i386/pr23372a.d: Likewise.
	* testsuite/ld-i386/pr23372c.d: Likewise.
	* testsuite/ld-i386/pr23486a.d: Likewise.
	* testsuite/ld-i386/pr23486b.d: Likewise.
	* testsuite/ld-i386/pr23486c.d: Likewise.
	* testsuite/ld-i386/pr23486d.d: Likewise.
	* testsuite/ld-i386/pr24322a.d: Likewise.
	* testsuite/ld-i386/pr24322b.d: Likewise.
	* testsuite/ld-i386/property-x86-3.d: Likewise.
	* testsuite/ld-i386/property-x86-4a.d: Likewise.
	* testsuite/ld-i386/property-x86-5.d: Likewise.
	* testsuite/ld-i386/property-x86-cet1.d: Likewise.
	* testsuite/ld-i386/property-x86-cet2a.d: Likewise.
	* testsuite/ld-i386/property-x86-cet5a.d: Likewise.
	* testsuite/ld-i386/property-x86-cet5b.d: Likewise.
	* testsuite/ld-i386/property-x86-ibt1a.d: Likewise.
	* testsuite/ld-i386/property-x86-ibt1b.d: Likewise.
	* testsuite/ld-i386/property-x86-ibt2.d: Likewise.
	* testsuite/ld-i386/property-x86-ibt3a.d: Likewise.
	* testsuite/ld-i386/property-x86-ibt3b.d: Likewise.
	* testsuite/ld-i386/property-x86-ibt4.d: Likewise.
	* testsuite/ld-i386/property-x86-ibt5.d: Likewise.
	* testsuite/ld-i386/property-x86-shstk1a.d: Likewise.
	* testsuite/ld-i386/property-x86-shstk1b.d: Likewise.
	* testsuite/ld-i386/property-x86-shstk2.d: Likewise.
	* testsuite/ld-i386/property-x86-shstk3a.d: Likewise.
	* testsuite/ld-i386/property-x86-shstk3b.d: Likewise.
	* testsuite/ld-i386/property-x86-shstk4.d: Likewise.
	* testsuite/ld-i386/property-x86-shstk5.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-2d-x32.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-2d.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-3d-x32.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-3d.d: Likewise.
	* testsuite/ld-x86-64/pr23372a-x32.d: Likewise.
	* testsuite/ld-x86-64/pr23372a.d: Likewise.
	* testsuite/ld-x86-64/pr23372c-x32.d: Likewise.
	* testsuite/ld-x86-64/pr23372c.d: Likewise.
	* testsuite/ld-x86-64/pr23486a-x32.d: Likewise.
	* testsuite/ld-x86-64/pr23486a.d: Likewise.
	* testsuite/ld-x86-64/pr23486b-x32.d: Likewise.
	* testsuite/ld-x86-64/pr23486b.d: Likewise.
	* testsuite/ld-x86-64/pr23486c-x32.d: Likewise.
	* testsuite/ld-x86-64/pr23486c.d: Likewise.
	* testsuite/ld-x86-64/pr23486d-x32.d: Likewise.
	* testsuite/ld-x86-64/pr23486d.d: Likewise.
	* testsuite/ld-x86-64/pr24322a-x32.d: Likewise.
	* testsuite/ld-x86-64/pr24322a.d: Likewise.
	* testsuite/ld-x86-64/pr24322b-x32.d: Likewise.
	* testsuite/ld-x86-64/pr24322b.d: Likewise.
	* testsuite/ld-x86-64/pr24458a-x32.d: Likewise.
	* testsuite/ld-x86-64/pr24458a.d: Likewise.
	* testsuite/ld-x86-64/pr24458b-x32.d: Likewise.
	* testsuite/ld-x86-64/pr24458b.d: Likewise.
	* testsuite/ld-x86-64/pr24458c-x32.d: Likewise.
	* testsuite/ld-x86-64/pr24458c.d: Likewise.
	* testsuite/ld-x86-64/property-1.r: Likewise.
	* testsuite/ld-x86-64/property-1a.r: Likewise.
	* testsuite/ld-x86-64/property-2.r: Likewise.
	* testsuite/ld-x86-64/property-2a.r: Likewise.
	* testsuite/ld-x86-64/property-3.r: Likewise.
	* testsuite/ld-x86-64/property-3a.r: Likewise.
	* testsuite/ld-x86-64/property-4.r: Likewise.
	* testsuite/ld-x86-64/property-4a.r: Likewise.
	* testsuite/ld-x86-64/property-5.r: Likewise.
	* testsuite/ld-x86-64/property-5a.r: Likewise.
	* testsuite/ld-x86-64/property-6.r: Likewise.
	* testsuite/ld-x86-64/property-7.r: Likewise.
	* testsuite/ld-x86-64/property-7a.r: Likewise.
	* testsuite/ld-x86-64/property-x86-3-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-3.d: Likewise.
	* testsuite/ld-x86-64/property-x86-4a-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-4a.d: Likewise.
	* testsuite/ld-x86-64/property-x86-5-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-5.d: Likewise.
	* testsuite/ld-x86-64/property-x86-cet1-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-cet1.d: Likewise.
	* testsuite/ld-x86-64/property-x86-cet2a-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-cet2a.d: Likewise.
	* testsuite/ld-x86-64/property-x86-cet5a-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-cet5a.d: Likewise.
	* testsuite/ld-x86-64/property-x86-cet5b-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-cet5b.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt1a-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt1a.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt1b-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt1b.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt2-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt2.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt3a-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt3a.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt3b-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt3b.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt4-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt4.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt5-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt5.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk1a-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk1a.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk1b-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk1b.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk2-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk2.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk3a-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk3a.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk3b-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk3b.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk4-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk4.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk5-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk5.d: Likewise.

gas	* testsuite/gas/i386/property-1.d: Adjust for new output format
	from readelf.
	* testsuite/gas/i386/property-2.d: Likewise.
	* testsuite/gas/i386/x86-64-property-1.d: Likewise.
	* testsuite/gas/i386/x86-64-property-2.d: Likewise.
2019-08-08 17:04:31 +01:00
Yoshinori Sato
7b1dd70105 Update the handling of shift rotate and load/store multiple instructions in the H8300 assembler.
incldue	* opcode/h8300.h (EXPAND_UNOP_EXTENDED_B): Add MODEL.
	(EXPAND_UNOP_EXTENDED_W): Likewise.
	(EXPAND_UNOP_EXTENDED_L): Likewise.
	(struct h8_opcode h8_opcodes): Likewise.
	(struct h8_opcode h8_opcodes): tas / ldm / stm supported H8S or
	later.
2019-08-08 13:59:17 +01:00
Yoshinori Sato
8fb49c3c71 Move the h8300 assembler's MOVFPE and MOVTPE tests to the correct location.
* gas/testsuite/gas/h8300/h8300.exp: Fix movfpe and movtpe tests.
	* gas/testsuite/gas/h8300/misc.s: Likewise.
	* gas/testsuite/gas/h8300/misch.s: Likewise.
	* gas/testsuite/gas/h8300/miscs.s: Likewise.
2019-08-08 13:43:13 +01:00
Barnaby Wilks
23d188c74e Removes support in the ARM assembler for the unsigned variants of the VQ(R)DMLAH and VQ(R)DMLASH MVE instructions.
Previously GAS would accept .u32, .u16 and .u8 suffixes to the VQ(R)DMLAH and VQ(R)DMLASH
instructions, however the Armv8.1-M Mainline specification states that these functions only
have signed variations (.s32, .s16 and .s8 suffixes).
This is documented here:
https://static.docs.arm.com/ddi0553/bh/DDI0553B_h_armv8m_arm.pdf?_ga=2.143079093.1892401233.1563295591-999473562.1560847439#page=1183

gas	* config/tc-arm.c (do_mve_vqdmlah): Use N_S_32 macro.
	(do_neon_qrdmlah): Use N_S_32 macro.
	* testsuite/gas/arm/mve-vqdmlah-bad.d: New test.
	* testsuite/gas/arm/mve-vqdmlah-bad.l: New test.
	* testsuite/gas/arm/mve-vqdmlah-bad.s: New test.
	* testsuite/gas/arm/mve-vqdmlah.d: Remove unsigned instruction tests.
	* testsuite/gas/arm/mve-vqdmlah.s: Remove unsigned instruction tests.
	* testsuite/gas/arm/mve-vqdmlash-bad.d: New test.
	* testsuite/gas/arm/mve-vqdmlash-bad.l: New test.
	* testsuite/gas/arm/mve-vqdmlash-bad.s: New test.
	* testsuite/gas/arm/mve-vqdmlash.d: Remove unsigned instruction tests.
	* testsuite/gas/arm/mve-vqdmlash.s: Remove unsigned instruction tests.

opcodes	* arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
	instructions.
2019-08-05 12:43:38 +01:00
Jim Wilson
c0d6f62fce RISC-V: Fix minor issues with FP csr instructions.
Mel Chen <mel.chen@sifive.com>
	gas/
	* testsuite/gas/riscv/alias-csr.s: Add testcase for CSR-access
	alias instructions.
	* testsuite/gas/riscv/no-aliases-csr.d: Run testcase alias-csr.s with
	-Mno-aliases.
	* testsuite/gas/riscv/alias-csr.d: Run testcase alias-csr.s.
	* testsuite/gas/riscv/priv-reg.d: Update.
	opcodes/
	* riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
	fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
	* riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
	fscsr.
2019-07-30 14:42:16 -07:00
Nick Clifton
dac6552d4a Update the Swedish translation for the gas sub-directory. 2019-07-24 15:21:24 +01:00
Claudiu Zissulescu
0f3f71676a [ARC] Update disassembler opcode selection
New instruction are added, and some of them are overlapping. Update
disassembler to correctly recognize them. Introduce nps400 option.

opcodes/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
	and MPY class instructions.
	(parse_option): Add nps400 option.
	(print_arc_disassembler_options): Add nps400 info.

gas/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* testsuite/gas/arc/nps400-6.d: Update test.
2019-07-24 16:52:23 +03:00
Alan Modra
cc364be6ff Complain about mbind, ifunc, and unique in final_write
It's not as good as complaining in gas/config/obj-elf.c since you lose
any reference to the source file.

bfd/
	* elf-bfd.h (struct elf_backend_data): Return bfd_boolean from
	elf_backend_final_write_processing, don't pass linker arg.
	(_bfd_elf_final_write_processing): Update prototype.
	* elf.c (_bfd_elf_write_object_contents): Adjust call.
	(_bfd_elf_final_write_processing): Return error on incompatible
	OSABI and has_gnu_osabi.  Remove linker arg.
	* elf-nacl.h (nacl_final_write_processing): Update prototype.
	* elf-vxworks.h (elf_vxworks_final_write_processing): Likewise.
	* elfxx-mips.h (_bfd_mips_final_write_processing): Likewise.
	(_bfd_mips_elf_final_write_processing): Likewise.
	* elf-hppa.h (elf_hppa_final_write_processing): Return status
	and remove linker arg.
	* elf-m10300.c (_bfd_mn10300_elf_final_write_processing): Likewise.
	* elf-nacl.c (nacl_final_write_processing): Likewise.
	* elf-vxworks.c (elf_vxworks_final_write_processing): Likewise.
	* elf32-arc.c (arc_elf_final_write_processing): Likewise.
	* elf32-arm.c (arm_final_write_processing): Likewise.
	(elf32_arm_final_write_processing): Likewise.
	(elf32_arm_nacl_final_write_processing): Likewise.
	(elf32_arm_vxworks_final_write_processing): Likewise.
	* elf32-avr.c (bfd_elf_avr_final_write_processing): Likewise.
	* elf32-bfin.c (elf32_bfin_final_write_processing): Likewise.
	* elf32-cr16.c (_bfd_cr16_elf_final_write_processing): Likewise.
	* elf32-cris.c (cris_elf_final_write_processing): Likewise.
	* elf32-h8300.c (elf32_h8_final_write_processing): Likewise.
	* elf32-lm32.c (lm32_elf_final_write_processing): Likewise.
	* elf32-m32r.c (m32r_elf_final_write_processing): Likewise.
	* elf32-m68k.c (elf_m68k_final_write_processing): Likewise.
	* elf32-mips.c (mips_vxworks_final_write_processing): Likewise.
	* elf32-msp430.c (bfd_elf_msp430_final_write_processing): Likewise.
	* elf32-nds32.c (nds32_elf_final_write_processing): Likewise.
	* elf32-or1k.c (or1k_elf_final_write_processing): Likewise.
	* elf32-pj.c (pj_elf_final_write_processing): Likewise.
	* elf32-ppc.c (ppc_final_write_processing): Likewise.
	(ppc_elf_final_write_processing): Likewise.
	(ppc_elf_vxworks_final_write_processing): Likewise.
	* elf32-sparc.c (sparc_final_write_processing): Likewise.
	(elf32_sparc_final_write_processing): Likewise.
	(elf32_sparc_vxworks_final_write_processing): Likewise.
	* elf32-v850.c (v850_elf_final_write_processing): Likewise.
	* elf32-xc16x.c (elf32_xc16x_final_write_processing): Likewise.
	* elf32-xtensa.c (elf_xtensa_final_write_processing): Likewise.
	* elf64-ia64-vms.c (elf64_vms_final_write_processing): Likewise.
	* elfnn-ia64.c (elfNN_ia64_final_write_processing): Likewise.
	* elfxx-mips.c (_bfd_mips_final_write_processing): Likewise.
	(_bfd_mips_elf_final_write_processing): Likewise.
gas/
	* config/obj-elf.c (obj_elf_section, obj_elf_type): Set has_gnu_osabi.
	* testsuite/gas/elf/section12a.d: Update xfails.
	* testsuite/gas/elf/section12b.d: Likewise.
2019-07-24 16:12:02 +09:30
Alan Modra
7613ca5e38 Define ELF_OSABI for visium
and update expected results for gas mbind tests.

bfd/
	* elf32-visium.c (visium_elf_post_process_headers): Don't set
	EI_OSABI header byte here.
	(ELF_OSABI): Define.
gas/
	* testsuite/gas/elf/section12a.d: xfail visium and cloudabi.
	* testsuite/gas/elf/section12b.d: Likewise.
	* testsuite/gas/elf/section13.d: Likewise.
2019-07-24 16:12:01 +09:30
Kyrylo Tkachov
a028026d2f [AArch64] Add support for GMID_EL1 register for +memtag
We're missing support for the GMID_EL1 system register from the Memory Tagging Extension in binutils.
This is specified at:
https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/gmid_el1

This simple patch adds the support for this read-only register.
Tested make check on gas.
2019-07-23 15:54:54 +01:00
Alan Modra
df3a023bd6 SHF_GNU_MBIND requires ELFOSABI_GNU
When SHF_GNU_MBIND was added in the SHF_LOOS to SHF_HIOS range, it
should have required ELFOSABI_GNU since these flags are already in use
by other OSes.  HPUX SHF_HP_TLS in fact has the same value.  That
means no place in binutils should test SHF_GNU_MBIND without first
checking OSABI, and SHF_GNU_MBIND should not be set without also
setting OSABI.  At least, that's the ideal, but the patch accepts
SHF_GNU_MBIND on ELFOSABI_NONE object files since gas didn't always
set OSABI.  However, to reinforce the fact that SHF_GNU_MBIND isn't
proper without a non-zero OSABI, readelf will display the flag as
LOOS+0 if OSABI isn't set.

The clash with SHF_HP_TLS means that hppa64-linux either has that flag
on .tbss sections or supports GNU_MBIND, not both.  (hppa64-linux
users, if there are any, may have noticed that GNU ld since 2017
mysteriously aligned their .tbss sections to a 4k boundary.  That was
one consequence of SHF_HP_TLS being blindly interpreted as
SHF_GNU_MBIND.)  Since it seems that binutils, gdb, gcc, glibc, and
the linux kernel don't care about SHF_HP_TLS I took that flag out of
.tbss for hppa64-linux.

bfd/
	* elf-bfd.h (enum elf_gnu_osabi): Add elf_gnu_osabi_mbind.
	* elf.c (_bfd_elf_make_section_from_shdr): Set elf_gnu_osabi_mbind.
	(get_program_header_size): Formatting.  Only test SH_GNU_MBIND
	when elf_gnu_osabi_mbind is set.
	(_bfd_elf_map_sections_to_segments): Likewise.
	(_bfd_elf_init_private_section_data): Likewise.
	(_bfd_elf_final_write_processing): Update comment.
	* elf64-hppa.c (elf64_hppa_special_sections): Move .tbss entry.
	(elf_backend_special_sections): Define without .tbss for linux.
binutils/
	* readelf.c (get_parisc_segment_type): Split off hpux entries..
	(get_ia64_segment_type): ..and these..
	(get_hpux_segment_type): ..to here.
	(get_segment_type): Condition GNU_MBIND on osabi.  Use
	get_hpux_segment_type.
	(get_symbol_binding): Do not print UNIQUE for ELFOSABI_NONE.
	(get_symbol_type): Do not print IFUNC for ELFOSABI_NONE.
gas/
	* config/obj-elf.c (obj_elf_change_section): Don't emit a fatal
	error for non-SHF_ALLOC SHF_GNU_MBIND here.
	(obj_elf_parse_section_letters): Return SHF_GNU_MBIND in new
	gnu_attr param.
	(obj_elf_section): Adjust obj_elf_parse_section_letters call.
	Formatting.  Set SHF_GNU_MBIND and elf_osabi from gnu_attr.
	Emit normal error for non-SHF_ALLOC SHF_GNU_MBIND and wrong osabi.
	(obj_elf_type): Set elf_osabi for ifunc.
	* testsuite/gas/elf/section12a.d: xfail msp430 and hpux.
	* testsuite/gas/elf/section12b.d: Likewise.
	* testsuite/gas/elf/section13.d: Likewise.
	* testsuite/gas/elf/section13.l: Adjust expected error.
ld/
	* emultempl/elf32.em (gld${EMULATION_NAME}_place_orphan): Condition
	SHF_GNU_MBIND on osabi.  Set output elf_gnu_osabi_mbind.
2019-07-23 18:22:02 +09:30
Alan Modra
89ebb345e7 gas "mbind sections" test
Doesn't fail on rx-elf

	* testsuite/gas/elf/section12a.d: Don't skip for rx.
2019-07-23 18:22:01 +09:30
Barnaby Wilks
236ab0c60c This patch addresses the change in the June Armv8.1-M Mainline specification, that marks certain MVE instructions as no longer UNPREDICTABLE when a source operand is the same as a destination operand for a 32-bit element size.
The instructions that this change apply to are:

  VQDMLADH, VQRDMLADH, VQDMLSDH, VQRDMLSDH

The updated documentation is here: https://static.docs.arm.com/ddi0553/bh/DDI0553B_h_armv8m_arm.pdf

Fixed this by removing the check for this warning from GAS as well as opcodes.

Added testcases to test that the warning is not generated for the instructions that have a 32-bit element size
and the same source and destination operand. Also fixed tests that would previously check for this warning.

gas	* config/tc-arm.c (do_mve_vqdmladh): Remove check for UNPREDICTABLE.
	* testsuite/gas/arm/mve-vqdmladh-bad.l: Remove tests.
	* testsuite/gas/arm/mve-vqdmladh-bad.s: Remove tests.
	* testsuite/gas/arm/mve-vqdmladh.d: New tests.
	* testsuite/gas/arm/mve-vqdmladh.s: New tests.
	* testsuite/gas/arm/mve-vqdmlsdh-bad.l: Remove tests.
	* testsuite/gas/arm/mve-vqdmlsdh-bad.s: Remove tests.
	* testsuite/gas/arm/mve-vqdmlsdh.d: New tests.
	* testsuite/gas/arm/mve-vqdmlsdh.s: New tests.

opcodes	* arm-dis.c (is_mve_unpredictable): Stop marking some MVE
	instructions as UNPREDICTABLE.
2019-07-22 13:18:27 +01:00
H.J. Lu
ec38ac465d x86: Pass -O0 to assembler in noextreg.d
* testsuite/gas/i386/noextreg.d: Pass -O0 to assembler.
2019-07-19 11:07:59 -07:00
Jose E. Marchesi
231097b03a cpu,opcodes,gas: use %r0 and %r6 instead of %a and %ctf in eBPF disassembler
This patch changes the eBPF CPU description to prefer the register
names %r0 and %r6 instead of %a and %ctx when disassembling.  This
matches better with the current practice, vs. cBPF.

It also updates the GAS tests in order to reflect this change.
Tested in a x86_64 host.

cpu/ChangeLog:

2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf.cpu (h-gpr): when disassembling, use %r0 and %r6 instead of
	%a and %ctx.

opcodes/ChangeLog:

2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf-desc.c: Regenerated.

gas/ChangeLog:

2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* testsuite/gas/bpf/alu.d: Use %r6 instead of %ctx.
	* testsuite/gas/bpf/lddw-be.d: Likewise.
	* testsuite/gas/bpf/lddw.d: Likewise.
	* testsuite/gas/bpf/alu-be.d: Likewise.
	* testsuite/gas/bpf/alu32.d: Likewise.
2019-07-19 15:35:43 +02:00
Jose E. Marchesi
1802aae844 gas: make .lcomm to accept an optional aligmnet in eBPF targets
Tested in a x86_64 host.

gas/ChangeLog:

2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* config/tc-bpf.c (pe_lcomm_internal): Adapted from tc-i386.c.
	(pe_lcomm): Likewise.
	(md_pseudo_table): Use pe_lcomm to implement .lcomm.
2019-07-19 15:35:02 +02:00
Richard Sandiford
ccbdd22fb9 [AArch64] Rename +bitperm to +sve2-bitperm
After some discussion, we've decided to rename the +bitperm feature
flag to +sve2-bitperm, so that it's consistent with the other SVE2
feature flags.  The associated internal macros already used
"SVE2_BITPERM", so only the feature flag itself needs to change.

2019-07-19  Richard Sandiford  <richard.sandiford@arm.com>

gas/
	* doc/c-aarch64.texi: Remame the +bitperm extension to +sve2-bitperm.
	* config/tc-aarch64.c (aarch64_features): Likewise.
	* testsuite/gas/aarch64/illegal-sve2-aes.d: Update accordingly.
	* testsuite/gas/aarch64/illegal-sve2-sha3.d: Likewise.
	* testsuite/gas/aarch64/illegal-sve2-sm4.d: Likewise.
	* testsuite/gas/aarch64/illegal-sve2.d: Likewise.
	* testsuite/gas/aarch64/sve2.d: Likewise.
2019-07-19 12:18:02 +01:00
Alan Modra
c213164ad2 [PowerPC64] pc-relative TLS relocations
This patch supports using pcrel instructions in TLS code sequences.  A
number of new relocations are needed, gas operand modifiers to
generate those relocations, and new TLS optimisation.  For
optimisation it turns out that the new pcrel GD and LD sequences can
be distinguished from the non-pcrel GD and LD sequences by there being
different relocations on the new sequence.  The final "add ra,rb,13"
on IE sequences similarly needs a new relocation, or as I chose, a
modification of R_PPC64_TLS.  On pcrel IE code, the R_PPC64_TLS points
one byte into the "add" instruction rather than being on the
instruction boundary.

GD:
 pla 3,z@got@tlsgd@pcrel	  # R_PPC64_GOT_TLSGD34
 bl __tls_get_addr@notoc(z@tlsgd) # R_PPC64_TLSGD and R_PPC64_REL24_NOTOC
  edited to IE
   pld 3,z@got@tprel@pcrel
   add 3,3,13
  edited to LE
   paddi 3,13,z@tprel
   nop

LD:
 pla 3,z@got@tlsld@pcrel	  # R_PPC64_GOT_TLSLD34
 bl __tls_get_addr@notoc(z@tlsld) # R_PPC64_TLSLD and R_PPC64_REL24_NOTOC
 ..
 paddi 9,3,z2@dtprel
 pld 10,z3@got@dtprel@pcrel
 add 10,10,3
  edited to LE
   paddi 3,13,0x1000
   nop

IE:
 pld 9,z@got@tprel@pcrel	  # R_PPC64_GOT_TPREL34
 add 3,9,z@tls@pcrel		  # R_PPC64_TLS at insn+1
 ldx 4,9,z@tls@pcrel
 lwax 5,9,z@tls@pcrel
 stdx 5,9,z@tls@pcrel
  edited to LE
  paddi 9,13,z@tprel
  nop
  ld 4,0(9)
  lwa 5,0(9)
  std 5,0(9)

LE:
 paddi 10,13,z@tprel

include/
	* elf/ppc64.h (R_PPC64_TPREL34, R_PPC64_DTPREL34),
	(R_PPC64_GOT_TLSGD34, R_PPC64_GOT_TLSLD34),
	(R_PPC64_GOT_TPREL34, R_PPC64_GOT_DTPREL34): Define.
	(IS_PPC64_TLS_RELOC): Include new tls relocs.
bfd/
	* reloc.c (BFD_RELOC_PPC64_TPREL34, BFD_RELOC_PPC64_DTPREL34),
	(BFD_RELOC_PPC64_GOT_TLSGD34, BFD_RELOC_PPC64_GOT_TLSLD34),
	(BFD_RELOC_PPC64_GOT_TPREL34, BFD_RELOC_PPC64_GOT_DTPREL34),
	(BFD_RELOC_PPC64_TLS_PCREL): New pcrel tls relocs.
	* elf64-ppc.c (ppc64_elf_howto_raw): Add howtos for pcrel tls relocs.
	(ppc64_elf_reloc_type_lookup): Translate pcrel tls relocs.
	(must_be_dyn_reloc, dec_dynrel_count): Add R_PPC64_TPREL64.
	(ppc64_elf_check_relocs): Support pcrel tls relocs.
	(ppc64_elf_tls_optimize, ppc64_elf_relocate_section): Likewise.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.
gas/
	* config/tc-ppc.c (ppc_elf_suffix): Map "tls@pcrel", "got@tlsgd@pcrel",
	"got@tlsld@pcrel", "got@tprel@pcrel", and "got@dtprel@pcrel".
	(fixup_size, md_assemble): Handle pcrel tls relocs.
	(ppc_force_relocation, ppc_fix_adjustable): Likewise.
	(md_apply_fix, tc_gen_reloc): Likewise.
ld/
	* testsuite/ld-powerpc/tlsgd.d,
	* testsuite/ld-powerpc/tlsgd.s,
	* testsuite/ld-powerpc/tlsie.d,
	* testsuite/ld-powerpc/tlsie.s,
	* testsuite/ld-powerpc/tlsld.d,
	* testsuite/ld-powerpc/tlsld.s: New tests.
	* testsuite/ld-powerpc/powerpc.exp: Run them.
2019-07-19 18:01:25 +09:30
Jose E. Marchesi
d0044bac9e gas: .lcomm gets an alignment argument in eBPF
gas/ChangeLog:

2019-07-17  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* config/tc-bpf.c: Make .lcomm to get a third argument with the
	alignment.
2019-07-18 13:12:33 +02:00
Jose E. Marchesi
e0b989a6d7 gas: support .half, .word and .dword directives in eBPF
This little patch adds support to the eBPF port of GAS for a few data
directives.  The names for the directives have been chosen to be
coherent with the suffixes used in eBPF instructions: b, h, w and dw
for 8, 16, 32 and 64-bit values respectively.

Documentation and tests included.
Tested in a x86_64 host.

gas/ChangeLog:

2019-07-17  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* config/tc-bpf.c (md_pseudo_table): .half, .word and .dword.
	* testsuite/gas/bpf/data.s: New file.
	* testsuite/gas/bpf/data.d: Likewise.
	* testsuite/gas/bpf/data-be.d: Likewise.
	* testsuite/gas/bpf/bpf.exp: Run data and data-be.
	* doc/c-bpf.texi (BPF Directives): New section.
2019-07-17 22:57:23 +02:00
Jan Beulich
8dc0818eb2 x86: replace "anymem" checks where possible
Once operand parsing has completed, the simpler check of Operand_Mem can
be used in places where i.types[] got passed to operand_type_check().
Note that this has shown a couple of omissions of adjusting i.flags[]
when playing with i.op[] / i.types[] / i.tm.operand_types[].  Not all of
them get added here, just all of the ones needed in process_operands().
2019-07-17 09:16:31 +02:00
Jan Beulich
dfd6917457 x86: make RegMem an opcode modifier
... instead of an operand type bit: It's an insn property, not an
operand one.  There's just one actual change to be made to the
templates: Most are now required to have the (unswapped) destination go
into ModR/M.rm, so VMOVD template needs its opcode adjusted accordingly
and its operands swapped.  {,V}MOVS{S,D}, otoh, are left alone in this
regard, as otherwise generated code would differ from what we've been
producing so far (which I don't think is wanted).

Take the opportunity and add a missing IgnoreSize to pextrb (leading to
an error in 16-bit mode), and take the liberty to once again drop stray
IgnoreSize attributes from lines changed and neighboring related ones.
2019-07-16 09:31:36 +02:00
Jan Beulich
21df382b91 x86: fold SReg{2,3}
They're the only exception to there generally being no mix of register
kinds possible in an insn operand template, and there being two bits per
operand for their representation is also quite wasteful, considering the
low number of uses.  Fold both bits and deal with the little bit of
fallout.

Also take the liberty and drop dead code trying to set REX_B: No segment
register has RegRex set on it.

Additionally I was quite surprised that PUSH/POP with the permitted
segment registers is not covered by the test cases.  Add the missing
pieces.
2019-07-16 09:30:29 +02:00
Jose E. Marchesi
3719fd55b6 cpu,opcodes,gas: fix explicit arguments to eBPF ldabs instructions
This patch fixes the eBPF CPU description in order to reflect the
right explicit arguments passed to the ldabs{b,h,w,dw} instructions,
updates the corresponding GAS tests, and updates the BPF section of
the GAS manual.

cpu/ChangeLog:

2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf.cpu (dlabs): New pmacro.
	(dlind): Likewise.

opcodes/ChangeLog:

2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf-desc.c: Regenerate.
	* bpf-opc.c: Likewise.
	* bpf-opc.h: Likewise.

gas/ChangeLog:

2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* testsuite/gas/bpf/mem.s: ldabs instructions do not take a `src'
	register as an argument.
	* testsuite/gas/bpf/mem.d: Updated accordingly.
	* testsuite/gas/bpf/mem-be.d: Likewise.
	* doc/c-bpf.texi (BPF Opcodes): Update to reflect the correct
	explicit arguments to ldabs and ldind instructions.
2019-07-15 16:00:28 +02:00
Jose E. Marchesi
92434a14b9 cpu,opcodes,gas: fix arguments to ldabs and ldind eBPF instructions
The eBPF non-generic load instructions ldind{b,h,w,dw} and
ldabs{b,h,w,dw} do not take an explicit destination register as an
argument.  Instead, they put the loaded value in %r0, implicitly.

This patch fixes the CPU BPF description to not expect a 'dst'
argument in these arguments, regenerates the corresponding files in
opcodes, and updates the impacted GAS tests.

Tested in a x86-64 host.

cpu/ChangeLog:

2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf.cpu (dlsi): ldabs and ldind instructions do not take an
	explicit 'dst' argument.

opcodes/ChangeLog:

2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf-desc.c: Regenerate.
	* bpf-opc.c: Likewise.

gas/ChangeLog:

2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* testsuite/gas/bpf/mem.s: Do not use explicit arguments for
	ldabs and ldind instructions.
	* testsuite/gas/bpf/mem.d: Updated accordingly.
	* testsuite/gas/bpf/mem-be.d: Likewise.
2019-07-14 14:45:31 +02:00
Alan Modra
d69cd47e7e Re: gas/ELF: don't accumulate .type settings
git commit f2d4ba38f5 caused many failures for mips-sgi-irix targets,
and added a new test that failed for aarch64, nds32, and rl78.
The mips failures are due to BSF_OBJECT being set in many cases for
symbols by the mips .global/.globl directive.  This patch removes that
code and instead sets BSF_OBJECT in a target frob_symbol function,
also moving the mips hacks in elf_frob_symbol to the new function.

Note that common symbols are handled fine in elf.c:swap_out_syms
without needing to set BSF_OBJECT, so that old code can disappear.

	* config/obj-elf.c (elf_frob_symbol): Remove mips hacks.
	* config/tc-mips.h (tc_frob_symbol): Define.
	(mips_frob_symbol): Declare.
	* config/tc-mips.c (s_mips_globl): Don't set BSF_OBJECT for irix.
	(mips_frob_symbol): Fudge symbols for irix here.
	* testsuite/gas/elf/type-2.e: Allow random target symbols.
2019-07-09 14:30:00 +09:30
Jim Wilson
98602811d8 Kito's 5-part patch set to improve .insn support.
From Kito Cheng <kito.cheng@sifive.com>
	gas/ChangeLog
	* doc/c-riscv.texi (Instruction Formats): Add r4 type.
	* testsuite/gas/riscv/insn.d: Add testcase for r4 type.
	* testsuite/gas/riscv/insn.s: Ditto.
	* doc/c-riscv.texi (Instruction Formats): Add b and j type.
	* testsuite/gas/riscv/insn.d: Add test case for b and j type.
	* testsuite/gas/riscv/insn.s: Ditto.
	* testsuite/gas/riscv/insn.s: Correct instruction type for load
	and store.
	* testsuite/gas/riscv/insn.d: Using regular expression to match
	address.
	* doc/c-riscv.texi (Instruction Formats): Fix encoding table for SB
	type and fix typo.
	opcode/ChangeLog
	* riscv-opc.c (riscv_insn_types): Add r4 type.
	* riscv-opc.c (riscv_insn_types): Add b and j type.
	* opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
	format for sb type and correct s type.
2019-07-05 15:19:11 +08:00
Jan Beulich
d4693039f9 x86: correct "-Q" option handling
For another patch I wanted to use a sufficiently benign option (simply
to be able to specify one, which certain test case invocations require),
and I stumbled across -Q in the --help output.  Before realizing that
this is x86-specific anyway, I've tried and and ran into a mysterious
testsuite failure, until I further realized that other than the help
text suggests the option requires an argument.  Correct the help text,
and make the implementation actually match what the comment there has
been describing (and what the help text now says).
2019-07-04 10:36:41 +02:00
Jan Beulich
f2d4ba38f5 gas/ELF: don't accumulate .type settings
Recently a patch was submitted for a Xen Project test harness binary to
override the compiler specified @object to @func (see [1]). In a reply I
suggested we shouldn't make ourselves dependent on currently unspecified
behavior of gas here: It accumulates all requests, and then
bfd/elf.c:swap_out_syms(), in an apparently ad hoc manner, prioritizes
certain flags over others.

Make the behavior predictable: Generally the last .type is what counts.
Exceptions are directives which set multiple bits (TLS, IFUNC, and
UNIQUE): Subsequent directives requesting just the more generic bit
(i.e. FUNC following IFUNC) won't clear the more specific one.  Warn
about incompatible changes, except from/to STT_NOTYPE.

Also add a new target hook, which hppa wants to use right away afaict.

In the course of adding the warning I ran into two ld testsuite
failures.  I can only assume that it was a copy-and-paste mistake that
lead to the same symbol having its type set twice.

[1] https://lists.xenproject.org/archives/html/xen-devel/2019-05/msg01980.html
2019-07-04 10:35:47 +02:00
Nick Clifton
077a039f70 Fix assembler tests to work with toolchains that have been configured with --enable-generate-build-notes. 2019-07-03 15:26:32 +01:00
Barnaby Wilks
163b2c58bd This patch fixes a bug in the AArch64 assembler where an incorrect structural load/store by element instruction would generate the wrong error message.
For example, when provided with the (incorrect) instruction

st4 {v0.16b-v3.16b}[4],[x0]

currently assembler provides the following error message
"Error: comma expected between operands at operand 2 -- `st4 {v0.16b-v3.16b}[4],[x0]'".

This was due to the assembler consuming the {v0.16b-v3.16b} as the first operand leaving
[4],[x0] as what it believed to be the second operand.

The actual error is that the first operand should be of element type and not
vector type (as provided). The new diagnostic for this error is
"Error: expected element type rather than vector type at operand 1 -- `st4 {v0.16b-v3.16b}[4],[x0]'.

Added testcases to check for the correct diagnostic message as well as checking that
variations of the structural load/store by element instruction also generate the error
when they have the same problem.

	* config/tc-aarch64.c (parse_operands): Add error check.
	* testsuite/gas/aarch64/diagnostic.l: New test.
	* testsuite/gas/aarch64/diagnostic.s: New test.
	* testsuite/gas/aarch64/illegal.l: New tests.
	* testsuite/gas/aarch64/illegal.s: New tests.
2019-07-02 14:11:14 +01:00
Richard Sandiford
01c1ee4a70 [AArch64] Allow MOVPRFX to be used with FMOV
The entry for the FMOV alias of FCPY was missing C_SCAN_MOVPRFX.
(The entry for FCPY itself was OK.)

This was the only /m-predicated instruction I could see that was
missing the flag.

2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>

opcodes/
	* aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
	SVE FMOV alias of FCPY.

gas/
	* testsuite/gas/aarch64/sve-movprfx_27.s,
	* testsuite/gas/aarch64/sve-movprfx_27.d: New test.
2019-07-02 10:52:16 +01:00
Richard Sandiford
83adff695c [AArch64] Add missing C_MAX_ELEM flags for SVE conversions
SVE FCVTZS, FCVTZU, SCVTF and UCVTF need the same treatment as FCVT:
the register size used in a predicated MOVPRFX must be the wider of
the destination and source sizes.

Since I was adding a (supposedly) complete set of tests for converts,
it seemed more consistent to add a complete set of tests for shifts
as well, even though there's no bug to fix there.

2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>

opcodes/
	* aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
	to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.

gas/
	* testsuite/gas/aarch64/sve-movprfx_26.s: Also test FCVTZS, FCVTZU,
	SCVTF, UCVTF, LSR and ASR.
	* testsuite/gas/aarch64/sve-movprfx_26.d: Update accordingly.
	* testsuite/gas/aarch64/sve-movprfx_26.l: Likewise.
2019-07-02 10:51:09 +01:00