Commit Graph

112524 Commits

Author SHA1 Message Date
Jan Beulich
a5ce326cfe gas: re-arrange listing output for .irp and alike
It is kind of odd to have the expansions of such constructs ahead of
their definition in listings with macro expansion enabled. Adjust this
by pulling ahead the output of the definition lines, taking care to
avoid producing a listing line for (non-existing) line 0 when the source
is stdin.

Note that with the code movement the conditional operator isn't
necessary anymore - list->line now match up.
2022-12-22 14:31:11 +01:00
Jan Beulich
760ab3d0db x86: correct/improve TSX controls
TSXLDTRK takes RTM as a prereq. Additionally introduce an umbrella "tsx"
extension option covering both RTM and HLE, paralleling the "abm" one we
already have.
2022-12-22 09:36:16 +01:00
Jan Beulich
0919e770af x86: add dependencies on SVME
SEV-ES is an extension to SVME. SNP in turn is an extension to SEV-ES,
and yet in turn RMPQUERY is a SNP extension.

Note that cpu_arch[] has no SNP entry, so CPU_ANY_SNP_FLAGS remains
unused (just like CPU_SNP_FLAGS already is).
2022-12-22 09:35:53 +01:00
Jan Beulich
25626f7939 x86: add dependencies on VMX
Both EPT and VMFUNC are extensions to VMX.
2022-12-22 09:35:32 +01:00
Jan Beulich
af1ad9aac5 x86: correct XSAVE* dependencies
Like various other features AMX-TILE takes XSAVE as a prereq.

XSAVES, unconditionally using compacted format, in turn effectively
takes XSAVEC as a prereq (an SDM clarification to this effect is in the
works).
2022-12-22 09:35:11 +01:00
Jan Beulich
9a019125a6 x86: correct dependencies of a few AVX512 sub-features
Like AVX512-FP16, several other extensions require wider than 16-bit
mask registers. As a result they take AVX512BW as a prereq, not (just)
AVX512F. Which in turn points out wrong expectations in the noavx512-1
testcase.
2022-12-22 09:34:50 +01:00
Jan Beulich
b236b82a1a x86: rework noavx512-1 testcase
So far the set of ".noavx512*" has been accumulating, which isn't ideal.
In particular this hides issues with dependencies between features.
Switch back to the default ISA before disabling a particular subset.
Furthermore limit redundancy by wrapping the repeated block of insns in
an .irp.
2022-12-22 09:34:17 +01:00
Jan Beulich
b20f426174 x86: add dependencies on AVX2
Like AVX-VNNI both VAES and VPCLMUL take AVX2 as a prereq, for operating
on up to 256-bit packed integer vectors.
2022-12-22 09:33:53 +01:00
Jan Beulich
88bd2203ef x86: correct SSE dependencies
SSE itself takes FXSR as a prereq. Like AES, PCLMUL, and SHA both GFNI
and KL take SSE2 as a prereq, for operating on packed integers. And
while correcting KL also record it as a prereq to WIDEKL.
2022-12-22 09:33:26 +01:00
Jan Beulich
5091b9ee34 x86: correct what gets disabled by certain ".arch .no*"
Features with prereqs as well as features with dependents cannot re-use
CPU_*_MASK for the 3rd argument of SUBARCH() - they need to use
CPU_ANY_*_MASK in order to avoid disabling too many (when there are
prereqs) and/or too few (when there are dependents) features.

Generally any CPU_ANY_*_MASK which exist should not remain unused.
Exceptions are
- FISTTP which has no corresponding entry in cpu_arch[],
- IAMCU which is a base architecture and hence uses ARCH(), not
  SUBARCH() (only extensions can be disabled, but unlike for Cpu*86 it
  would be a little more clumsy to suppress generating of the #define).
2022-12-22 09:33:01 +01:00
Jan Beulich
4d97c5c833 x86: re-work ISA extension dependency handling
Getting both forward and reverse ISA dependencies right / consistent has
been a permanent source of mistakes. Reduce what needs specifying
manually to just the direct forward dependencies. Transitive forward
dependencies as well as reverse ones are now derived and hence cannot go
out of sync anymore (at least in the vast majority of cases; there are a
few special cases to still take care of manually). In the course of this
several CPU_ANY_*_FLAGS disappear, requiring adjustment to the
assembler's cpu_arch[].

Note that to retain the correct reverse dependency of AVX512F wrt
AVX512-VP2INTERSECT, the latter has the previously missing AVX512F
prereq added.

Note further that to avoid adding the following undue prereqs:
* ATHLON, K8, and AMDFAM10 gain CMOV and FXSR,
* IAMCU gains 387,
auxiliary table entries (including a colon-separated modifier) are
introduced in addition to the ones representing from converting the old
table.

To maintain forward-only dependencies between AVX (XOP) and SSE* (SSE4a)
(i.e. "nosse" not disabling AVX), reverse dependency tracking is
artifically suppressed.

As a side effect disabling of SSE or SSE2 will now also disable AES,
PCLMUL, and SHA (respective elements were missing from
CPU_ANY_SSE2_FLAGS).
2022-12-22 09:32:29 +01:00
Mike Frysinger
2011a54779 sim: mips: match target on cpu settings
We don't need to enforce larger target settings when the only thing
the sim should care about is the CPU target.  So reduce most of the
target matches to only check the CPU.
2022-12-21 22:27:12 -05:00
Mike Frysinger
d455df988a sim: mips: move fpu bitsize defines to top-level configure
This drops support for the --enable-sim-float configure option,
but it's not clear anyone ever actually used that.  Eventually
we'll want this to be a runtime option anyways.
2022-12-21 22:27:12 -05:00
Mike Frysinger
19b11256a5 sim: mips: move bitsize defines to top-level configure
Since the msb value is always defined as the wordsize-1, stop
hardcoding that value directly, and use a CPP value instead.
2022-12-21 22:27:12 -05:00
Mike Frysinger
2d5700ad4e sim: mips: move subtarget defines to top-level configure
We want to kill off mips/configure entirely.  Move this small part
out now to get started.
2022-12-21 22:27:11 -05:00
Mike Frysinger
0fb6c560ff sim: mips: always resolve active bfd mach dynamically
Don't assume that the default bfd that we configured for is the one
that is always active when running a program.  We already have access
to the real runtime value, so use it directly.  This simplifies the
code quite a bit, and will make it easier to support multiple mach's
in a single binary.
2022-12-21 22:27:11 -05:00
Mike Frysinger
f4ac230605 sim: hw-config.h: move generation to top-level
In order to compile arch objects from the top-level, we need to
generate the hw-config.h header, so move that logic up to the top
level first.
2022-12-21 22:21:25 -05:00
Mike Frysinger
3d04211786 sim: build: hoist lists of hw devices up
We need these in the top-level to generate libsim.a, but also in the
subdirs to generate hw-config.h.  Move it to the local.mk, and pass
it down when running recursive make.  This avoids duplication, and
makes it available to both.  We can simplify this once we move the
various steps up to the top-level too.
2022-12-21 22:21:25 -05:00
Mike Frysinger
d47ea1b9c1 sim: build: hoist lists of common objects up
In order to create libsim.a in the common dir, we need the list of
objects for each target.  To avoid duplicating the list with the
recursive make in each port, pass it down as a variable.  This is
a temporary hack until the top-level creates libsim.a for ports.
2022-12-21 22:21:25 -05:00
GDB Administrator
e9c4e2d24f Automatic date update in version.in 2022-12-22 00:01:01 +00:00
Alan Modra
d28fbc7197 PR29925, Memory leak in find_abstract_instance
The testcase in the PR had a variable with both DW_AT_decl_file and
DW_AT_specification, where the DW_AT_specification also specified
DW_AT_decl_file.  This leads to a memory leak as the file name is
malloced and duplicates are not expected.

I've also changed find_abstract_instance to not use a temp for "name",
because that can result in a change in behaviour from the usual last
of duplicate attributes wins.

	PR 29925
	* dwarf2.c (find_abstract_instance): Delete "name" variable.
	Free *filename_ptr before assigning new file name.
	(scan_unit_for_symbols): Similarly free func->file and
	var->file before assigning.
2022-12-22 07:03:07 +10:30
Andrew Pinski
f7cb9bba3d Fix compiling of top.c
When I moved my last patch forward, somehow I missed removing
the #endif for the HAVE_LIBMPFR case.

Committed as obvious after a quick build.

gdb/ChangeLog:
	* top.c: Remove the extra #endif which was missed.
2022-12-21 17:32:40 +00:00
Andrew Pinski
9911806278 Use toplevel configure for GMP and MPFR for gdb
This patch uses the toplevel configure parts for GMP/MPFR for
gdb. The only thing is that gdb now requires MPFR for building.
Before it was a recommended but not required library.
Also this allows building of GMP and MPFR with the toplevel
directory just like how it is done for GCC.
We now error out in the toplevel configure of the version
of GMP and MPFR that is wrong.

OK after GDB 13 branches? Build gdb 3 ways:
with GMP and MPFR in the toplevel (static library used at that point for both)
With only MPFR in the toplevel (GMP distro library used and MPFR built from source)
With neither GMP and MPFR in the toplevel (distro libraries used)

Changes from v1:
* Updated gdb/README and gdb/doc/gdb.texinfo.
* Regenerated using unmodified autoconf-2.69

Thanks,
Andrew Pinski

ChangeLog:
	* Makefile.def: Add configure-gdb dependencies
	on all-gmp and all-mpfr.
	* configure.ac: Split out MPC checking from MPFR.
	Require GMP and MPFR if the gdb directory exist.
	* Makefile.in: Regenerate.
	* configure: Regenerate.

gdb/ChangeLog:

	PR bug/28500
	* configure.ac: Remove AC_LIB_HAVE_LINKFLAGS
	for gmp and mpfr.
	Use GMPLIBS and GMPINC which is provided by the
	toplevel configure.
	* Makefile.in (LIBGMP, LIBMPFR): Remove.
	(GMPLIBS, GMPINC): Add definition.
	(INTERNAL_CFLAGS_BASE): Add GMPINC.
	(CLIBS): Exchange LIBMPFR and LIBGMP
	for GMPLIBS.
	* target-float.c: Make the code conditional on
	HAVE_LIBMPFR unconditional.
	* top.c: Remove code checking HAVE_LIBMPFR.
	* configure: Regenerate.
	* config.in: Regenerate.
	* README: Update GMP/MPFR section of the config
	options.
	* doc/gdb.texinfo: Likewise.

Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=28500
2022-12-21 16:49:23 +00:00
Bruno Larsen
68ce1575fc gdb/c++: validate 'using' directives based on the current line
When asking GDB to print a variable from an imported namespace, we only
want to see variables imported in lines that the inferior has already
gone through, as is being tested last in gdb.cp/nsusing.exp. However
with the proposed change to gdb.cp/nsusing.exp, we get the following
failures:

(gdb) PASS: gdb.cp/nsusing.exp: continue to breakpoint: marker10 stop
print x
$9 = 911
(gdb) FAIL: gdb.cp/nsusing.exp: print x, before using statement
next
15        y += x;
(gdb) PASS: gdb.cp/nsusing.exp: using namespace M
print x
$10 = 911
(gdb) PASS: gdb.cp/nsusing.exp: print x, only using M

Showing that the feature wasn't functioning properly, it just so
happened that gcc ordered the namespaces in a convenient way.
This happens because GDB doesn't take into account the line where the
"using namespace" directive is written. So long as it shows up in the
current scope, we assume it is valid.

To fix this, add a new member to struct using_direct, that stores the
line where the directive was written, and a new function that informs if
the using directive is valid already.

Unfortunately, due to a GCC bug, the failure still shows up. Compilers
that set the declaration line of the using directive correctly (such as
Clang) do not show such a bug, so the test includes an XFAIL for gcc
code.

Finally, because the final test of gdb.cp/nsusing.exp has turned into
multiple that all would need XFAILs for older GCCs (<= 4.3), and that
GCC is very old, if it is detected, the test just exits early.

Approved-by: Tom Tromey <tom@tromey.com>
2022-12-21 16:26:44 +01:00
Nick Clifton
ea6ed58e63 Updated Romanian translation for the BFD sub-directory. 2022-12-21 12:19:04 +00:00
Nick Clifton
75393a2d54 Fix an attempt to allocate an unreasonably large amount of memory when parsing a corrupt ELF file.
PR  29924
	* objdump.c (load_specific_debug_section): Check for excessively
	large sections.
2022-12-21 11:51:23 +00:00
Nick Clifton
a7a32d588f Keep the .drectve section when performing a relocateable link.
PR 29900
	* scripttempl/pe.sc: Keep the .drectve section when performing a
	relocateable link.
	* scripttempl/pep.sc: Likewise.
2022-12-21 10:23:08 +00:00
Jan Beulich
9c19e9ec4d x86: rename CheckRegSize to CheckOperandSize
While originally indeed used for register size checking only, the
attribute has been used for memory operand size checking as well already
for quite a while, with more such uses recently having been added.
2022-12-21 09:07:03 +01:00
Jan Beulich
6b7d3204b5 gprofng/testsuite: restrict testing to native configurations
The binaries involved in testing gprofng are native ones, and hence a
cross build of binutils won't really test intended functionality. Since
this testing takes quite a bit of time (typically more than running all
of binutils, gas, and ld testsuites together), restrict the testing to
native configurations only.
2022-12-21 09:05:43 +01:00
Alan Modra
c63d486281 enable-non-contiguous-regions warnings
The warning about discarded sections in elf_link_input_bfd doesn't
belong there since the code is dealing with symbols.  Multiple symbols
in a discarded section will result in multiple identical warnings
about the section.  Move the warning to a new function in ldlang.c.

The patch also tidies the warning quoting of section and file names,
consistently using `%pA' and `%pB'.  I'm no stickler for one style of
section and file name quoting, but they ought to be consistent within
a warning, eg. see the first one fixed in ldlang.c, and when a warning
is emitted for multiple targets they all ought to use exactly the same
format string to reduce translation work.  elf64-ppc.c loses the
build_one_stub errors since we won't get there before hitting the
fatal errors in size_one_stub.

bfd/
	* elflink.c (elf_link_input_bfd): Don't warn here about
	discarded sections.
	* elf32-arm.c (arm_build_one_stub): Use consistent style in
	--enable-non-contiguous-regions error.
	* elf32-csky.c (csky_build_one_stub): Likewise.
	* elf32-hppa.c (hppa_build_one_stub): Likewise.
	* elf32-m68hc11.c (m68hc11_elf_build_one_stub): Likewise.
	* elf32-m68hc12.c (m68hc12_elf_build_one_stub): Likewise.
	* elf32-metag.c (metag_build_one_stub): Likewise.
	* elf32-nios2.c (nios2_build_one_stub): Likewise.
	* elfnn-aarch64.c (aarch64_build_one_stub): Likewise.
	* xcofflink.c (xcoff_build_one_stub): Likewise.
	* elf64-ppc.c (ppc_size_one_stub): Likewise.
	(ppc_build_one_stub): Delete dead code.
ld/
	* ldlang.c (lang_add_section): Use consistent style in
	--enable-non-contiguous-regions warnings.
	(size_input_section): Likewise.
	(warn_non_contiguous_discards): New function.
	(lang_process): Call it.
	* testsuite/ld-arm/non-contiguous-arm.d: Update.
	* testsuite/ld-arm/non-contiguous-arm4.d: Update.
	* testsuite/ld-arm/non-contiguous-arm7.d: Add
	--enable-non-contiguous-regions-warnings.
	* testsuite/ld-arm/non-contiguous-arm7.err: New.
	* testsuite/ld-powerpc/non-contiguous-powerpc.d: Update.
	* testsuite/ld-powerpc/non-contiguous-powerpc64.d: Update.
2022-12-21 17:56:27 +10:30
Alan Modra
8f2c64de86 PR29922, SHT_NOBITS section avoids section size sanity check
PR 29922
	* dwarf2.c (find_debug_info): Ignore sections without
	SEC_HAS_CONTENTS.
2022-12-21 17:55:34 +10:30
Mike Frysinger
8df77a27a3 sim: fully merge sim_cpu_base into sim_cpu
Now that all ports have migrated to the new framework, drop support
for the old sim_cpu_base layout.  There's a lot of noise here, so
it's been split into a dedicated commit.
2022-12-21 00:00:19 -05:00
Mike Frysinger
4a21ad1e76 sim: enable common sim_cpu usage everywhere
All ports should be migrated now.  Drop the SIM_HAVE_COMMON_SIM_CPU
knob and require it be used everywhere now.
2022-12-21 00:00:18 -05:00
Mike Frysinger
4c3c31719b sim: or1k: invert sim_cpu storage
The cpu.h change is in generated cgen code, but that has been sent
upstream too, so the next regen should include it automatically.
2022-12-21 00:00:01 -05:00
Mike Frysinger
9a9db21d12 sim: m32r: invert sim_cpu storage
The cpu*.h changes are in generated cgen code, but that has been sent
upstream too, so the next regen should include it automatically.
2022-12-21 00:00:01 -05:00
Mike Frysinger
63c5692305 sim: lm32: invert sim_cpu storage
The cpu.h change is in generated cgen code, but that has been sent
upstream too, so the next regen should include it automatically.
2022-12-21 00:00:01 -05:00
Mike Frysinger
06f4b7b6d1 sim: iq2000: invert sim_cpu storage
The cpu.h change is in generated cgen code, but that has been sent
upstream too, so the next regen should include it automatically.
2022-12-21 00:00:01 -05:00
Mike Frysinger
811727abbd sim: frv: invert sim_cpu storage
The cpu.h change is in generated cgen code, but that has been sent
upstream too, so the next regen should include it automatically.
2022-12-21 00:00:01 -05:00
Mike Frysinger
8681713743 sim: cris: invert sim_cpu storage
The cpu*.h changes are in generated cgen code, but that has been sent
upstream too, so the next regen should include it automatically.
2022-12-21 00:00:01 -05:00
Mike Frysinger
ef7878a286 sim: bpf: invert sim_cpu storage
The cpu.h change is in generated cgen code, but that has been sent
upstream too, so the next regen should include it automatically.
2022-12-21 00:00:01 -05:00
Mike Frysinger
53891d9a7c sim: cgen: prep for inverting sim_cpu storage
Some common cgen code changes to allow cgen ports to invert their
sim_cpu storage one-by-one.
2022-12-21 00:00:01 -05:00
Mike Frysinger
5409cab77e sim: riscv: invert sim_cpu storage 2022-12-21 00:00:01 -05:00
Mike Frysinger
3d165c11f0 sim: pru: invert sim_cpu storage 2022-12-21 00:00:01 -05:00
Mike Frysinger
86ecb89bb7 sim: example-synacor: invert sim_cpu storage 2022-12-21 00:00:01 -05:00
Mike Frysinger
3fbdc6f908 sim: h8300: invert sim_cpu storage 2022-12-21 00:00:01 -05:00
Mike Frysinger
79d784aef9 sim: m68hc11: invert sim_cpu storage 2022-12-21 00:00:01 -05:00
Mike Frysinger
8e9408080b sim: mips: invert sim_cpu storage 2022-12-21 00:00:01 -05:00
Mike Frysinger
6d53d06992 sim: v850: invert sim_cpu storage 2022-12-21 00:00:01 -05:00
Mike Frysinger
620dd532fe sim: mcore: invert sim_cpu storage 2022-12-21 00:00:00 -05:00
Mike Frysinger
6a08ae198b sim: aarch64: invert sim_cpu storage 2022-12-21 00:00:00 -05:00