Commit Graph

195 Commits

Author SHA1 Message Date
Cui,Lili
bb651e8b7f Add support for intel TSXLDTRK instructions$
gas/

	* config/tc-i386.c (cpu_arch): Add .TSXLDTRK.
	(cpu_noarch): Likewise.
	* doc/c-i386.texi: Document TSXLDTRK.
	* testsuite/gas/i386/i386.exp: Run TSXLDTRK tests.
	* testsuite/gas/i386/tsxldtrk.d: Likewise.
	* testsuite/gas/i386/tsxldtrk.s: Likewise.
	* testsuite/gas/i386/x86-64-tsxldtrk.d: Likewise.

opcodes/

	* i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
	(prefix_table): New instructions (see prefixes above).
	(rm_table): Likewise.
	* i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
	CPU_ANY_TSXLDTRK_FLAGS.
	(cpu_flags): Add CpuTSXLDTRK.
	* i386-opc.h (enum): Add CpuTSXLDTRK.
	(i386_cpu_flags): Add cputsxldtrk.
	* i386-opc.tbl: Add XSUSPLDTRK insns.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.
2020-04-07 13:59:50 +08:00
LiliCui
4b27d27c07 Add support for intel SERIALIZE instruction
gas/

	* config/tc-i386.c (cpu_arch): Add .serialize.
	(cpu_noarch): Likewise.
	* doc/c-i386.texi: Document serialize.
	* testsuite/gas/i386/i386.exp: Run serialize tests
	* testsuite/gas/i386/serialize.d: Likewise.
	* testsuite/gas/i386/x86-64-serialize.d: Likewise.
	* testsuite/gas/i386/serialize.s: Likewise.

opcodes/

	* i386-dis.c (prefix_table): New instructions serialize.
	* i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
	CPU_ANY_SERIALIZE_FLAGS.
	(cpu_flags): Add CpuSERIALIZE.
	* i386-opc.h (enum): Add CpuSERIALIZE.
	(i386_cpu_flags): Add cpuserialize.
	* i386-opc.tbl: Add SERIALIZE insns.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.
2020-04-02 05:48:36 -07:00
Jan Beulich
643bb87079 x86: drop Rex64 attribute
It is almost entirely redundant with Size64, and the sole case (CRC32)
where direct replacement isn't possible can easily be taken care of in
another way.
2020-03-06 08:52:12 +01:00
Jan Beulich
a847e32224 x86: support VMGEXIT
It has been publicly documented for quite some time, albeit not in the
"General-Purpose and System Instructions" volume:
https://www.amd.com/system/files/TechDocs/24593.pdf.
2020-03-04 08:58:13 +01:00
H.J. Lu
3cd7f3e3bd x86: Replace IgnoreSize/DefaultSize with MnemonicSize
Since an instruction template can't have both IgnoreSize and DefaultSize,
this patch replaces IgnoreSize and DefaultSize with MnemonicSize.

gas/

	* config/tc-i386.c (match_template): Replace ignoresize and
	defaultsize with mnemonicsize.
	(process_suffix): Likewise.

opcodes/

	* i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
	with MnemonicSize.
	* i386-opc.h (IGNORESIZE): New.
	(DEFAULTSIZE): Likewise.
	(IgnoreSize): Removed.
	(DefaultSize): Likewise.
	(MnemonicSize): New.
	(i386_opcode_modifier): Replace ignoresize/defaultsize with
	mnemonicsize.
	* i386-opc.tbl (IgnoreSize): New.
	(DefaultSize): Likewise.
	* i386-tbl.h: Regenerated.
2020-03-03 11:24:26 -08:00
H.J. Lu
272a84b120 x86: Remove CpuABM and add CpuPOPCNT
AMD ABM has 2 instructions: popcnt and lzcnt.  ABM CPUID feature bit has
been reused for lzcnt and a POPCNT CPUID feature bit is added for popcnt
which used to be the part of SSE4.2.  This patch removes CpuABM and adds
CpuPOPCNT.  It changes ABM to enable both lzcnt and popcnt, changes SSE4.2
to also enable popcnt.

gas/

	* config/tc-i386.c (cpu_arch): Add .popcnt.
	* doc/c-i386.texi: Remove abm and .abm.  Add popcnt and .popcnt.
	Add a tab before @samp{.sse4a}.

opcodes/

	* i386-gen.c (cpu_flag_init): Replace CpuABM with
	CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
	CPU_POPCNT_FLAGS.
	(cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
	* i386-opc.h (CpuABM): Removed.
	(CpuPOPCNT): New.
	(i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
	* i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
	popcnt.  Remove CpuABM from lzcnt.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
2020-02-17 07:31:28 -08:00
Jan Beulich
50128d0cab x86: drop ShortForm attribute
It is very simple to derive from other template properties, and hence
there's little point wasting storage for it.
2020-02-11 11:20:55 +01:00
H.J. Lu
4b5aaf5f69 x86: Accept Intel64 only instruction by default
Commit d835a58baa disabled sysenter/sysenter in 64-bit mode by
default.  By default, assembler should accept common, Intel64 only
and AMD64 ISAs since there are no conflicts.

gas/

	PR gas/25516
	* config/tc-i386.c (intel64): Renamed to ...
	(isa64): This.
	(match_template): Accept Intel64 only instruction by default.
	(i386_displacement): Updated.
	(md_parse_option): Updated.
	* c-i386.texi: Update -mamd64/-mintel64 documentation.
	* testsuite/gas/i386/i386.exp: Run x86-64-sysenter.  Pass
	-mamd64 to x86-64-sysenter-amd.
	* testsuite/gas/i386/x86-64-sysenter.d: New file.

opcodes/

	PR gas/25516
	* i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
	with ISA64.
	* i386-opc.h (AMD64): Removed.
	(Intel64): Likewose.
	(AMD64): New.
	(INTEL64): Likewise.
	(INTEL64ONLY): Likewise.
	(i386_opcode_modifier): Replace amd64 and intel64 with isa64.
	* i386-opc.tbl (Amd64): New.
	(Intel64): Likewise.
	(Intel64Only): Likewise.
	Replace AMD64 with Amd64.  Update sysenter/sysenter with
	Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
	* i386-tbl.h: Regenerated.
2020-02-10 08:37:36 -08:00
Alan Modra
b3adc24a07 Update year range in copyright notice of binutils files 2020-01-01 18:42:54 +10:30
Jan Beulich
0cfa3eb352 x86: fold individual Jump* attributes into a single Jump one
..., taking just 3 bits instead of 5. No two of them are used together.
2019-11-14 08:47:44 +01:00
Jan Beulich
6f2f06bea8 x86: make JumpAbsolute an insn attribute
... instead of an operand one: There's only ever one operand here
anyway.
2019-11-14 08:47:03 +01:00
Jan Beulich
601e856422 x86: make AnySize an insn attribute
... instead of an operand one. Which operand it applies to can be
determined from other operand properties, but as it turns out the only
place it is actually used at doesn't even need further qualification.
2019-11-14 08:46:19 +01:00
Jan Beulich
51c8edf68b x86: fold EsSeg into IsString
EsSeg (a per-operand bit) is used with IsString (a per-insn attribute)
only. Extend the attribute to 2 bits, thus allowing to encode
- not a string insn,
- string insn with neither operand requiring use of %es:,
- string insn with 1st operand requiring use of %es:,
- string insn with 2nd operand requiring use of %es:,
which covers all possible cases, allowing to drop EsSeg.

The (transient) need to comment out the OTUnused #define did uncover an
oversight in the earlier OTMax -> OTNum conversion, which is being taken
care of here.
2019-11-12 09:09:31 +01:00
Jan Beulich
474da251bf x86: eliminate ImmExt abuse
Drop the remaining instances left in place by commit c3949f432f ("x86:
limit ImmExt abuse), now that we have a way to specify specific GPRs.

Take the opportunity and also introduce proper 16-bit forms of
applicable SVME insns as well as 1-operand forms of CLZERO.
2019-11-12 09:08:32 +01:00
Jan Beulich
75e5731b8f x86: introduce operand type "instance"
Special register "class" instances can't be combined with one another
(neither in templates nor in register entries), and hence it is not a
good use of resources (memory as well as execution time) to represent
them as individual bits of a bit field.

Furthermore the generalization becoming possible will allow
improvements to the handling of insns accepting only individual
registers as their operands.
2019-11-12 09:07:34 +01:00
Jan Beulich
f74a630727 x86: convert RegMask and RegBND from bitfield to enumerator
This is to further shrink the operand type representation.
2019-11-08 09:06:24 +01:00
Jan Beulich
3528c362d9 x86: convert RegSIMD and RegMMX from bitfield to enumerator
This is to further shrink the operand type representation.
2019-11-08 09:05:36 +01:00
Jan Beulich
4a5c67ed84 x86: convert Control/Debug/Test from bitfield to enumerator
This is to further shrink the operand type representation.
2019-11-08 09:04:53 +01:00
Jan Beulich
00cee14fba x86: convert SReg from bitfield to enumerator
This is to further shrink the operand type representation.
2019-11-08 09:04:09 +01:00
Jan Beulich
bab6aec125 x86: introduce operand type "class"
Many operand types, in particular the various kinds of registers, can't
be combined with one another (neither in templates nor in register
entries), and hence it is not a good use of resources (memory as well as
execution time) to represent them as individual bits of a bit field.
2019-11-08 09:03:23 +01:00
Jan Beulich
142861dfd5 x86: support further AMD Zen2 instructions
Both RDPRU and MCOMMIT have been publicly documented meanwhile:
https://www.amd.com/system/files/TechDocs/24594.pdf.
2019-11-07 09:29:14 +01:00
Jan Beulich
a2cebd03fa x86: slightly rearrange struct insn_template
This avoids holes between the individual fields, (potentially) shrinking
the overall template table size by 4 bytes per entry.
2019-10-30 09:06:42 +01:00
Jan Beulich
507916b855 x86: drop stray W
The flag is used to indicate opcodes which can be switched between byte
and word/dword/qword forms (in a "canonical" way). Obviously it's quite
odd then to see it on insns not allowing for byte operands in the first
place. As a result the opcode bytes need to be adjusted accordingly,
which includes comparisons done in optimize_encoding().

To make re-introduction of such issues less likely have i386-gen
diagnose it (in a generally non-fatal way for now).
2019-10-30 09:05:46 +01:00
Jan Beulich
1d942ae908 x86: drop stale Mem enumerator
This was supposed to also be removed by c48dadc9a8 ('x86: drop "mem"
operand type attribute').  It's odd enough that this hasn't caused
build issues, considering the careful use of OTunused (apparently to
avoid "missing initializer" warnings).

To avoid such happening again introduce compile time consistency
checks.
2019-07-17 09:15:49 +02:00
Jan Beulich
dfd6917457 x86: make RegMem an opcode modifier
... instead of an operand type bit: It's an insn property, not an
operand one.  There's just one actual change to be made to the
templates: Most are now required to have the (unswapped) destination go
into ModR/M.rm, so VMOVD template needs its opcode adjusted accordingly
and its operands swapped.  {,V}MOVS{S,D}, otoh, are left alone in this
regard, as otherwise generated code would differ from what we've been
producing so far (which I don't think is wanted).

Take the opportunity and add a missing IgnoreSize to pextrb (leading to
an error in 16-bit mode), and take the liberty to once again drop stray
IgnoreSize attributes from lines changed and neighboring related ones.
2019-07-16 09:31:36 +02:00
Jan Beulich
21df382b91 x86: fold SReg{2,3}
They're the only exception to there generally being no mix of register
kinds possible in an insn operand template, and there being two bits per
operand for their representation is also quite wasteful, considering the
low number of uses.  Fold both bits and deal with the little bit of
fallout.

Also take the liberty and drop dead code trying to set REX_B: No segment
register has RegRex set on it.

Additionally I was quite surprised that PUSH/POP with the permitted
segment registers is not covered by the test cases.  Add the missing
pieces.
2019-07-16 09:30:29 +02:00
Jan Beulich
9d3bf266fd x86: drop Vec_Imm4
It is pretty wasteful to have a per-operand flag which is used in
exactly 4 cases. It can be relatively easily replaced, and by doing so
I've actually found some dead code to remove at the same time (there's
no case of ImmExt set at the same time as Vec_Imm4).
2019-07-01 08:38:50 +02:00
H.J. Lu
9186c494a3 Enable Intel AVX512_VP2INTERSECT insn
This patch enables support for VP2INTERSECT in binutils.  Please refer to

https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

for VP2INTERSECT details.

Make check-gas is ok.

gas/

2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
	    Lili Cui  <lili.cui@intel.com>

	* config/tc-i386.c (cpu_arch): Add .avx512_vp2intersect.
	(cpu_noarch): Likewise.
	* doc/c-i386.texi: Document avx512_vp2intersect.
	* testsuite/gas/i386/i386.exp: Run vp2intersect tests.
	* testsuite/gas/i386/vp2intersect-intel.d: New test.
	* testsuite/gas/i386/vp2intersect.d: Likewise.
	* testsuite/gas/i386/vp2intersect.s: Likewise.
	* testsuite/gas/i386/vp2intersect-inval-bcast.l: Likewise.
	* testsuite/gas/i386/vp2intersect-inval-bcast.s: Likewise.
	* testsuite/gas/i386/x86-64-vp2intersect-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-vp2intersect.d: Likewise.
	* testsuite/gas/i386/x86-64-vp2intersect.s: Likewise.
	* testsuite/gas/i386/x86-64-vp2intersect-inval-bcast.l: Likewise.
	* testsuite/gas/i386/x86-64-vp2intersect-inval-bcast.s: Likewise.

opcodes/

2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
	    Lili Cui  <lili.cui@intel.com>

	* i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
	* i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
	instructions.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
	CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
	(cpu_flags): Add CpuAVX512_VP2INTERSECT.
	* i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
	(i386_cpu_flags): Add cpuavx512_vp2intersect.
	* i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
2019-06-04 08:58:31 -07:00
H.J. Lu
5d79adc4b2 Add support for Intel ENQCMD[S] instructions
This patch enables support for ENQCMD[S] in binutils.  Please refer to

https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

for ENQCMD[S] details.

Make check-gas is ok.

gas/ChangeLog:

2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
	    Lili Cui  <lili.cui@intel.com>

	* doc/c-i386.texi: Document enqcmd.
	* testsuite/gas/i386/enqcmd-intel.d: New file.
	* testsuite/gas/i386/enqcmd-inval.l: Likewise.
	* testsuite/gas/i386/enqcmd-inval.s: Likewise.
	* testsuite/gas/i386/enqcmd.d: Likewise.
	* testsuite/gas/i386/enqcmd.s: Likewise.
	* testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
	* testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
	* testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
	* testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
	* testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
	enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
	and x86-64-enqcmd.

opcodes/ChangeLog:

2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
	    Lili Cui  <lili.cui@intel.com>

	* i386-dis.c (enum): Add MOD_0F38F8_PREFIX_1 and
	MOD_0F38F8_PREFIX_3.
	(prefix_table): New instructions (see prefix above).
	(mod_table): New instructions (see prefix above).
	* i386-gen.c (cpu_flag_init): Add entries for enqcmd.
	(cpu_flags): Add a bitfield for enqmcd.
	* i386-init.h: Regenerated.
	* i386-opc.h (enum): Add CpuENQCMD.
	(i386_cpu_flags): Add a bitfield for cpuenqcmd.
	* i386-opc.tbl: Add enqcmd and enqcmds instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Regenerated.
2019-06-04 08:50:46 -07:00
Xuepeng Guo
d6aab7a11b x86: Support Intel AVX512 BF16
Add assembler and disassembler support Intel AVX512 BF16:

https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference

gas/

2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>

	* config/tc-i386.c (cpu_arch): Add .avx512_bf16.
	(cpu_noarch): Add noavx512_bf16.
	* doc/c-i386.texi: Document avx512_bf16.
	* testsuite/gas/i386/avx512_bf16.d: New file.
	* testsuite/gas/i386/avx512_bf16.s: Likewise.
	* testsuite/gas/i386/avx512_bf16_vl-inval.l: Likewise.
	* testsuite/gas/i386/avx512_bf16_vl-inval.s: Likewise.
	* testsuite/gas/i386/avx512_bf16_vl.d: Likewise.
	* testsuite/gas/i386/avx512_bf16_vl.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512_bf16.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512_bf16.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.l: Likesie.
	* testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512_bf16_vl.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512_bf16_vl.s: Likewise.
	* testsuite/gas/i386/i386.exp: Add BF16 related tests.

opcodes/

2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>

	* i386-dis-evex.h (evex_table): Updated to support BF16
	instructions.
	* i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
	and EVEX_W_0F3872_P_3.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
	(cpu_flags): Add bitfield for CpuAVX512_BF16.
	* i386-opc.h (enum): Add CpuAVX512_BF16.
	(i386_cpu_flags): Add bitfield for cpuavx512_bf16.
	* i386-opc.tbl: Add AVX512 BF16 instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
2019-04-05 11:03:13 -07:00
Alan Modra
827041555a Update year range in copyright notice of binutils files 2019-01-01 22:06:53 +10:30
Jan Beulich
673fe0f0a7 x86: fold Size{16,32,64} template attributes
Only one of them can be set at a time, which means they can be expressed
by a single 2-bit field instead of three 1-bit ones.
2018-10-10 08:41:52 +02:00
H.J. Lu
6865c0435a x86: Support VEX/EVEX WIG encoding
Add VEXWIG, defined as 3, to indicate that the VEX.W/EVEX.W bit is
ignored by such VEX/EVEX instructions, aka WIG instructions.  Set
VexW=3 on VEX/EVEX WIG instructions.  Update assembler to check
VEXWIG when setting the VEX.W bit.

gas/

	PR gas/23642
	* config/tc-i386.c (build_vex_prefix): Check VEXWIG when setting
	the VEX.W bit.
	(build_evex_prefix): Check VEXWIG when setting the EVEX.W bit.

opcodes/

	PR gas/23642
	* i386-opc.h (VEXWIG): New.
	* i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
	* i386-tbl.h: Regenerated.
2018-09-14 12:20:10 -07:00
Jan Beulich
dbbc8b7e62 x86: use D attribute also for SIMD templates
Various moves come in load and store forms, and just like on the GPR
and FPU sides there would better be only one pattern. In some cases this
is not feasible because the opcodes are too different, but quite a few
cases follow a similar standard scheme. Introduce Opcode_SIMD_FloatD and
Opcode_SIMD_IntD, generalize handling in operand_size_match() (reverse
operand handling there simply needs to match "straight" operand one),
and fix a long standing, but so far only latent bug with when to zap
found_reverse_match.

Also once again drop IgnoreSize where pointlessly applied to templates
touched anyway as well as *word when redundant with Reg*.
2018-09-13 11:07:07 +02:00
H.J. Lu
d871f3f483 x86: Add CpuCMOV and CpuFXSR
There are separate CPUID feature bits for fxsave/fxrstor and cmovCC
instructions.  This patch adds CpuCMOV and CpuFXSR to replace Cpu686
on corresponding instructions.

gas/

	* config/tc-i386.c (cpu_arch): Add .cmov and .fxsr.
	(cpu_noarch): Add nocmov and nofxsr.
	* doc/c-i386.texi: Document cmov and fxsr.

opcodes/

	* i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
	CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
	CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
	(cpu_flags): Add CpuCMOV and CpuFXSR.
	* i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
	fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
2018-08-11 14:37:32 -07:00
Jan Beulich
e968fc9b63 x86: fold RegEip/RegRip and RegEiz/RegRiz
This allows to simplify the code in a number of places.
2018-08-06 08:34:36 +02:00
Jan Beulich
c48dadc9a8 x86: drop "mem" operand type attribute
No template specifies this bit, so there's no point recording it in the
templates. Use a flags[] bit instead.
2018-08-03 09:30:02 +02:00
Jan Beulich
ae2387feae x86: fold various AVX512 templates with so far differing Masking attributes
There's no insn allowing ZEROING_MASKING alone. Re-purpose its value for
handling the not uncommon case of insns allowing either form of masking
with register operands, but only merging masking with a memory operand.
2018-07-31 10:57:09 +02:00
Jan Beulich
e951d5ca3d x86: drop CpuVREX
It is fully redundant with CpuAVX512F.
2018-07-31 10:52:37 +02:00
H.J. Lu
4a1b91eabb x86: Expand Broadcast to 3 bits
Expand Broadcast to 3 bits so that the number of bytes to broadcast
can be computed as 1 << (Broadcast - 1).  Use it to simplify x86
assembler.

gas/

	* config/tc-i386.c (Broadcast_Operation): Add bytes.
	(build_evex_prefix): Use i.broadcast->bytes.
	(match_broadcast_size): New function.
	(check_VecOperands): Use the broadcast field to compute the
	number of bytes to broadcast directly.  Set i.broadcast->bytes.
	Use match_broadcast_size.

opcodes/

	* i386-gen.c (adjust_broadcast_modifier): New function.
	(process_i386_opcode_modifier): Add an argument for operands.
	Adjust the Broadcast value based on operands.
	(output_i386_opcode): Pass operand_types to
	process_i386_opcode_modifier.
	(process_i386_opcodes): Pass NULL as operands to
	process_i386_opcode_modifier.
	* i386-opc.h (BYTE_BROADCAST): New.
	(WORD_BROADCAST): Likewise.
	(DWORD_BROADCAST): Likewise.
	(QWORD_BROADCAST): Likewise.
	(i386_opcode_modifier): Expand broadcast to 3 bits.
	* i386-tbl.h: Regenerated.
2018-07-25 15:28:24 -07:00
Jan Beulich
7091c61201 x86: fold various AVX512VL templates into their AVX512F counterparts 2018-07-19 08:29:35 +02:00
H.J. Lu
11a322db5c x86: Split vcvtps2{,u}qq and vcvttps2{,u}qq
After

commit 1b54b8d7e4
Author: Jan Beulich <jbeulich@novell.com>
Date:   Mon Dec 18 09:36:14 2017 +0100

    x86: fold RegXMM/RegYMM/RegZMM into RegSIMD

    ... qualified by their respective sizes, allowing to drop FirstXmm0 at
    the same time.

folded RegXMM, RegYMM and RegZMM into RegSIMD, it's no longer impossible
to distinguish if Xmmword can represent a memory reference when operand
specification contains SIMD register. For example, template operands
specification like these

RegXMM|...|Xmmword|...

and

RegXMM|...

The Xmmword bitfield is always set by RegXMM which is represented by
"RegSIMD|Xmmword".  This patch splits each of vcvtps2qq, vcvtps2uqq,
vcvttps2qq and vcvttps2uqq into 2 templates: one template only has
RegXMM source operand and the other only has mempry source operand.

gas/

	PR gas/23418
	* testsuite/gas/i386/xmmword.s: Add tests for vcvtps2qq,
	vcvtps2uqq, vcvttps2qq and vcvttps2uqq.
	* testsuite/gas/i386/xmmword.l: Updated.

opcodes/

	PR gas/23418
	* i386-opc.h (Byte): Update comments.
	(Word): Likewise.
	(Dword): Likewise.
	(Fword): Likewise.
	(Qword): Likewise.
	(Tbyte): Likewise.
	(Xmmword): Likewise.
	(Ymmword): Likewise.
	(Zmmword): Likewise.
	* i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
	vcvttps2uqq.
	* i386-tbl.h: Regenerated.
2018-07-18 05:33:50 -07:00
Jan Beulich
f0a85b0706 x86: replace off-by-one OTMax
With its name it should equal to the largest prior enumerator, which is
not very helpful as that will change every once in a while. Rename it to
OTNum instead to make name and value match, and correct use sites to no
longer use one too large a value.
2018-07-11 10:24:44 +02:00
H.J. Lu
c0a30a9f0a Enable Intel MOVDIRI, MOVDIR64B instructions
gas/

	* config/tc-i386.c (cpu_arch): Add .movdir, .movdir64b.
	(cpu_noarch): Likewise.
	(process_suffix): Add check for register size.
	* doc/c-i386.texi: Document movdiri, movdir64b.
	* testsuite/gas/i386/i386.exp: Run MOVDIR{I,64B} tests.
	* testsuite/gas/i386/movdir-intel.d: New file.
	* testsuite/gas/i386/movdir.d: Likewise.
	* testsuite/gas/i386/movdir.s: Likewise.
	* testsuite/gas/i386/movdir64b-reg.s: Likewise.
	* testsuite/gas/i386/movdir64b-reg.l: Likewise.
	* testsuite/gas/i386/x86-64-movdir-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-movdir.d: Likewise.
	* testsuite/gas/i386/x86-64-movdir.s: Likewise.
	* testsuite/gas/i386/x86-64-movdir64b-reg.s: Likewise.
	* testsuite/gas/i386/x86-64-movdir64b-reg.l: Likewise.

opcodes/

	* i386-dis.c (Gva): New.
	(enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
	MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
	(prefix_table): New instructions (see prefix above).
	(mod_table): New instructions (see prefix above).
	(OP_G): Handle va_mode.
	* i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
	CPU_MOVDIR64B_FLAGS.
	(cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
	* i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
	(i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
	* i386-opc.tbl: Add movidir{i,64b}.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
2018-05-07 16:57:48 -07:00
H.J. Lu
75c0a43899 x86: Replace AddrPrefixOp0 with AddrPrefixOpReg
This patch replaces AddrPrefixOp0 with AddrPrefixOpReg to indicate that
the size of register operand is controlled by the address size prefix.
This will be used by Intel MOVDIRI and MOVDIR64B instructions later.

gas/

	* config/tc-i386.c (process_suffix): Check addrprefixopreg
	instead of addrprefixop0.

opcodes/

	* i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
	AddrPrefixOpReg.
	* i386-opc.h (AddrPrefixOp0): Renamed to ...
	(AddrPrefixOpReg): This.
	(i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
	* i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
2018-05-07 09:57:06 -07:00
Igor Tsimbalist
aa17843739 Revert "Enable Intel MOVDIRI, MOVDIR64B instructions."
This reverts commit a914a7c958.
2018-04-27 14:34:13 +02:00
Igor Tsimbalist
a914a7c958 Enable Intel MOVDIRI, MOVDIR64B instructions.
gas/
	* config/tc-i386.c (cpu_arch): Add .movdir, .movdir64b.
	(cpu_noarch): Likewise.
	(process_suffix): Add check for register size.
	* doc/c-i386.texi: Document movdiri, movdir64b.
	* testsuite/gas/i386/i386.exp: Run MOVDIR{I,64B} tests.
	* testsuite/gas/i386/movdir-intel.d: New test.
	* testsuite/gas/i386/movdir.d: Likewise.
	* testsuite/gas/i386/movdir.s: Likewise.
	* testsuite/gas/i386/movdir64b-reg.s: Likewise.
	* testsuite/gas/i386/movdir64b-reg.l: Likewise.
	* testsuite/gas/i386/x86-64-movdir-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-movdir.d: Likewise.
	* testsuite/gas/i386/x86-64-movdir.s: Likewise.
	* testsuite/gas/i386/x86-64-movdir64b-reg.s: Likewise.
	* testsuite/gas/i386/x86-64-movdir64b-reg.l: Likewise.

opcodes/
	* i386-dis.c (enum): Add PREFIX_0F38F8, PREFIX_0F38F9.
	(prefix_table): New instructions (see prefix above).
	Add Gva macro and handling in OP_G.
	* i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
	CPU_MOVDIR64B_FLAGS.
	(cpu_flags): Likewise.
	(opcode_modifiers): Add AddrPrefixOpReg.
	(i386_opcode_modifier): Likewise.
	* i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
	(i386_cpu_flags): Likewise.
	* i386-opc.tbl: Add movidir{i,64b}.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.
2018-04-26 23:34:04 +02:00
Jan Beulich
6e041cf4b0 x86: drop CpuRegMMX, CpuReg[XYZ]MM, and CpuRegMask
It's not clear to me why they had been introduced - the respective
comments in opcodes/i386-gen.c are certainly wrong: ymm<N> registers
are very well supported (and necessary) with just AVX512F.
2018-04-26 08:48:01 +02:00
Jan Beulich
2f1bada2dc x86: drop VexImmExt
It's only used in assertions, and hence not really needed for correct
code generation.
2018-04-26 08:30:06 +02:00
Igor Tsimbalist
c48935d75f Enable Intel CLDEMOTE instruction.
gas/
	* config/tc-i386.c (cpu_arch): Add .cldemote.
	* doc/c-i386.texi: Document cldemote/.cldemote.
	* testsuite/gas/i386/cldemote-intel.d: New.
	* testsuite/gas/i386/cldemote.d: Likewise.
	* testsuite/gas/i386/cldemote.s: Likewise.
	* testsuite/gas/i386/i386.exp: Run new tests.
	* testsuite/gas/i386/x86-64-cldemote-intel.d: New.
	* testsuite/gas/i386/x86-64-cldemote.d: Likewise.
	* testsuite/gas/i386/x86-64-cldemote.s: Likewise.
	* testsuite/gas/i386/ilp32/x86-64-nops.d: Remove 0x0f1c
	NOP encoding that maps to cldemote.
	* testsuite/gas/i386/nops.d: Likewise.
	* testsuite/gas/i386/nops.s: Likewise.
	* testsuite/gas/i386/x86-64-nops.d: Likewise.
	* testsuite/gas/i386/x86-64-nops.s: Likewise.

opcode/
	* i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
	PREFIX_0F1C.
	* i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
	(cpu_flags): Add CpuCLDEMOTE.
	* i386-init.h: Regenerate.
	* i386-opc.h (enum): Add CpuCLDEMOTE,
	(i386_cpu_flags): Add cpucldemote.
	* i386-opc.tbl: Add cldemote.
	* i386-tbl.h: Regenerate.
2018-04-17 11:56:34 +02:00