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2185 Commits
| Author | SHA1 | Message | Date | |
|---|---|---|---|---|
John Baldwin
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0b9305edf1 |
Recognize the recently-added FreeBSD core dump note for LWP info.
This core dump note contains the same information returned by the ptrace PT_LWPINFO operation for each LWP belonging to a process. binutils/ChangeLog: * readelf.c (get_freebsd_elfcore_note_type): Handle NT_FREEBSD_PTLWPINFO. include/ChangeLog: * elf/common.h (NT_FREEBSD_PTLWPINFO): Define. |
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Jan Kratochvil
|
de837d77bc |
Import include/+libiberty/ r249883 from upstream GCC.
include/ChangeLog 2017-07-02 Jan Kratochvil <jan.kratochvil@redhat.com> * dwarf2.def (DW_IDX_compile_unit, DW_IDX_type_unit, DW_IDX_die_offset) (DW_IDX_parent, DW_IDX_type_hash, DW_IDX_lo_user, DW_IDX_hi_user) (DW_IDX_GNU_internal, DW_IDX_GNU_external): New. * dwarf2.h (DW_IDX, DW_IDX_DUP, DW_FIRST_IDX, DW_END_IDX): New. (enum dwarf_name_index_attribute): Remove. (get_DW_IDX_name): New declaration. libiberty/ChangeLog 2017-07-02 Jan Kratochvil <jan.kratochvil@redhat.com> * dwarfnames.c (DW_FIRST_IDX, DW_END_IDX, DW_IDX, DW_IDX_DUP): New. |
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Georg-Johann Lay
|
32f76c6773 |
Add support for a __gcc_isr pseudo isntruction to the AVR assembler.
PR gas/21683
include * opcode/avr.h (AVR_INSN): Add one for __gcc_isr.
gas * doc/c-avr.texi (AVR Options) <-mgcc-isr>: Document it.
(AVR Pseudo Instructions): New node.
* config/tc-avr.h (md_pre_output_hook): Define to avr_pre_output_hook.
(md_undefined_symbol): Define to avr_undefined_symbol.
(avr_pre_output_hook, avr_undefined_symbol): New protos.
* config/tc-avr.c (struc-symbol.h): Include it.
(ISR_CHUNK_Done, ISR_CHUNK_Prologue, ISR_CHUNK_Epilogue): New enums.
(avr_isr, avr_gccisr_opcode)
(avr_no_sreg_hash, avr_no_sreg): New static variables.
(avr_opt_s) <have_gccisr>: Add field.
(avr_opt): Add initializer for have_gccisr.
(enum options) <OPTION_HAVE_GCCISR>: Add enum.
(md_longopts) <"mgcc-isr">: Add entry.
(md_show_usage): Document -mgcc-isr.
(md_parse_option) [OPTION_HAVE_GCCISR]: Handle it.
(md_undefined_symbol): Remove.
(avr_undefined_symbol, avr_pre_output_hook): New fuctions.
(md_begin) <avr_no_sreg_hash, avr_gccisr_opcode>: Initialize them.
(avr_operand) <pregno>: Add argument and set *pregno if function
is called for a register constraint.
[N]: Handle constraint.
(avr_operands) <avr_operand>: Pass 5th parameter to calls.
[avr_opt.have_gccisr]: Call avr_update_gccisr. Call
avr_gccisr_operands instead of avr_operands.
(avr_update_gccisr, avr_emit_insn, avr_patch_gccisr_frag)
(avr_gccisr_operands, avr_check_gccisr_done): New static functions.
* testsuite/gas/avr/gccisr-01.d: New test.
* testsuite/gas/avr/gccisr-01.s: New test.
* testsuite/gas/avr/gccisr-02.d: New test.
* testsuite/gas/avr/gccisr-02.s: New test.
* testsuite/gas/avr/gccisr-03.d: New test.
* testsuite/gas/avr/gccisr-03.s: New test.
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Maciej W. Rozycki
|
9785fc2a4d |
MIPS: Fix XPA base and Virtualization ASE instruction handling
Correct a commit
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Andreas Arnez
|
88ab90e860 |
S390: Support guarded-storage core note sections
Newer Linux kernel versions offer two new register sets in support of the z/Architecture's guarded storage facility: NT_S390_GS_CB, the "guarded-storage registers", and NT_S390_GS_BC, the "guarded-storage broadcast control block". This patch adds support for the respective core notes sections to binutils. bfd/ChangeLog: * elf-bfd.h (elfcore_write_s390_gs_cb): Add prototype. (elfcore_write_s390_gs_bc): Likewise. * elf.c (elfcore_grok_s390_gs_cb): New function. (elfcore_grok_s390_gs_bc): New function. (elfcore_grok_note): Call them. (elfcore_write_s390_gs_cb): New function. (elfcore_write_s390_gs_bc): New function. (elfcore_write_register_note): Call them. binutils/ChangeLog: * readelf.c (get_note_type): Add NT_S390_GS_CB and NT_S390_GS_BC. include/ChangeLog: * elf/common.h (NT_S390_GS_CB): New macro. (NT_S390_GS_BC): Likewise. |
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Tamar Christina
|
65a55fbbd9 |
[AArch64] Add dot product support for AArch64 to binutils
gas/ * config/tc-aarch64.c (aarch64_reg_parse_32_64): Accept 4B. (aarch64_features): Added dotprod. * doc/c-aarch64.texi: Added dotprod. * testsuite/gas/aarch64/dotproduct.d: New. * testsuite/gas/aarch64/dotproduct.s: New. opcodes/ * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod. * aarch64-dis.c (aarch64_ext_reglane): Likewise. * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New. (aarch64_feature_dotprod, DOT_INSN): New. (udot, sdot): New. * aarch64-dis-2.c: Regenerated. include/ * opcode/aarch64.h: (AARCH64_FEATURE_DOTPROD): New. (aarch64_insn_class): Added dotprod. |
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Jiong Wang
|
c604a79ad4 |
[ARM] Assembler and disassembler support Dot Product Extension
This patch add assembler and disassembler support for new Dot Product Extension. The support can be enabled through the new "+dotprod" extension. include/ * opcode/arm.h (FPU_NEON_EXT_DOTPROD): New macro. (FPU_ARCH_DOTPROD_NEON_VFP_ARMV8): New macro. gas/ * config/tc-arm.c (fpu_neon_ext_dotprod): New variable. (neon_scalar_for_mul): Improve comments. (do_neon_dotproduct): New function to encode Dot Product instructions. (do_neon_dotproduct_s): Wrapper function for signed Dot Product instructions. (do_neon_dotproduct_u): Wrapper function for unsigned Dot Product instructions. (insns): New entries for vsdot and vudot. (arm_extensions): New entry for "dotprod". * doc/c-arm.texi: Document new "dotprod" extension. * testsuite/gas/arm/dotprod.s: New test source. * testsuite/gas/arm/dotprod-illegal.s: New test source. * testsuite/gas/arm/dotprod.d: New test. * testsuite/gas/arm/dotprod-thumb2.d: New test. * testsuite/gas/arm/dotprod-illegal.d: New test. * testsuite/gas/arm/dotprod-legacy-arch.d: New test. * testsuite/gas/arm/dotprod-illegal.l: New error file. * testsuite/gas/arm/dotprod-legacy-arch.l: New error file. opcodes/ * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot. |
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Maciej W. Rozycki
|
38bf472a15 |
MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor support
Add support for the Imagination interAptiv MR2 MIPS32r3 processor with
the MIPS16e2 ASE as per documentation, including in particular:
1. Support for implementation-specific interAptiv MR2 COPYW and UCOPYW
MIPS16e2 instructions[1], for assembly and disassembly,
2. Support for implementation-specific interAptiv MR2 SAVE and RESTORE
regular MIPS instructions[2], for assembly and disassembly,
3. ELF binary file annotation for the interAptiv MR2 MIPS architecture
extension.
4. Support for interAptiv MR2 architecture selection for assembly, in
the form of the `-march=interaptiv-mr2' command-line option and its
corresponding `arch=interaptiv-mr2' setting for the `.set' and
`.module' pseudo-ops.
5. Support for interAptiv MR2 architecture selection for disassembly,
in the form of the `mips:interaptiv-mr2' target architecture, for
use e.g. with the `-m' command-line option for `objdump'.
Parts of this change by Matthew Fortune and Andrew Bennett.
References:
[1] "MIPS32 interAptiv Multiprocessing System Software User's Manual",
Imagination Technologies Ltd., Document Number: MD00904, Revision
02.01, June 15, 2016, Section 24.3 "MIPS16e2 Implementation Specific
Instructions", pp. 878-883
[2] same, Chapter 25 "Implementation-specific Instructions", pp. 911-917
include/
* elf/mips.h (E_MIPS_MACH_IAMR2): New macro.
(AFL_EXT_INTERAPTIV_MR2): Likewise.
* opcode/mips.h: Document new operand codes defined.
(INSN_INTERAPTIV_MR2): New macro.
(INSN_CHIP_MASK): Adjust accordingly.
(CPU_INTERAPTIV_MR2): New macro.
(cpu_is_member) <CPU_INTERAPTIV_MR2>: New case.
(MIPS16_ALL_ARGS): Rename to...
(MIPS_SVRS_ALL_ARGS): ... this.
(MIPS16_ALL_STATICS): Rename to...
(MIPS_SVRS_ALL_STATICS): ... this.
bfd/
* archures.c (bfd_mach_mips_interaptiv_mr2): New macro.
* cpu-mips.c (I_interaptiv_mr2): New enum value.
(arch_info_struct): Add "mips:interaptiv-mr2" entry.
* elfxx-mips.c (_bfd_elf_mips_mach) <E_MIPS_MACH_IAMR2>: New
case.
(mips_set_isa_flags) <bfd_mach_mips_interaptiv_mr2>: Likewise.
(bfd_mips_isa_ext) <bfd_mach_mips_interaptiv_mr2>: Likewise.
(print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise.
(mips_mach_extensions): Add `bfd_mach_mipsisa32r3' and
`bfd_mach_mips_interaptiv_mr2' entries.
* bfd-in2.h: Regenerate.
opcodes/
* mips-formats.h (INT_BIAS): New macro.
(INT_ADJ): Redefine in INT_BIAS terms.
* mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
(mips_print_save_restore): New function.
(print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
(validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
call.
(print_insn_args): Handle OP_SAVE_RESTORE_LIST.
(print_mips16_insn_arg): Call `mips_print_save_restore' for
OP_SAVE_RESTORE_LIST handling, factored out from here.
* mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
(RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
(mips_builtin_opcodes): Add "restore" and "save" entries.
* mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
(IAMR2): New macro.
(mips16_opcodes): Add "copyw" and "ucopyw" entries.
binutils/
* readelf.c (get_machine_flags) <E_MIPS_MACH_IAMR2>: New case.
(print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise.
* NEWS: Mention Imagination interAptiv MR2 processor support.
gas/
* config/tc-mips.c (validate_mips_insn): Handle
OP_SAVE_RESTORE_LIST specially.
(mips_encode_save_restore, mips16_encode_save_restore): New
functions.
(match_save_restore_list_operand): Factor out SAVE/RESTORE
operand insertion into the instruction word or halfword to these
new functions.
(mips_cpu_info_table): Add "interaptiv-mr2" entry.
* doc/c-mips.texi (MIPS Options): Add `interaptiv-mr2' to the
`-march=' argument list.
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Kuan-Lin Chen
|
a6cbf936e3 |
RISC-V: Use pc-relative relocation for FDE initial location
The symbol address in .eh_frame may be adjusted in _bfd_elf_discard_section_eh_frame, and the content of .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame. Therefore, we cannot insert a relocation whose addend symbol is in .eh_frame. Othrewise, the value may be adjusted twice. bfd/ChangeLog 2017-06-26 Kuan-Lin Chen <rufus@andestech.com> * elfnn-riscv.c (perform_relocation): Support the new R_RISCV_32_PCREL relocation. (riscv_elf_relocate_section): Likewise. * elfxx-riscv.c (howto_table): Likewise. (riscv_reloc_map): Likewise. * bfd-in2.h (BFD_RELOC_RISCV_32_PCREL): New relocation. * libbfd.h: Regenerate. gas/ChangeLog 2017-06-26 Kuan-Lin Chen <rufus@andestech.com> * config/tc-riscv.c (md_apply_fix) [BFD_RELOC_32]: Convert to a R_RISCV_32_PCREL relocation. include/ChangeLog 2017-06-26 Kuan-Lin Chen <rufus@andestech.com> * elf/riscv.h (R_RISCV_32_PCREL): New. |
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Andreas Krebbel
|
fd52715cfa | Add pgste marker changelog | ||
Thomas Preud'homme
|
ced40572e4 |
[ARM] Add support for ARMv8-R in assembler and readelf
=== Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to add support for ARMv8-R in GAS: instructions, build attributes and readelf. === Patch description === Although some differences exist for system registers, from GAS point of view ARMv8-R supports the same instructions as ARMv8-A Aarch32 state and a subset of its extensions. This patch therefore introduce a new feature bit to distinguish the availability of the pan, ras and rdma extensions between ARMv8-A and ARMv8-R and allow crypto, fp and simd extensions to be used by ARMv8-R. Most of the changes are then in the testsuite to (i) rename source files and error output to be shared between ARMv8-A and ARMv8-R, (ii) rename files with expected output for ARMv8-A build attributes and (iii) add new files with expected output for ARMv8-R build attributes. 2017-06-24 Thomas Preud'homme <thomas.preudhomme@arm.com> binutils/ * readelf.c (arm_attr_tag_CPU_arch): Fill value for ARMv8-R. gas/ * NEWS: Mention support for ARMv8-R architecture. * config/tc-arm.c (arm_archs): Add entry for ARMv8-R. (arm_extensions): Restrict pan, ras and rdma extension to ARMv8-A and make crypto, fp and simd extensions available to ARMv8-R. (cpu_arch_ver): Add entry for ARMv8-R. (aeabi_set_public_attributes): Update gas_assert for Tag_DIV_use logic. * testsuite/gas/arm/armv8-a+fp.s: Rename into ... * testsuite/gas/arm/armv8-ar+fp.s: This. Remove .arch directive. * testsuite/gas/arm/armv8-a+fp.d: Specify source to assemble and architecture to assemble for. * testsuite/gas/arm/armv8-r+fp.d: New. * testsuite/gas/arm/armv8-a+simd.s: Rename into ... * testsuite/gas/arm/armv8-ar+simd.s: This. Remove .arch directive. * testsuite/gas/arm/armv8-a+simd.d: Specify source to assemble and architecture to assemble for. * testsuite/gas/arm/armv8-r+simd.d: New. * testsuite/gas/arm/armv8-a-bad.s: Rename into ... * testsuite/gas/arm/armv8-ar-bad.s: This. Remove .arch directive. * testsuite/gas/arm/armv8-a-bad.l: Rename into ... * testsuite/gas/arm/armv8-ar-bad.l: This. Decrement line number by 1. * testsuite/gas/arm/armv8-a-bad.d: Specify source to assemble, architecture to assemble for and adjust error output file. * testsuite/gas/arm/armv8-r-bad.d: New. * testsuite/gas/arm/armv8-a-barrier.s: Rename into ... * testsuite/gas/arm/armv8-ar-barrier.s: This. * testsuite/gas/arm/armv8-a-barrier-arm.d: Adjust source. * testsuite/gas/arm/armv8-a-barrier-thumb.d: Likewise. * testsuite/gas/arm/armv8-r-barrier-arm.d: New. * testsuite/gas/arm/armv8-r-barrier-thumb.d: New. * testsuite/gas/arm/armv8-a-it-bad.s: Rename into ... * testsuite/gas/arm/armv8-ar-it-bad.s: This. Remove .arch directive. * testsuite/gas/arm/armv8-a-it-bad.l: Rename into ... * testsuite/gas/arm/armv8-ar-it-bad.l: This. Decrement line number by 1. * testsuite/gas/arm/armv8-a-it-bad.d: Specify source to assemble, architecture to assemble for and adjust error output file. * testsuite/gas/arm/armv8-r-it-bad.d: New. * testsuite/gas/arm/armv8-a.s: Rename into ... * testsuite/gas/arm/armv8-ar.s: This. Remove .arch directive. * testsuite/gas/arm/armv8-a.d: Specify source to assemble and architecture to assemble for. * testsuite/gas/arm/armv8-r.d: New. * testsuite/gas/arm/attr-march-armv8-r+crypto.d: New. * testsuite/gas/arm/attr-march-armv8-r+fp.d: New. * testsuite/gas/arm/attr-march-armv8-r+simd.d: New. * testsuite/gas/arm/attr-march-armv8-r.d: New. * testsuite/gas/arm/crc32.s: Rename into ... * testsuite/gas/arm/crc32-armv8-ar.s: This. * testsuite/gas/arm/crc32.d: Rename into ... * testsuite/gas/arm/crc32-armv8-a.d: This. Specify source to assemble. * testsuite/gas/arm/crc32-armv8-r.d: New. * testsuite/gas/arm/crc32-bad.s: Rename into ... * testsuite/gas/arm/crc32-armv8-ar-bad.s: This. * testsuite/gas/arm/crc32-bad.d: Rename into ... * testsuite/gas/arm/crc32-armv8-a-bad.d: This. Specify source to assemble. * testsuite/gas/arm/crc32-armv8-r-bad.d: New. * testsuite/gas/arm/mask_1.s: Rename into ... * testsuite/gas/arm/mask_1-armv8-ar.s: This. * testsuite/gas/arm/mask_1.d: Rename into ... * testsuite/gas/arm/mask_1-armv8-a.d: This. Specify source to assemble. * testsuite/gas/arm/mask_1-armv8-r.d: new. include/ * elf/arm.h (TAG_CPU_ARCH_V8R): New macro. * opcode/arm.h (ARM_EXT2_V8A): New macro. (ARM_AEXT2_V8A): Rename into ... (ARM_AEXT2_V8AR): This. (ARM_AEXT2_V8A): New macro. (ARM_AEXT_V8R): New macro. (ARM_AEXT2_V8R): New macro. (ARM_ARCH_V8R): New macro. |
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Thomas Preud'homme
|
173205ca33 |
[ARM] Remove ARMv6S-M special casing
=== Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to remove special casing for ARMv6S-M autodetection. === Motivation === Currently, SWI and SVC mnemonics are enabled for ARMv4T and successor architectures with extra checks in the handler function (do_t_swi) to give an error message when ARMv6-M is targeted and some more special casing in aeabi_set_public_attributes. This was made to exclude these mnemonics for ARMv6-M unless the OS extension is in use. However this logic is superfluous: there is already code to check whether an instruction is available based on the feature bit it is part of and whether the targeted architecture has that feature bit. This patch aims at removing that unneeded complexity. === Patch description === The OS extension is already limited to the ARMv6-M architecture so all this patch does is redefined availability of the ARM_EXT_OS feature bit to not be present for ARM_ARCH_V6M. ARM_ARCH_V6SM does not need any change either because it already includes ARM_EXT_OS. The patch also make sure that the error message that was given by do_t_swi when SWI/SVC is unavailable is still the same by detecting the situation in md_assemble. 2017-06-24 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (arm_ext_v6m): Delete. (arm_ext_v7m): Delete. (arm_ext_m): Remove ARM_EXT_OS from the set of feature defined M profile. (arm_arch_v6m_only): Delete. (do_t_swi): Remove special case for ARMv6S-M. (md_assemble): Display error message previously in do_t_swi when SVC is not available. (insns): Guard swi and svc by arm_ext_os for Thumb mode. (aeabi_set_public_attributes): Remove special case for ARMv6S-M. include/ * opcode/arm.h (ARM_AEXT_V4TxM): Add ARM_EXT_OS bit to the set. (ARM_AEXT_V4T): Likewise. (ARM_AEXT_V5TxM): Likewise. (ARM_AEXT_V5T): Likewise. (ARM_AEXT_V6M): Mask off ARM_EXT_OS bit. |
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|
Andreas Krebbel
|
b4cbbe8f72 |
S/390: Add support for pgste marker
This patch adds a new S/390 specific segment type: PT_S390_PGSTE. For binaries marked with that segment the kernel will allocate 4k page tables. The only user so far will be qemu. ld/ChangeLog: 2017-06-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * Makefile.in: Add s390.em as build dependency. * emulparams/elf64_s390.sh (EXTRA_EM_FILE): Add s390.em. * emultempl/s390.em: New file. * gen-doc.texi: Add documentation for --s390-pgste option. * ld.texinfo: Likewise. include/ChangeLog: 2017-06-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * elf/s390.h (PT_S390_PGSTE): Define macro. binutils/ChangeLog: 2017-06-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * readelf.c (get_s390_segment_type): Add support for the new segment type PT_S390_PGSTE. (get_segment_type): Call get_s390_segment_type. elfcpp/ChangeLog: 2017-06-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * elfcpp.h (enum PT): Add PT_S390_PGSTE to enum. bfd/ChangeLog: 2017-06-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * elf-s390.h: New file. * elf64-s390.c (struct elf_s390_link_hash_table): Add params field. (elf_s390_additional_program_headers): New function. (elf_s390_modify_segment_map): New function. (bfd_elf_s390_set_options): New function. (elf_backend_additional_program_headers) (elf_backend_modify_segment_map): Add macro definitions. |
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H.J. Lu
|
48580982ef |
x86: Support Intel Shadow Stack with SHSTK property
To support Intel Shadow Stack (SHSTK) in Intel Control-flow Enforcement Technology (CET) instructions: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf #define GNU_PROPERTY_X86_FEATURE_1_SHSTK (1U << 1) is added to GNU program properties to indicate that all executable sections are compatible with SHSTK where return address popped from shadow stack always matches return address popped from normal stack. GNU_PROPERTY_X86_FEATURE_1_SHSTK is set on output only if it is set on all relocatable inputs. bfd/ * elf32-i386.c (elf_i386_merge_gnu_properties): If info->shstk is set, turn on GNU_PROPERTY_X86_FEATURE_1_SHSTK. (elf_i386_link_setup_gnu_properties): If info->shstk is set, turn on GNU_PROPERTY_X86_FEATURE_1_IBT. * elf64-x86-64.c (elf_x86_64_merge_gnu_properties): If info->shstk is set, turn on GNU_PROPERTY_X86_FEATURE_1_SHSTK. (elf_x86_64_link_setup_gnu_properties): If info->shstk is set, turn on GNU_PROPERTY_X86_FEATURE_1_IBT. binutils/ * readelf.c (decode_x86_feature): Decode GNU_PROPERTY_X86_FEATURE_1_SHSTK. * testsuite/binutils-all/i386/shstk.d: New file. * testsuite/binutils-all/i386/shstk.s: Likewise. * testsuite/binutils-all/x86-64/shstk-x32.d: Likewise. * testsuite/binutils-all/x86-64/shstk.d: Likewise. * testsuite/binutils-all/x86-64/shstk.s: Likewise. include/ * bfdlink.h (bfd_link_info): Add shstk. * elf/common.h (GNU_PROPERTY_X86_FEATURE_1_SHSTK): New. ld/ * NEWS: Mention -z shstk and GNU_PROPERTY_X86_FEATURE_1_SHSTK. * emulparams/cet.sh (PARSE_AND_LIST_OPTIONS_CET): Add "-z shstk". (PARSE_AND_LIST_ARGS_CASE_Z_CET): Support "-z shstk". * ld.texinfo: Document -z shstk. * testsuite/ld-i386/i386.exp: Run SHSTK tests. * testsuite/ld-x86-64/x86-64.exp: Likewise. * testsuite/ld-i386/property-x86-shstk.s: New file. * testsuite/ld-i386/property-x86-shstk1a.d: Likewise. * testsuite/ld-i386/property-x86-shstk1b.d: Likewise. * testsuite/ld-i386/property-x86-shstk2.d: Likewise. * testsuite/ld-i386/property-x86-shstk3a.d: Likewise. * testsuite/ld-i386/property-x86-shstk3b.d: Likewise. * testsuite/ld-i386/property-x86-shstk4.d: Likewise. * testsuite/ld-i386/property-x86-shstk5.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk.s: Likewise. * testsuite/ld-x86-64/property-x86-shstk1a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk1a.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk1b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk1b.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk2-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk2.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3a.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3b.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk4-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk4.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk5-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk5.d: Likewise. |
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H.J. Lu
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ee2fdd6f36 |
x86: Support Intel IBT with IBT property and IBT-enable PLT
To support IBT in Intel Control-flow Enforcement Technology (CET) instructions: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf #define GNU_PROPERTY_X86_FEATURE_1_AND 0xc0000002 #define GNU_PROPERTY_X86_FEATURE_1_IBT (1U << 0) are added to GNU program properties to indicate that all executable sections are compatible with IBT when ENDBR instruction starts each valid target where an indirect branch instruction can land. GNU_PROPERTY_X86_FEATURE_1_IBT is set on output only if it is set on all relocatable inputs. The followings changes are made to the Procedure Linkage Table (PLT): 1. For 64-bit x86-64, PLT is changed to PLT0: push GOT[1] bnd jmp *GOT[2] nop ... PLTn: endbr64 push namen_reloc_index bnd jmp PLT0 together with the second PLT section: PLTn: endbr64 bnd jmp *GOT[namen_index] nop BND prefix is also added so that IBT-enabled PLT is compatible with MPX. 2. For 32-bit x86-64 (x32) and i386, PLT is changed to PLT0: push GOT[1] jmp *GOT[2] nop ... PLTn: endbr64 # endbr32 for i386. push namen_reloc_index jmp PLT0 together with the second PLT section: PLTn: endbr64 # endbr32 for i386. jmp *GOT[namen_index] nop BND prefix isn't used since MPX isn't supported on x32 and BND registers aren't used in parameter passing on i386. GOT is an array of addresses. Initially, GOT[namen_index] is filled with the address of the ENDBR instruction of the corresponding entry in the first PLT section. The function, namen, is called via the ENDBR instruction in the second PLT entry. GOT[namen_index] is updated to the actual address of the function, namen, at run-time. 2 linker command line options are added: 1. -z ibtplt: Generate IBT-enabled PLT. 2. -z ibt: Generate GNU_PROPERTY_X86_FEATURE_1_IBT in GNU program properties as well as IBT-enabled PLT. bfd/ * elf32-i386.c (elf_i386_lazy_ibt_plt0_entry): New. (elf_i386_lazy_ibt_plt_entry): Likewise. (elf_i386_pic_lazy_ibt_plt0_entry): Likewise. (elf_i386_non_lazy_ibt_plt_entry): Likewise. (elf_i386_pic_non_lazy_ibt_plt_entry): Likewise. (elf_i386_eh_frame_lazy_ibt_plt): Likewise. (elf_i386_lazy_plt_layout): Likewise. (elf_i386_non_lazy_plt_layout): Likewise. (elf_i386_link_hash_entry): Add plt_second. (elf_i386_link_hash_table): Add plt_second and plt_second_eh_frame. (elf_i386_allocate_dynrelocs): Use the second PLT if needed. (elf_i386_size_dynamic_sections): Use .plt.got unwind info for the second PLT. Check the second PLT. (elf_i386_relocate_section): Use the second PLT to resolve PLT reference if needed. (elf_i386_finish_dynamic_symbol): Fill and use the second PLT if needed. (elf_i386_finish_dynamic_sections): Set sh_entsize on the second PLT. Generate unwind info for the second PLT. (elf_i386_plt_type): Add plt_second. (elf_i386_get_synthetic_symtab): Support the second PLT. (elf_i386_parse_gnu_properties): Support GNU_PROPERTY_X86_FEATURE_1_AND. (elf_i386_merge_gnu_properties): Support GNU_PROPERTY_X86_FEATURE_1_AND. If info->ibt is set, turn on GNU_PROPERTY_X86_FEATURE_1_IBT (elf_i386_link_setup_gnu_properties): If info->ibt is set, turn on GNU_PROPERTY_X86_FEATURE_1_IBT. Use IBT-enabled PLT for info->ibtplt, info->ibt or GNU_PROPERTY_X86_FEATURE_1_IBT is set on all relocatable inputs. * elf64-x86-64.c (elf_x86_64_lazy_ibt_plt_entry): New. (elf_x32_lazy_ibt_plt_entry): Likewise. (elf_x86_64_non_lazy_ibt_plt_entry): Likewise. (elf_x32_non_lazy_ibt_plt_entry): Likewise. (elf_x86_64_eh_frame_lazy_ibt_plt): Likewise. (elf_x32_eh_frame_lazy_ibt_plt): Likewise. (elf_x86_64_lazy_ibt_plt): Likewise. (elf_x32_lazy_ibt_plt): Likewise. (elf_x86_64_non_lazy_ibt_plt): Likewise. (elf_x32_non_lazy_ibt_plt): Likewise. (elf_x86_64_get_synthetic_symtab): Support the second PLT. (elf_x86_64_parse_gnu_properties): Support GNU_PROPERTY_X86_FEATURE_1_AND. (elf_x86_64_merge_gnu_properties): Support GNU_PROPERTY_X86_FEATURE_1_AND. If info->ibt is set, turn on GNU_PROPERTY_X86_FEATURE_1_IBT (elf_x86_64_link_setup_gnu_properties): If info->ibt is set, turn on GNU_PROPERTY_X86_FEATURE_1_IBT. Use IBT-enabled PLT for info->ibtplt, info->ibt or GNU_PROPERTY_X86_FEATURE_1_IBT is set on all relocatable inputs. binutils/ * readelf.c (decode_x86_feature): New. (print_gnu_property_note): Call decode_x86_feature on GNU_PROPERTY_X86_FEATURE_1_AND. * testsuite/binutils-all/i386/empty.d: New file. * testsuite/binutils-all/i386/empty.s: Likewise. * testsuite/binutils-all/i386/ibt.d: Likewise. * testsuite/binutils-all/i386/ibt.s: Likewise. * testsuite/binutils-all/x86-64/empty-x32.d: Likewise. * testsuite/binutils-all/x86-64/empty.d: Likewise. * testsuite/binutils-all/x86-64/empty.s: Likewise. * testsuite/binutils-all/x86-64/ibt-x32.d: Likewise. * testsuite/binutils-all/x86-64/ibt.d: Likewise. * testsuite/binutils-all/x86-64/ibt.s: Likewise. include/ * bfdlink.h (bfd_link_info): Add ibtplt and ibt. * elf/common.h (GNU_PROPERTY_X86_FEATURE_1_AND): New. (GNU_PROPERTY_X86_FEATURE_1_IBT): Likewise. ld/ * Makefile.am (ELF_X86_DEPS): Add $(srcdir)/emulparams/cet.sh. * Makefile.in: Regenerated. * NEWS: Mention GNU_PROPERTY_X86_FEATURE_1_IBT, -z ibtplt and -z ibt. * emulparams/cet.sh: New file. * testsuite/ld-i386/ibt-plt-1.d: Likewise. * testsuite/ld-i386/ibt-plt-1.s: Likewise. * testsuite/ld-i386/ibt-plt-2.s: Likewise. * testsuite/ld-i386/ibt-plt-2a.d: Likewise. * testsuite/ld-i386/ibt-plt-2b.d: Likewise. * testsuite/ld-i386/ibt-plt-2c.d: Likewise. * testsuite/ld-i386/ibt-plt-2d.d: Likewise. * testsuite/ld-i386/ibt-plt-3.s: Likewise. * testsuite/ld-i386/ibt-plt-3a.d: Likewise. * testsuite/ld-i386/ibt-plt-3b.d: Likewise. * testsuite/ld-i386/ibt-plt-3c.d: Likewise. * testsuite/ld-i386/ibt-plt-3d.d: Likewise. * testsuite/ld-i386/plt-main-ibt.dd: Likewise. * testsuite/ld-i386/plt-pie-ibt.dd: Likewise. * testsuite/ld-i386/property-x86-empty.s: Likewise. * testsuite/ld-i386/property-x86-ibt.s: Likewise. * testsuite/ld-i386/property-x86-ibt1a.d: Likewise. * testsuite/ld-i386/property-x86-ibt1b.d: Likewise. * testsuite/ld-i386/property-x86-ibt2.d: Likewise. * testsuite/ld-i386/property-x86-ibt3a.d: Likewise. * testsuite/ld-i386/property-x86-ibt3b.d: Likewise. * testsuite/ld-i386/property-x86-ibt4.d: Likewise. * testsuite/ld-i386/property-x86-ibt5.d: Likewise. * testsuite/ld-x86-64/ibt-plt-1-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-1.d: Likewise. * testsuite/ld-x86-64/ibt-plt-1.s: Likewise. * testsuite/ld-x86-64/ibt-plt-2.s: Likewise. * testsuite/ld-x86-64/ibt-plt-2a-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2a.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2b-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2b.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2c-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2c.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2d-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2d.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3.s: Likewise. * testsuite/ld-x86-64/ibt-plt-3a-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3a.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3b-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3b.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3c-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3c.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3d-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3d.d: Likewise. * testsuite/ld-x86-64/plt-main-ibt-now.rd: Likewise. * testsuite/ld-x86-64/plt-main-ibt-x32.dd: Likewise. * testsuite/ld-x86-64/plt-main-ibt.dd: Likewise. * testsuite/ld-x86-64/property-x86-empty.s: Likewise. * testsuite/ld-x86-64/property-x86-ibt.s: Likewise. * testsuite/ld-x86-64/property-x86-ibt1a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt1a.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt1b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt1b.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt2-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt2.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3a.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3b.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt4-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt4.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt5-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt5.d: Likewise. * emulparams/elf32_x86_64.sh: Source emulparams/cet.sh. (TINY_READONLY_SECTION): Add .plt.sec. * emulparams/elf_i386.sh: Likewise. * emulparams/elf_x86_64.sh: Source emulparams/cet.sh. * ld.texinfo: Document -z ibtplt and -z ibt. * testsuite/ld-i386/i386.exp: Run IBT and IBT PLT tests. * testsuite/ld-x86-64/x86-64.exp: Likewise. * testsuite/ld-x86-64/pr21481b.S (check): Updated for x32. |
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Thomas Preud'homme
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2c6b98ea6f |
[ARM] Rework Tag_CPU_arch build attribute value selection
=== Context === This patch is part of a patch series to add support for ARMv8-R architecture. Its purpose is to rework the Tag_CPU_arch build attribute value selection to (i) match architecture or CPU if specified by user without any need for hack and (ii) match an architecture with all the features used if in autodetection mode or return an error. === Motivation === Currently, Tag_CPU_arch build attribute value selection assumes that an architecture is always a superset of architectures released earlier. As such, the logic is to browse architectures in chronological order of release and selecting the Tag_CPU_arch value of the last one to contribute a feature used[1]/requested[2] not contributed by earlier architectures. [1] in case of autodetection mode [2] otherwise, ie. in case of -mcpu/-march or associated directives This logic fails the two objectives mentionned in the Context section. First, due to the assumption it does an architecture can be selected while not having all the features used/requested which fails the second objective. Second, not doing an exact match when an architecture or CPU is selected by the user means the wrong value is chosen when a later architecture provides a subset of the feature bits of an earlier architecture. This is the case for the implementation of ARMv8-R (see later patch). An added benefit of this patch is that it is possible to easily generate more consistent build attribute by setting the feature bits from the architecture matched in aeabi_set_public_attributes in autodetection mode. This is better done as a separate patch because lots of testcase' expected results must then be updated accordingly. === Patch description === The patch changes the main logic for Tag_CPU_arch and Tag_CPU_arch_profile values selection to: - look for an exact match in case an architecture or CPU was specified on the command line or in a directive - select the first released architecture that provides a superset of the feature used in the autodetection case - select the most featureful architecture in case of -march=all The array cpu_arch_ver is updated to include all architectures in order to make the first point work. Note that when looking for an exact match, the architecture with selected extension is tried first and then only the architecture. This is because some architectures are exactly equivalent to an earlier architecture with its extensions selected. ARMv6S-M (= ARMv6-M + OS extension) and ARMv6KZ (ARMv6K + security extension) are two such examples. Other adjustments are also necessary in aeabi_set_public_attributes to make this change work. 1) The logic to set Tag_ARM_ISA_use and Tag_THUMB_ISA_use must check the absence of feature bit used/requested to decide whether to give the default value for empty files (see EABI attribute defaults test). It was previously checking that arch == 0 which would only happen if no feature bit could be matched by any architecture, ie there is no feature bit to match. 2) A fallback to a superset match must exist when no_cpu_selected () returns true. This is because aeabi_set_public_attributes is called again after relaxation and at this point selected_cpu is set from the previous execution of that function. There is therefore no way to check whether the user specified an architecture or CPU. 3) Tag_CPU_arch lines are removed from expected output when the detected architecture should be pre-ARMv4, since 0 is the Tag_CPU_arch value for pre-ARMv4 architectures and default value for an absent entry is 0. 2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (fpu_any): Defined from FPU_ANY. (cpu_arch_ver): Add all architectures and sort by release date. (have_ext_for_needed_feat_p): New. (get_aeabi_cpu_arch_from_fset): New. (aeabi_set_public_attributes): Call above function to determine Tag_CPU_arch and Tag_CPU_arch_profile values. Adapt Tag_ARM_ISA_use and Tag_THUMB_ISA_use selection logic to check absence of feature bit accordingly. * testsuite/gas/arm/attr-march-armv1.d: Fix expected Tag_CPU_arch build attribute value. * testsuite/gas/arm/attr-march-armv2.d: Likewise. * testsuite/gas/arm/attr-march-armv2a.d: Likewise. * testsuite/gas/arm/attr-march-armv2s.d: Likewise. * testsuite/gas/arm/attr-march-armv3.d: Likewise. * testsuite/gas/arm/attr-march-armv3m.d: Likewise. * testsuite/gas/arm/pr12198-2.d: Likewise. include/ * opcode/arm.h (FPU_ANY): New macro. |
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Alan Modra
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7dba9362c1 |
Rewrite __start and __stop symbol handling
This arranges for __start and __stop symbols to be defined before garbage collection, for all target formats. That should allow the COFF and PE --gc-sections to keep a singleton orphan input section, a feature lost by 2017-06-13 commit |
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Yao Qi
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6394c60699 |
Don't use print_insn_XXX in GDB
This is a follow-up to [PATCH 0/6] Unify the disassembler selection in gdb and objdump https://sourceware.org/ml/binutils/2017-05/msg00192.html that is, opcodes is able to select the right disassembler, so gdb doesn't have to select them. Instead, gdb can just use default_print_insn. As a result, these print_insn_XXX are not used out of opcodes, so this patch also moves their declarations from include/dis-asm.h to opcodes/disassemble.h. With this change, GDB doesn't use any print_insn_XXX directly any more. gdb: 2017-06-14 Yao Qi <yao.qi@linaro.org> * aarch64-tdep.c (aarch64_gdb_print_insn): Call default_print_insn instead of print_insn_aarch64. * arm-tdep.c (gdb_print_insn_arm): Call default_print_insn instead of print_insn_big_arm and print_insn_little_arm. * i386-tdep.c (i386_print_insn): Call default_print_insn instead of print_insn_i386. * ia64-tdep.c (ia64_print_insn): Call default_print_insn instead of print_insn_ia64. * mips-tdep.c (gdb_print_insn_mips): Call default_print_insn instead of print_insn_big_mips and print_insn_little_mips. * spu-tdep.c (gdb_print_insn_spu): Call default_print_insn instead of print_insn_spu. include: 2017-06-14 Yao Qi <yao.qi@linaro.org> * dis-asm.h (print_insn_aarch64): Move it to opcodes/disassemble.h. (print_insn_big_arm, print_insn_big_mips): Likewise. (print_insn_i386, print_insn_ia64): Likewise. (print_insn_little_arm, print_insn_little_mips): Likewise. (print_insn_spu): Likewise. opcodes: 2017-06-14 Yao Qi <yao.qi@linaro.org> * aarch64-dis.c: Include disassemble.h instead of dis-asm.h. * arm-dis.c: Likewise. * ia64-dis.c: Likewise. * mips-dis.c: Likewise. * spu-dis.c: Likewise. * disassemble.h (print_insn_aarch64): New declaration, moved from include/dis-asm.h. (print_insn_big_arm, print_insn_big_mips): Likewise. (print_insn_i386, print_insn_ia64): Likewise. (print_insn_little_arm, print_insn_little_mips): Likewise. |
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Andrew Burgess
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7bdf4127c3 |
ld: Allow section groups to be resolved as part of a relocatable link
This commit adds a new linker feature: the ability to resolve section groups as part of a relocatable link. Currently section groups are automatically resolved when performing a final link, and are carried through when performing a relocatable link. By carried through this means that one copy of each section group (from all the copies that might be found in all the input files) is placed into the output file. Sections that are part of a section group will not match input section specifiers within a linker script and are forcibly kept as separate sections. There is a slight resemblance between section groups and common section. Like section groups, common sections are carried through when performing a relocatable link, and resolved (allocated actual space) only at final link time. However, with common sections there is an ability to force the linker to allocate space for the common sections when performing a relocatable link, there's currently no such ability for section groups. This commit adds such a mechanism. This new facility can be accessed in two ways, first there's a command line switch --force-group-allocation, second, there's a new linker script command FORCE_GROUP_ALLOCATION. If one of these is used when performing a relocatable link then the linker will resolve the section groups as though it were performing a final link, the section group will be deleted, and the members of the group will be placed like normal input sections. If there are multiple copies of the group (from multiple input files) then only one copy of the group members will be placed, the duplicate copies will be discarded. Unlike common sections that have the --no-define-common command line flag, and INHIBIT_COMMON_ALLOCATION linker script command there is no way to prevent group resolution during a final link, this is because the ELF gABI specifically prohibits the presence of SHT_GROUP sections in a fully linked executable. However, the code as written should make adding such a feature trivial, setting the new resolve_section_groups flag to false during a final link should work as you'd expect. bfd/ChangeLog: * elf.c (_bfd_elf_make_section_from_shdr): Don't initially mark SEC_GROUP sections as SEC_EXCLUDE. (bfd_elf_set_group_contents): Replace use of abort with an assert. (assign_section_numbers): Use resolve_section_groups flag instead of relocatable link type. (_bfd_elf_init_private_section_data): Use resolve_section_groups flag instead of checking the final_link flag for part of the checks in here. Fix white space as a result. * elflink.c (elf_link_input_bfd): Use resolve_section_groups flag instead of relocatable link type. (bfd_elf_final_link): Likewise. include/ChangeLog: * bfdlink.h (struct bfd_link_info): Add new resolve_section_groups flag. ld/ChangeLog: * ld.h (struct args_type): Add force_group_allocation field. * ldgram.y: Add support for FORCE_GROUP_ALLOCATION. * ldlex.h: Likewise. * ldlex.l: Likewise. * lexsup.c: Likewise. * ldlang.c (unique_section_p): Check resolve_section_groups flag not the relaxable link flag. (lang_add_section): Discard section groups when we're resolving groups. Clear the SEC_LINK_ONCE flag if we're resolving section groups. * ldmain.c (main): Initialise resolve_section_groups flag in link_info based on command line flags. * testsuite/ld-elf/group11.d: New file. * testsuite/ld-elf/group12.d: New file. * testsuite/ld-elf/group12.ld: New file. * NEWS: Mention new features. * ld.texinfo (Options): Document --force-group-allocation. (Miscellaneous Commands): Document FORCE_GROUP_ALLOCATION. |
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Alan Modra
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f378ab099d |
PPC64_OPT_LOCALENTRY
ELFv2 functions with localentry:0 are those with a single entry point, ie. global entry == local entry, and that have no requirement on r2 or r12, and guarantee r2 is unchanged on return. Such an external function can be called via the PLT without saving r2 or restoring it on return, avoiding a common load-hit-store for small functions. The optimization is attractive. The TOC pointer load-hit-store is a major reason why calls to small functions that need no register saves, or with shrink-wrap, no register saves on a fast path, are slow on powerpc64le. To be safe, this optimization needs ld.so support to check that the run-time matches link-time function implementation. If a function in a shared library with st_other localentry non-zero is called without saving and restoring r2, r2 will be trashed on return, leading to segfaults. For that reason the optimization does not happen for weak functions since a weak definition is a fairly solid hint that the function will likely be overridden. I'm also not enabling the optimization by default unless glibc-2.26 is detected, which should have the ld.so checks implemented. bfd/ * elf64-ppc.c (struct ppc_link_hash_table): Add has_plt_localentry0. (ppc64_elf_merge_symbol_attribute): Merge localentry bits from dynamic objects. (is_elfv2_localentry0): New function. (ppc64_elf_tls_setup): Default params->plt_localentry0. (plt_stub_size): Adjust size for tls_get_addr_opt stub. (build_tls_get_addr_stub): Use a simpler stub when r2 is not saved. (ppc64_elf_size_stubs): Leave stub_type as ppc_stub_plt_call for optimized localentry:0 stubs. (ppc64_elf_build_stubs): Save r2 in ELFv2 __glink_PLTresolve. (ppc64_elf_relocate_section): Leave nop unchanged for optimized localentry:0 stubs. (ppc64_elf_finish_dynamic_sections): Set PPC64_OPT_LOCALENTRY in DT_PPC64_OPT. * elf64-ppc.h (struct ppc64_elf_params): Add plt_localentry0. include/ * elf/ppc64.h (PPC64_OPT_LOCALENTRY): Define. ld/ * emultempl/ppc64elf.em (params): Init plt_localentry0 field. (enum ppc64_opt): New, replacing OPTION_* defines. Add OPTION_PLT_LOCALENTRY, and OPTION_NO_PLT_LOCALENTRY. (PARSE_AND_LIST_*): Support --plt-localentry and --no-plt-localentry. * testsuite/ld-powerpc/elfv2so.d: Update. * testsuite/ld-powerpc/powerpc.exp (TLS opt 5): Use --no-plt-localentry. * testsuite/ld-powerpc/tlsopt5.d: Update. |
||
Eli Zaretskii
|
b9c6833008 |
Fix MinGW compilation warnings due to environ.h
include/ChangeLog: 2017-05-31 Eli Zaretskii <eliz@gnu.org> * environ.h: Add #ifndef guard. |
||
Anton Kolesov
|
940171d086 |
[ARC] Add arc-cpu.def with processor definitions
This patch extracts ARC CPU definitions from gas/config/tc-arc.c (cpu_types) into a separate file arc-cpu.def. This will allow reuse of CPU type definition in multiple places where it might be needed, for example in disassembler. This will help ensure that gas and disassembker use same option values for CPUs. arc-cpu.def file relies on preprocessor macroses which are defined somewhere else. This for example multiple C files to include arc-cpu.def, but define different macroses, therefore creating different structures. include/ChangeLog: yyyy-mm-dd Anton Kolesov <anton.kolesov@synopsys.com> * elf/arc-cpu.def: New file. gas/ChangeLog: yyyy-mm-dd Anton Kolesov <anton.kolesov@synopsys.com> * config/tc-arc.c (cpu_types): Include arc-cpu.def Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com> |
||
|
Andreas Krebbel
|
a09f258601 |
S/390: Improve error checking for optional operands
So far we only had an instruction flag which made an arbitrary number of operands optional. This limits error checking capabilities for instructions marked that way. With this patch the optparm flag only allows a single optional parameter and another one is added (optparm2) allowing 2 optional arguments. Hopefully we won't need more than that in the future. So far there will be only a single use of optparm2. gas/ChangeLog: 2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config/tc-s390.c (md_gather_operands): Support new optparm2 instruction flag. include/ChangeLog: 2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * opcode/s390.h: Add new instruction flags optparm2. opcodes/ChangeLog: 2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * s390-dis.c (s390_print_insn_with_opcode): Support new optparm2 instruction flag. * s390-mkopc.c (main): Recognize the new instruction flag when parsing instruction list. |
||
|
Andreas Krebbel
|
bfcfbe611b |
S/390: Remove optional operand flag.
The per operand optional flag hasn't been used for quite some time. Cleanup some remains. include/ChangeLog: 2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * opcode/s390.h: Remove S390_OPERAND_OPTIONAL. gas/ChangeLog: 2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config/tc-s390.c (md_gather_operands): Remove code dealing with S390_OPERAND_OPTIONAL. |
||
|
Yao Qi
|
88c1242dc0 |
Move print_insn_XXX to an opcodes internal header
With the changes done in previous patches, print_insn_XXX functions don't have to be external visible out of opcodes, because both gdb and objdump select disassemblers through a single interface. This patch moves these print_insn_XXX declarations from include/dis-asm.h to opcodes/disassemble.h, which is a new header added by this patch. include: 2017-05-24 Yao Qi <yao.qi@linaro.org> * dis-asm.h: Move some function declarations to opcodes/disassemble.h. opcodes: 2017-05-24 Yao Qi <yao.qi@linaro.org> * alpha-dis.c: Include disassemble.h, don't include dis-asm.h. * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise. * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise. * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise. * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise. * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise. * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise. * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise. * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise. * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise. * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise. * moxie-dis.c, msp430-dis.c, mt-dis.c: * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise. * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise. * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise. * rl78-dis.c, s390-dis.c, score-dis.c: Likewise. * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise. * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise. * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise. * v850-dis.c, vax-dis.c, visium-dis.c: Likewise. * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise. * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise. * z80-dis.c, z8k-dis.c: Likewise. * disassemble.h: New file. |
||
|
Yao Qi
|
003ca0fd22 |
Refactor disassembler selection
Nowadays, opcodes/disassemble.c:disassembler selects the proper disassembler according to ABFD only. However, it actually selects disassemblers according to arch, mach, endianess, and abfd. This patch adds them to the parameters of disassembler, so that its caller can still select disassemblers in case that abfd is NULL (a typical case in GDB). There isn't any functionality change. binutils: 2017-05-24 Yao Qi <yao.qi@linaro.org> * objdump.c (disassemble_data): Caller update. include: 2017-05-24 Yao Qi <yao.qi@linaro.org> * dis-asm.h (disassembler): Update declaration. opcodes: 2017-05-24 Yao Qi <yao.qi@linaro.org> * disassemble.c (disassembler): Add arguments a, big and mach. Use them. sim/common: 2017-05-24 Yao Qi <yao.qi@linaro.org> * sim-trace.c (trace_disasm): Caller update. |
||
claziss
|
575dcd27f8 |
[ARC] Update MAX_INSN_FLGS.
It is required to parse instructions like ldb.x.a.di. include/ 2017-05-23 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (MAX_INSN_FLGS): Update to 4. |
||
|
H.J. Lu
|
04ef582ace |
x86: Add NOTRACK prefix support
For register indirect branches, NOTRACK prefix (0x3e), which is also the DS segment register prefix, can be used to ignore the CET indirect branch track. gas/ * config/tc-i386.c (REX_PREFIX): Changed to 7. (NOTRACK_PREFIX): New. (MAX_PREFIXES): Changed to 8. (_i386_insn): Add notrack_prefix. (PREFIX_GROUP): Add PREFIX_DS. (add_prefix): Return PREFIX_DS for DS_PREFIX_OPCODE. (md_assemble): Check if NOTRACK prefix is supported. (parse_insn): Set notrack_prefix and issue an error for other prefixes after NOTRACK prefix. * testsuite/gas/i386/i386.exp: Run tests for NOTRACK prefix. * testsuite/gas/i386/notrack-intel.d: New file. * testsuite/gas/i386/notrack.d: Likewise. * testsuite/gas/i386/notrack.s: Likewise. * testsuite/gas/i386/notrackbad.l: Likewise. * testsuite/gas/i386/notrackbad.s: Likewise. * testsuite/gas/i386/x86-64-notrack-intel.d: Likewise. * testsuite/gas/i386/x86-64-notrack.d: Likewise. * testsuite/gas/i386/x86-64-notrack.s: Likewise. * testsuite/gas/i386/x86-64-notrackbad.l: Likewise. * testsuite/gas/i386/x86-64-notrackbad.s: Likewise. include/ * include/opcode/i386.h (NOTRACK_PREFIX_OPCODE): New. opcodes/ * i386-dis.c (NOTRACK_Fixup): New. (NOTRACK): Likewise. (NOTRACK_PREFIX): Likewise. (last_active_prefix): Likewise. (reg_table): Use NOTRACK on indirect call and jmp. (ckprefix): Set last_active_prefix. (prefix_name): Return "notrack" for NOTRACK_PREFIX. * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk. * i386-opc.h (NoTrackPrefixOk): New. (i386_opcode_modifier): Add notrackprefixok. * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp. Add notrack. * i386-tbl.h: Regenerated. |
||
Jose E. Marchesi
|
6451799480 |
binutils: support for the SPARC M8 processor
This patch adds support for the new SPARC M8 processor (implementing OSA
2017) to binutils.
New instructions:
- Dictionary Unpack
+ dictunpack
- Partitioned Compare with shifted result
+ Signed variants: fpcmp{le,gt,eq,ne}{8,16,32}shl
+ Unsigned variants: fpcmpu{le,gt}{8,16,32}shl
- Partitioned Dual-Equal compared, with shifted result
+ fpcmpde{8,16,32}shl
- Partitioned Unsigned Range Compare, with shifted result
+ fpcmpur{8,16,32}shl
- 64-bit shifts on Floating-Point registers
+ fps{ll,ra,rl}64x
- Misaligned loads and stores
+ ldm{sh,uh,sw,uw,x,ux}
+ ldm{sh,uh,sw,uw,x,ux}a
+ ldmf{s,d}
+ ldmf{s,d}a
+ stm{h,w,x}
+ stm{h,w,x}a
+ stmf{s,d}
+ stmf{s,d}a
- Oracle Numbers
+ on{add,sub,mul,div}
- Reverse Bytes/Bits
+ revbitsb
+ revbytes{h,w,x}
- Run-Length instructions
+ rle_burst
+ rle_length
- New crypto instructions
+ sha3
- Instruction to read the new register %entropy
+ rd %entropy
New Alternate Address Identifiers:
- 0x24, #ASI_CORE_COMMIT_COUNT
- 0x24, #ASI_CORE_SELECT_COUNT
- 0x48, #ASI_ARF_ECC_REG
- 0x53, #ASI_ITLB_PROBE
- 0x58, #ASI_DSFAR
- 0x5a, #ASI_DTLB_PROBE_PRIMARY
- 0x5b, #ASI_DTLB_PROBE_REAL
- 0x64, #ASI_CORE_SELECT_COMMIT_NHT
The new assembler command-line options for selecting the M8 architecture
are:
-Av9m8 or -Asparc6 for 64-bit binaries.
-Av8plusm8 for 32-bit (v8+) binaries.
The corresponding disassembler command-line options are:
-msparc:v9m8 for 64-bit binaries.
-msparc:v8plusm8 for 32-bit (v8+) binaries.
Tested for regressions in the following targets:
sparc-aout sparc-linux sparc-vxworks sparc64-linux
bfd/ChangeLog:
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* archures.c (bfd_mach_sparc_v9m8): Define.
(bfd_mach_sparc_v8plusm8): Likewise.
(bfd_mach_sparc_v9_p): Adjust to M8.
(bfd_mach_sparc_64bit_p): Likewise.
* aoutx.h (machine_type): Handle bfd_mach_sparc_v9m8 and
bfd_mach_sparc_v8plusm8.
* bfd-in2.h: Regenerated.
* cpu-sparc.c (arch_info_struct): Entries for sparc:v9m8 and
sparc:v8plusm8.
* elfxx-sparc.c (_bfd_sparc_elf_object_p): Handle
bfd_mach_sparc_v8plusm8 and bfd_mach_sparc_v9m8 using the new hw
capabilities ONADDSUB, ONMUL, ONDIV, DICTUNP, FPCPSHL, RLE and
SHA3.
* elf32-sparc.c (elf32_sparc_final_write_processing): Handle
bfd_mach_sparc_v8plusm8.
binutils/ChangeLog:
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* NEWS: Mention the SPARC M8 support.
gas/ChangeLog:
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_arch_table): Entries for `sparc6',
`v9m8' and `v8plusm8'.
(sparc_md_end): Handle SPARC_OPCODE_ARCH_M8.
(get_hwcap_name): Support the M8 hardware capabilities.
(sparc_ip): Handle new operand types.
* doc/c-sparc.texi (Sparc-Opts): Document -Av9m8, -Av8plusm8 and
-Asparc6, and the corresponding -xarch aliases.
* testsuite/gas/sparc/sparc6.s: New file.
* testsuite/gas/sparc/sparc6.d: Likewise.
* testsuite/gas/sparc/sparc6-diag.s: Likewise.
* testsuite/gas/sparc/sparc6-diag.l: Likewise.
* testsuite/gas/sparc/fpcmpshl.s: Likewise.
* testsuite/gas/sparc/fpcmpshl.d: Likewise.
* testsuite/gas/sparc/fpcmpshl-diag.s: Likewise.
* testsuite/gas/sparc/fpcmpshl-diag.l: Likewise.
* testsuite/gas/sparc/ldm-stm.s: Likewise.
* testsuite/gas/sparc/ldm-stm.d: Likewise.
* testsuite/gas/sparc/ldm-stm-diag.s: Likewise.
* testsuite/gas/sparc/ldm-stm-diag.l: Likewise.
* testsuite/gas/sparc/ldmf-stmf.s: Likewise.
* testsuite/gas/sparc/ldmf-stmf.d: Likewise.
* testsuite/gas/sparc/ldmf-stmf-diag.s: Likewise.
* testsuite/gas/sparc/ldmf-stmf-diag.l: Likewise.
* testsuite/gas/sparc/on.s: Likewise.
* testsuite/gas/sparc/on.d: Likewise.
* testsuite/gas/sparc/on-diag.s: Likewise.
* testsuite/gas/sparc/on-diag.l: Likewise.
* testsuite/gas/sparc/rle.s: Likewise.
* testsuite/gas/sparc/rle.d: Likewise.
* testsuite/gas/sparc/sparc.exp (gas_64_check): Run new tests.
* testsuite/gas/sparc/rdasr.s: Add test for RDENTROPY.
* testsuite/gas/sparc/rdasr.d: Likewise.
include/ChangeLog:
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* elf/sparc.h (ELF_SPARC_HWCAP2_SPARC6): Define.
(ELF_SPARC_HWCAP2_ONADDSUB): Likewise.
(ELF_SPARC_HWCAP2_ONMUL): Likewise.
(ELF_SPARC_HWCAP2_ONDIV): Likewise.
(ELF_SPARC_HWCAP2_DICTUNP): Likewise.
(ELF_SPARC_HWCAP2_FPCMPSHL): Likewise.
(ELF_SPARC_HWCAP2_RLE): Likewise.
(ELF_SPARC_HWCAP2_SHA3): Likewise.
* opcode/sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_M8
and adjust SPARC_OPCODE_ARCH_MAX.
(HWCAP2_SPARC6): Define.
(HWCAP2_ONADDSUB): Likewise.
(HWCAP2_ONMUL): Likewise.
(HWCAP2_ONDIV): Likewise.
(HWCAP2_DICTUNP): Likewise.
(HWCAP2_FPCMPSHL): Likewise.
(HWCAP2_RLE): Likewise.
(HWCAP2_SHA3): Likewise.
(OPM): Likewise.
(OPMI): Likewise.
(ONFCN): Likewise.
(REVFCN): Likewise.
(SIMM10): Likewise.
opcodes/ChangeLog:
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
(X_IMM2): Define.
(compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
bfd_mach_sparc_v9m8.
(print_insn_sparc): Handle new operand types.
* sparc-opc.c (MASK_M8): Define.
(v6): Add MASK_M8.
(v6notlet): Likewise.
(v7): Likewise.
(v8): Likewise.
(v9): Likewise.
(v9a): Likewise.
(v9b): Likewise.
(v9c): Likewise.
(v9d): Likewise.
(v9e): Likewise.
(v9v): Likewise.
(v9m): Likewise.
(v9andleon): Likewise.
(m8): Define.
(HWS_VM8): Define.
(HWS2_VM8): Likewise.
(sparc_opcode_archs): Add entry for "m8".
(sparc_opcodes): Add OSA2017 and M8 instructions
dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
fpx{ll,ra,rl}64x,
ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
(asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
ASI_CORE_SELECT_COMMIT_NHT.
|
||
|
Alan Modra
|
bc4e12ded1 |
Rename non_ir_ref to non_ir_ref_regular
Since the flag is now set only for regular object refs. include/ * bfdlink.h (struct bfd_link_hash_entry <non_ir_ref>): Rename to non_ir_ref_regular. bfd/ * elf-m10300.c: Rename occurrences of non_ir_ref. * elf32-arm.c: Likewise. * elf32-bfin.c: Likewise. * elf32-cr16.c: Likewise. * elf32-cris.c: Likewise. * elf32-d10v.c: Likewise. * elf32-dlx.c: Likewise. * elf32-fr30.c: Likewise. * elf32-frv.c: Likewise. * elf32-hppa.c: Likewise. * elf32-i370.c: Likewise. * elf32-i386.c: Likewise. * elf32-iq2000.c: Likewise. * elf32-lm32.c: Likewise. * elf32-m32c.c: Likewise. * elf32-m32r.c: Likewise. * elf32-m68hc1x.c: Likewise. * elf32-m68k.c: Likewise. * elf32-mcore.c: Likewise. * elf32-metag.c: Likewise. * elf32-microblaze.c: Likewise. * elf32-moxie.c: Likewise. * elf32-msp430.c: Likewise. * elf32-mt.c: Likewise. * elf32-nios2.c: Likewise. * elf32-or1k.c: Likewise. * elf32-ppc.c: Likewise. * elf32-rl78.c: Likewise. * elf32-s390.c: Likewise. * elf32-score.c: Likewise. * elf32-score7.c: Likewise. * elf32-sh.c: Likewise. * elf32-tic6x.c: Likewise. * elf32-tilepro.c: Likewise. * elf32-v850.c: Likewise. * elf32-vax.c: Likewise. * elf32-xstormy16.c: Likewise. * elf32-xtensa.c: Likewise. * elf64-alpha.c: Likewise. * elf64-hppa.c: Likewise. * elf64-ia64-vms.c: Likewise. * elf64-mmix.c: Likewise. * elf64-ppc.c: Likewise. * elf64-s390.c: Likewise. * elf64-sh64.c: Likewise. * elf64-x86-64.c: Likewise. * elflink.c: Likewise. * elfnn-aarch64.c: Likewise. * elfnn-ia64.c: Likewise. * elfnn-riscv.c: Likewise. * elfxx-mips.c: Likewise. * elfxx-sparc.c: Likewise. * elfxx-tilegx.c: Likewise. * linker.c: Likewise. ld/ * plugin.c: Rename occurrences of non_ir_ref. |
||
|
Alan Modra
|
4070765b1a |
non_ir_ref_dynamic
dynamic_ref_after_ir_def is a little odd compared to other symbol flags in that as the name suggests, it is set only for certain references after a definition. It turns out that setting a flag for any non-ir reference from a dynamic object can be used to solve the problem for which this flag was invented, which I think is a cleaner. This patch does that, and sets non_ir_ref only for regular object references. include/ * bfdlink.h (struct bfd_link_hash_entry): Update non_ir_ref comment. Rename dynamic_ref_after_ir_def to non_ir_ref_dynamic. ld/ * plugin.c (is_visible_from_outside): Use non_ir_ref_dynamic. (plugin_notice): Set non_ir_ref for references from regular objects, non_ir_ref_dynamic for references from dynamic objects. bfd/ * elf64-ppc.c (add_symbol_adjust): Transfer non_ir_ref_dynamic. * elflink.c (elf_link_add_object_symbols): Update to use non_ir_ref_dynamic. (elf_link_input_bfd): Test non_ir_ref_dynamic in addition to non_ir_ref. * linker.c (_bfd_generic_link_add_one_symbol): Likewise. |
||
|
Maciej W. Rozycki
|
25499ac7ee |
MIPS16e2: Add MIPS16e2 ASE support
Add MIPS16e2 ASE support as per the architecture specification[1],
including in particular:
1. A new ELF ASE flag to mark MIPS16e2 binaries.
2. MIPS16e2 instruction assembly support, including a relaxation update
to use LUI rather than an LI/SLL instruction pair for loading the
high part of 32-bit addresses.
3. MIPS16e2 instruction disassembly support, including updated rules for
extended forms of instructions that are now subdecoded and therefore
do not alias to the original MIPS16 ISA revision instructions even
for encodings that are not valid in the MIPS16e2 instruction set.
Add `-mmips16e2' and `-mno-mips16e2' GAS command-line options and their
corresponding `mips16e2' and `no-mips16e2' settings for the `.set' and
`.module' pseudo-ops. Control the availability of the MT ASE subset of
the MIPS16e2 instruction set with a combination of these controls and
the preexisting MT ASE controls.
Parts of this change by Matthew Fortune and Andrew Bennett.
References:
[1] "MIPS32 Architecture for Programmers: MIPS16e2 Application-Specific
Extension Technical Reference Manual", Imagination Technologies
Ltd., Document Number: MD01172, Revision 01.00, April 26, 2016
include/
* elf/mips.h (AFL_ASE_MIPS16E2): New macro.
(AFL_ASE_MASK): Adjust accordingly.
* opcode/mips.h: Document new operand codes defined.
(mips_operand_type): Add OP_REG28 enum value.
(INSN2_SHORT_ONLY): Update description.
(ASE_MIPS16E2, ASE_MIPS16E2_MT): New macros.
bfd/
* elfxx-mips.c (print_mips_ases): Handle MIPS16e2 ASE.
opcodes/
* mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
(mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
(print_insn_arg) <OP_REG28>: Add handler.
(validate_insn_args) <OP_REG28>: Handle.
(print_mips16_insn_arg): Handle MIPS16 instructions that require
32-bit encoding and 9-bit immediates.
(print_insn_mips16): Handle MIPS16 instructions that require
32-bit encoding and MFC0/MTC0 operand decoding.
* mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
<'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
(RD_C0, WR_C0, E2, E2MT): New macros.
(mips16_opcodes): Add entries for MIPS16e2 instructions:
GP-relative "addiu" and its "addu" spelling, "andi", "cache",
"di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
"lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
"movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
"pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
instructions, "swl", "swr", "sync" and its "sync_acquire",
"sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
"xori", "dmt", "dvpe", "emt" and "evpe". Add split
regular/extended entries for original MIPS16 ISA revision
instructions whose extended forms are subdecoded in the MIPS16e2
ISA revision: "li", "sll" and "srl".
binutils/
* readelf.c (print_mips_ases): Handle MIPS16e2 ASE.
* NEWS: Mention MIPS16e2 ASE support.
gas/
* config/tc-mips.c (RELAX_MIPS16_ENCODE): Add `e2' flag.
(RELAX_MIPS16_E2): New macro.
(RELAX_MIPS16_PIC, RELAX_MIPS16_SYM32, RELAX_MIPS16_NOMACRO)
(RELAX_MIPS16_USER_SMALL, RELAX_MIPS16_USER_EXT)
(RELAX_MIPS16_DSLOT, RELAX_MIPS16_JAL_DSLOT)
(RELAX_MIPS16_EXTENDED, RELAX_MIPS16_MARK_EXTENDED)
(RELAX_MIPS16_CLEAR_EXTENDED, RELAX_MIPS16_ALWAYS_EXTENDED)
(RELAX_MIPS16_MARK_ALWAYS_EXTENDED)
(RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED, RELAX_MIPS16_MACRO)
(RELAX_MIPS16_MARK_MACRO, RELAX_MIPS16_CLEAR_MACRO): Shift bits.
(mips16_immed_extend): New prototype.
(options): Add OPTION_MIPS16E2 and OPTION_NO_MIPS16E2 enum
values.
(md_longopts): Add "mmips16e2" and "mno-mips16e2" options.
(mips_ases): Add "mips16e2" entry.
(mips_set_ase): Handle MIPS16e2 ASE.
(insn_insert_operand): Explicitly handle immediates with MIPS16
instructions that require 32-bit encoding.
(is_opcode_valid_16): Pass enabled ASE bitmask on to
`opcode_is_member'.
(validate_mips_insn): Explicitly handle immediates with MIPS16
instructions that require 32-bit encoding.
(operand_reg_mask) <OP_REG28>: Add handler.
(match_reg28_operand): New function.
(match_operand) <OP_REG28>: Add handler.
(append_insn): Pass ASE_MIPS16E2 setting to RELAX_MIPS16_ENCODE.
(match_mips16_insn): Handle MIPS16 instructions that require
32-bit encoding and `V' and `u' operand codes.
(mips16_ip): Allow any characters except from `.' in opcodes.
(mips16_immed_extend): Handle 9-bit immediates. Do not shuffle
immediates whose width is not one of these listed.
(md_estimate_size_before_relax): Handle MIPS16e2 relaxation.
(mips_relax_frag): Likewise.
(md_convert_frag): Likewise.
(mips_convert_ase_flags): Handle MIPS16e2 ASE.
* doc/as.texinfo (Target MIPS options): Add `-mmips16e2' and
`-mno-mips16e2' options.
(-mmips16e2, -mno-mips16e2): New options.
* doc/c-mips.texi (MIPS Options): Add `-mmips16e2' and
`-mno-mips16e2' options.
(MIPS ASE Instruction Generation Overrides): Add `.set mips16e2'
and `.set nomips16e2'.
|
||
John David Anglin
|
cd85e51ad3 | Fix match and mask for 64-bit bb opcode. | ||
|
Claudiu Zissulescu
|
53a346d823 |
[ARC] Object attributes.
gas/ 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/attr-arc600.d: New file. * testsuite/gas/arc/attr-arc600_mul32x16.d: Likewise. * testsuite/gas/arc/attr-arc600_norm.d: Likewise. * testsuite/gas/arc/attr-arc601.d: Likewise. * testsuite/gas/arc/attr-arc601_mul32x16.d: Likewise. * testsuite/gas/arc/attr-arc601_mul64.d: Likewise. * testsuite/gas/arc/attr-arc601_norm.d: Likewise. * testsuite/gas/arc/attr-arc700.d: Likewise. * testsuite/gas/arc/attr-arcem.d: Likewise. * testsuite/gas/arc/attr-archs.d: Likewise. * testsuite/gas/arc/attr-autodetect-1.d: Likewise. * testsuite/gas/arc/attr-autodetect-1.s: Likewise. * testsuite/gas/arc/attr-cpu-a601.d: Likewise. * testsuite/gas/arc/attr-cpu-a601.s: Likewise. * testsuite/gas/arc/attr-cpu-a700.d: Likewise. * testsuite/gas/arc/attr-cpu-a700.s: Likewise. * testsuite/gas/arc/attr-cpu-em.d: Likewise. * testsuite/gas/arc/attr-cpu-em.s: Likewise. * testsuite/gas/arc/attr-cpu-hs.d: Likewise. * testsuite/gas/arc/attr-cpu-hs.s: Likewise. * testsuite/gas/arc/attr-em.d: Likewise. * testsuite/gas/arc/attr-em4.d: Likewise. * testsuite/gas/arc/attr-em4_dmips.d: Likewise. * testsuite/gas/arc/attr-em4_fpuda.d: Likewise. * testsuite/gas/arc/attr-em4_fpus.d: Likewise. * testsuite/gas/arc/attr-hs.d: Likewise. * testsuite/gas/arc/attr-hs34.d: Likewise. * testsuite/gas/arc/attr-hs38.d: Likewise. * testsuite/gas/arc/attr-hs38_linux.d: Likewise. * testsuite/gas/arc/attr-mul64.d: Likewise. * testsuite/gas/arc/attr-name.d: Likewise. * testsuite/gas/arc/attr-name.s: Likewise. * testsuite/gas/arc/attr-nps400.d: Likewise. * testsuite/gas/arc/attr-override-mcpu.d: Likewise. * testsuite/gas/arc/attr-override-mcpu.s * testsuite/gas/arc/attr-quarkse_em.d: Likewise. * testsuite/gas/arc/blank.s: Likewise. * testsuite/gas/elf/section2.e-arc: Likewise. * testsuite/gas/arc/cpu-pseudop-1.d: Update test. * testsuite/gas/arc/cpu-pseudop-2.d: Likewise. * testsuite/gas/arc/nps400-0.d: Likewise. * testsuite/gas/elf/elf.exp: Set target_machine for ARC. * config/tc-arc.c (opcode/arc-attrs.h): Include. (ARC_GET_FLAG, ARC_SET_FLAG, streq): Define. (arc_attribute): Declare new function. (md_pseudo_table): Add arc_attribute. (cpu_types): Rename default cpu features. (selected_cpu): Set the default OSABI flag. (mpy_option): New variable. (pic_option): Likewise. (sda_option): Likewise. (tls_option): Likewise. (feature_type, feature_list): Remove. (arc_initial_eflag): Likewise. (attributes_set_explicitly): New variable. (arc_check_feature): Check also for the conflicting features. (arc_select_cpu): Refactor assignment of selected_cpu.eflags. (arc_option): Remove setting of private flags and architecture. (check_cpu_feature): Refactor feature names. (autodetect_attributes): New function. (assemble_tokens): Use above function. (md_parse_option): Refactor feature names. (arc_attribute): New function. (arc_set_attribute_int): Likewise. (arc_set_attribute_string): Likewise. (arc_stralloc): Likewise. (arc_set_public_attributes): Likewise. (arc_md_end): Likewise. (arc_copy_symbol_attributes): Likewise. (rc_convert_symbolic_attribute): Likewise. * config/tc-arc.h (md_end): Define. (CONVERT_SYMBOLIC_ATTRIBUTE): Likewise. (TC_COPY_SYMBOL_ATTRIBUTES): Likewise. * doc/c-arc.texi: Document ARC object attributes. binutils/ 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> * readelf.c (decode_ARC_machine_flags): Recognize OSABI v4. (get_arc_section_type_name): New function. (get_section_type_name): Use the above function. (display_arc_attribute): New function. (process_arc_specific): Likewise. (process_arch_specific): Handle ARC specific information. * testsuite/binutils-all/strip-3.d: Consider ARC.attributes section. include/ 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> * elf/arc.h (SHT_ARC_ATTRIBUTES): Define. (Tag_ARC_*): Define. (E_ARC_OSABI_V4): Define. (E_ARC_OSABI_CURRENT): Reassign it. (TAG_CPU_*): Define. * opcode/arc-attrs.h: New file. * opcode/arc.h (insn_subclass_t): Assign enum values. (insn_subclass_t): Update enum with QUARKSE1, QUARKSE2, and LL64. (ARC_EA, ARC_CD, ARC_LLOCK, ARC_ATOMIC, ARC_MPY, ARC_MULT) (ARC_NPS400, ARC_DPFP, ARC_SPFP, ARC_FPU, ARC_FPUDA, ARC_SWAP) (ARC_NORM, ARC_BSCAN, ARC_UIX, ARC_TSTAMP, ARC_VBFDW) (ARC_BARREL, ARC_DSPA, ARC_SHIFT, ARC_INTR, ARC_DIV, ARC_XMAC) (ARC_CRC): Delete. bfd/ 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> * elf32-arc.c (FEATURE_LIST_NAME): Define. (CONFLICT_LIST): Likewise. (opcode/arc-attrs.h): Include. (arc_elf_print_private_bfd_data): Print OSABI v4 flag. (arc_extract_features): New file. (arc_stralloc): Likewise. (arc_elf_merge_attributes): Likewise. (arc_elf_merge_private_bfd_data): Use object attributes. (bfd_arc_get_mach_from_attributes): New function. (arc_elf_object_p): Use object attributes. (arc_elf_final_write_processing): Likewise. (elf32_arc_obj_attrs_arg_type): New function. (elf32_arc_obj_attrs_handle_unknown): Likewise. (elf32_arc_section_from_shdr): Likewise. (elf_backend_obj_attrs_vendor): Define. (elf_backend_obj_attrs_section): Likewise. (elf_backend_obj_attrs_arg_type): Likewise. (elf_backend_obj_attrs_section_type): Likewise. (elf_backend_obj_attrs_handle_unknown): Likewise. (elf_backend_section_from_shdr): Likewise. ld/ 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/ld-arc/attr-merge-0.d: New file. * testsuite/ld-arc/attr-merge-0.s: Likewise. * testsuite/ld-arc/attr-merge-0e.s: Likewise. * testsuite/ld-arc/attr-merge-1.d: Likewise. * testsuite/ld-arc/attr-merge-1.s: Likewise. * testsuite/ld-arc/attr-merge-1e.s: Likewise. * testsuite/ld-arc/attr-merge-2.d: Likewise. * testsuite/ld-arc/attr-merge-2.s: Likewise. * testsuite/ld-arc/attr-merge-3.d: Likewise. * testsuite/ld-arc/attr-merge-3.s: Likewise. * testsuite/ld-arc/attr-merge-3e.s: Likewise. * testsuite/ld-arc/attr-merge-4.s: Likewise. * testsuite/ld-arc/attr-merge-5.d: Likewise. * testsuite/ld-arc/attr-merge-5a.s: Likewise. * testsuite/ld-arc/attr-merge-5b.s: Likewise. * testsuite/ld-arc/attr-merge-conflict-isa.d: Likewise. * testsuite/ld-arc/attr-merge-err-isa.d: Likewise. * testsuite/ld-arc/attr-merge-incompatible-cpu.d: Likewise. * testsuite/ld-arc/got-01.d: Update test. * testsuite/ld-arc/attr-merge-err-quarkse.d: New file. * testsuite/ld-arc/attr-quarkse.s: Likewise. * testsuite/ld-arc/attr-quarkse2.s: Likewise. opcodes/ 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> * arc-dis.c (parse_option): Update quarkse_em option.. * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to QUARKSE1. (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2. |
||
|
H.J. Lu
|
59fa66c538 |
Handle symbol defined in IR and referenced in DSO
We need to make an IR symbol visible if it is defined in an IR object and referenced in a dynamic object. When --as-needed is used, since linker removes the IR symbol reference of the dynamic object if the dynamic object isn't needed in the first pass, the IR definition isn't visible to the dynamic object even if the dynamic object becomes needed in the second pass. Add dynamic_ref_after_ir_def to bfd_link_hash_entry to track IR symbol which is defined in an IR object and later referenced in a dynamic object. dynamic_ref_after_ir_def is preserved when restoring the symbol table for unneeded dynamic object. bfd/ PR ld/21382 * elflink.c (elf_link_add_object_symbols): Preserve dynamic_ref_after_ir_def when restoring the symbol table for unneeded dynamic object. include/ PR ld/21382 * bfdlink.h (bfd_link_hash_entry): Add dynamic_ref_after_ir_def. ld/ PR ld/21382 * plugin.c (is_visible_from_outside): Symbol may be visible from outside if dynamic_ref_after_ir_def is set. (plugin_notice): Set dynamic_ref_after_ir_def if the symbol is defined in an IR object and referenced in a dynamic object. * testsuite/ld-plugin/lto.exp: Run PR ld/21382 tests. * testsuite/ld-plugin/pr21382a.c: New file. * testsuite/ld-plugin/pr21382b.c: Likewise. |
||
|
Alan Modra
|
954b63d4c8 |
Implement -z dynamic-undefined-weak
-z nodynamic-undefined-weak is only implemented for x86. (The sparc backend has some support code but doesn't enable the option by including ld/emulparams/dynamic_undefined_weak.sh, and since the support looks like it may be broken I haven't enabled it.) This patch adds the complementary -z dynamic-undefined-weak, extends both options to affect building of shared libraries as well as executables, and adds support for the option on powerpc. include/ * bfdlink.h (struct bfd_link_info <dynamic_undefined_weak>): Revise comment. bfd/ * elflink.c (_bfd_elf_adjust_dynamic_symbol): Hide undefweak or make dynamic for info->dynamic_undefined_weak 0 and 1. * elf32-ppc.c:Formatting. (ensure_undefweak_dynamic): Don't make dynamic when info->dynamic_undefined_weak is zero. (allocate_dynrelocs): Discard undefweak dyn_relocs for info->dynamic_undefined_weak. Discard undef dyn_relocs when not default visibility. Discard undef and undefweak dyn_relocs earlier. (ppc_elf_relocate_section): Adjust to suit. * elf64-ppc.c: Formatting. (ensure_undefweak_dynamic): Don't make dynamic when info->dynamic_undefined_weak is zero. (allocate_dynrelocs): Discard undefweak dyn_relocs for info->dynamic_undefined_weak. Discard them earlier. ld/ * ld.texinfo (dynamic-undefined-weak): Document. (nodynamic-undefined-weak): Document that this option now can be used with shared libs. * emulparams/dynamic_undefined_weak.sh: Support -z dynamic-undefined-weak. * emulparams/elf32ppccommon.sh: Include dynamic_undefined_weak.sh. * testsuite/ld-undefined/weak-undef.exp (undef_weak_so), (undef_weak_exe): New. Use them. Add -z dynamic-undefined-weak and -z nodynamic-undefined-weak tests. * Makefile.am: Update powerpc dependencies. * Makefile.in: Regenerate. |
||
|
Alan Modra
|
c03dc33b60 |
Reorder PPC_OPCODE_* and set PPC_OPCODE_TMR for e6500
PPC_OPCODE_* renumbered to fill the gaps left by previous patches, and reordered chronologically just because. I kept PPC_OPCODE_TMR because presumably it might be used in future APUinfo for e6500. include/ * opcode/ppc.h (PPC_OPCODE_*): Renumber and order chronologically. (PPC_OPCODE_SPE): Comment on this and other bits used for APUinfo. opcodes/ * ppc-dis.c (ppc_opts): Formatting. Set PPC_OPCODE_TMR for e6500. * ppc-opc.c (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500. |
||
|
Alan Modra
|
ef85eab0ec |
Bye bye PPC_OPCODE_HTM and -mhtm
The -mhtm option is fairly useless too. include/ * opcode/ppc.h (PPC_OPCODE_HTM): Delete. gas/ * config/tc-ppc.c (md_show_usage): Delete mention of -mhtm. * testsuite/gas/ppc/htm.d: Pass -mpower8 and -Mpower8. opcodes/ * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_HTM and "htm". * ppc-opc.c (PPCHTM): Define as PPC_OPCODE_POWER8. |
||
|
Alan Modra
|
9570835e55 |
Bye Bye PPC_OPCODE_VSX3
This bit is also useless as it can be replaced with PPC_OPCODE_POWER9. Defining the VSX2 and VSX3 selection based on cpu bits also lets the assembler/disassembler distinguish between the power7 VSX opcodes and the power8 ones. Note that this change means -mvsx now reverts back to just adding the power7 VSX insns. include/ * opcode/ppc.h (PPC_OPCODE_VSX3): Delete. opcodes/ * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_VSX3. * ppc-opc.c (PPCVSX2): Define as PPC_OPCODE_POWER8. (PPCVSX3): Define as PPC_OPCODE_POWER9. |
||
|
Alan Modra
|
9a85b496ac |
Bye bye PPC_OPCODE_ALTIVEC2
This bit is worse than useless. Using it prevents the assembler and disassembler distinguishing between opcodes added for power8 and those added for power9. include/ * opcode/ppc.h (PPC_OPCODE_ALTIVEC2): Delete. opcodes/ * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2. * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500. (PPCVEC3): Define as PPC_OPCODE_POWER9. |
||
Pip Cet
|
62ecb94c4a |
Add support for disassembling WebAssembly opcodes.
include * dis-asm.h: Add prototypes for wasm32 disassembler. opcodes * Makefile.am: Add wasm32-dis.c. * configure.ac: Add wasm32-dis.c to wasm32 target. * disassemble.c: Add wasm32 disassembler code. * wasm32-dis.c: New file. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate. * po/opcodes.pot: Regenerate. gas * testsuite/gas/wasm32/allinsn.d: Adjust test for disassembler changes. * testsuite/gas/wasm32/disass.d: New test. * testsuite/gas/wasm32/disass.s: New test. * testsuite/gas/wasm32/disass-2.d: New test. * testsuite/gas/wasm32/disass-2.s: New test. * testsuite/gas/wasm32/reloc.d: Adjust test for changed reloc names. * testsuite/gas/wasm32/reloc.s: Update test for changed assembler syntax. * testsuite/gas/wasm32/wasm32.exp: Run new tests. Expect allinsn test to succeed. |
||
Pedro Alves
|
f995bbe8e6 |
-Wwrite-strings: Constify struct disassemble_info's disassembler_options field
The memory disassemble_info::disassembler_options points to is always owned by the client. I.e., that field is an non-owning, observing pointer. Thus const makes sense. Are the include/ and opcodes/ bits OK? Tested on x86_64 Fedora 23, built with --enable-targets=all. include/ChangeLog: 2017-04-05 Pedro Alves <palves@redhat.com> * dis-asm.h (disassemble_info) <disassembler_options>: Now a "const char *". (next_disassembler_option): Constify. opcodes/ChangeLog: 2017-04-05 Pedro Alves <palves@redhat.com> * arc-dis.c (parse_option, parse_disassembler_options): Constify. * arm-dis.c (parse_arm_disassembler_options): Constify. * ppc-dis.c (powerpc_init_dialect): Constify local. * vax-dis.c (parse_disassembler_options): Constify. gdb/ChangeLog: 2017-04-05 Pedro Alves <palves@redhat.com> * arm-tdep.c (show_disassembly_style_sfunc): Constify local. * disasm.c (set_disassembler_options): Constify local. * i386-tdep.c (i386_print_insn): Remove cast and FIXME comment. |
||
|
H.J. Lu
|
a91e1603af |
Support ELF SHF_GNU_MBIND and PT_GNU_MBIND_XXX
Mark an ALLOC section, which should be placed in special memory area,
with SHF_GNU_MBIND. Its sh_info field indicates the special memory
type. GNU_MBIND section names start with ".mbind" so that they are
placed as orphan sections by linker. All input GNU_MBIND sections
with the same sh_type, sh_flags and sh_info are placed in one output
GNU_MBIND section. In executable and shared object, create a
GNU_MBIND segment for each GNU_MBIND section and its segment type is
PT_GNU_MBIND_LO plus the sh_info value. Each GNU_MBIND segment is
aligned at page boundary.
The assembler syntax:
.section .mbind.foo,"adx",%progbits
^ 0: Special memory type.
|
'd' for SHF_GNU_MBIND.
.section .mbind.foo,"adx",%progbits,0x1
^ 1: Special memory type.
|
'd' for SHF_GNU_MBIND.
.section .mbind.bar,"adG",%progbits,.foo_group,comdat,0x2
^ 2: Special memory type.
|
'd' for SHF_GNU_MBIND.
bfd/
* elf.c (get_program_header_size): Add a GNU_MBIND segment for
each GNU_MBIND section and align GNU_MBIND section to page size.
(_bfd_elf_map_sections_to_segments): Create a GNU_MBIND
segment for each GNU_MBIND section.
(_bfd_elf_init_private_section_data): Copy sh_info from input
for GNU_MBIND section.
binutils/
* NEWS: Mention support for ELF SHF_GNU_MBIND and
PT_GNU_MBIND_XXX.
* readelf.c (get_segment_type): Handle PT_GNU_MBIND_XXX.
(get_elf_section_flags): Handle SHF_GNU_MBIND.
(process_section_headers): Likewise.
* testsuite/binutils-all/mbind1.s: New file.
* testsuite/binutils-all/objcopy.exp: Run readelf test on
mbind1.s.
gas/
* NEWS: Mention support for ELF SHF_GNU_MBIND.
* config/obj-elf.c (section_match): New.
(get_section): Match both sh_info and group name.
(obj_elf_change_section): Add argument for sh_info. Pass both
sh_info and group name to get_section. Issue an error for
SHF_GNU_MBIND section without SHF_ALLOC. Set sh_info.
(obj_elf_parse_section_letters): Set SHF_GNU_MBIND for 'd'.
(obj_elf_section): Support SHF_GNU_MBIND section info.
* config/obj-elf.h (obj_elf_change_section): Add argument for
sh_info.
* config/tc-arm.c (start_unwind_section): Pass 0 as sh_info to
obj_elf_change_section.
* config/tc-ia64.c (obj_elf_vms_common): Likewise.
* config/tc-microblaze.c (microblaze_s_data): Likewise.
(microblaze_s_sdata): Likewise.
(microblaze_s_rdata): Likewise.
(microblaze_s_bss): Likewise.
* config/tc-mips.c (s_change_section): Likewise.
* config/tc-msp430.c (msp430_profiler): Likewise.
* config/tc-rx.c (parse_rx_section): Likewise.
* config/tc-tic6x.c (tic6x_start_unwind_section): Likewise.
* doc/as.texinfo: Document 'd' for SHF_GNU_MBIND.
* testsuite/gas/elf/elf.exp: Run section12a, section12b and
section13.
* testsuite/gas/elf/section10.d: Updated.
* testsuite/gas/elf/section10.s: Likewise.
* testsuite/gas/elf/section12.s: New file.
* testsuite/gas/elf/section12a.d: Likewise.
* testsuite/gas/elf/section12b.d: Likewise.
* testsuite/gas/elf/section13.l: Likewise.
* testsuite/gas/elf/section13.d: Likewise.
* testsuite/gas/elf/section13.s: Likewise.
include/
* elf/common.h (PT_GNU_MBIND_NUM): New.
(PT_GNU_MBIND_LO): Likewise.
(PT_GNU_MBIND_HI): Likewise.
(SHF_GNU_MBIND): Likewise.
ld/
* NEWS: Mention support for ELF SHF_GNU_MBIND and
PT_GNU_MBIND_XXX.
* emultempl/elf32.em (gld${EMULATION_NAME}_place_orphan): Place
input GNU_MBIND sections with the same type, attributes and
sh_info field into a single output GNU_MBIND section.
* testsuite/ld-elf/elf.exp: Run mbind2a and mbind2b.
* testsuite/ld-elf/mbind1.s: New file.
* testsuite/ld-elf/mbind1a.d: Likewise.
* testsuite/ld-elf/mbind1b.d: Likewise.
* testsuite/ld-elf/mbind1c.d: Likewise.
* testsuite/ld-elf/mbind2a.s: Likewise.
* testsuite/ld-elf/mbind2b.c: Likewise.
|
||
Palmer Dabbelt
|
b52920324f |
RISC-V: Resurrect GP-relative disassembly hints
We missed a "_gp" when changing the GP symbol. To make sure that
doesn't happen again, we now use the same definition everywhere (thanks,
Nick).
include/ChangeLog:
2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
* elf/riscv.h (RISCV_GP_SYMBOL): New define.
bfd/ChangeLog:
2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
* elfnn-riscv.c (GP_NAME): Delete.
(riscv_global_pointer_value): Change GP_NAME to RISCV_GP_SYMBOL.
(_bfd_riscv_relax_lui): Likewise.
opcodes/ChangeLog:
2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
* riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
RISCV_GP_SYMBOL.
|
||
Andrew Waterman
|
858f82bf7e |
RISC-V: Add physical memory protection CSRs
2017-03-27 Andrew Waterman <andrew@sifive.com>
* opcode/riscv-opc.h (CSR_PMPCFG0): New define.
(CSR_PMPCFG1): Likewise.
(CSR_PMPCFG2): Likewise.
(CSR_PMPCFG3): Likewise.
(CSR_PMPADDR0): Likewise.
(CSR_PMPADDR1): Likewise.
(CSR_PMPADDR2): Likewise.
(CSR_PMPADDR3): Likewise.
(CSR_PMPADDR4): Likewise.
(CSR_PMPADDR5): Likewise.
(CSR_PMPADDR6): Likewise.
(CSR_PMPADDR7): Likewise.
(CSR_PMPADDR8): Likewise.
(CSR_PMPADDR9): Likewise.
(CSR_PMPADDR10): Likewise.
(CSR_PMPADDR11): Likewise.
(CSR_PMPADDR12): Likewise.
(CSR_PMPADDR13): Likewise.
(CSR_PMPADDR14): Likewise.
(CSR_PMPADDR15): Likewise.
(pmpcfg0): Declare register.
(pmpcfg1): Likewise.
(pmpcfg2): Likewise.
(pmpcfg3): Likewise.
(pmpaddr0): Likewise.
(pmpaddr1): Likewise.
(pmpaddr2): Likewise.
(pmpaddr3): Likewise.
(pmpaddr4): Likewise.
(pmpaddr5): Likewise.
(pmpaddr6): Likewise.
(pmpaddr7): Likewise.
(pmpaddr8): Likewise.
(pmpaddr9): Likewise.
(pmpaddr10): Likewise.
(pmpaddr11): Likewise.
(pmpaddr12): Likewise.
(pmpaddr13): Likewise.
(pmpaddr14): Likewise.
(pmpaddr15): Likewise.
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Pip Cet
|
f96bd6c2d7 |
Add support for the WebAssembly file format and the wasm32 ELF conversion to gas and the binutils.
binutils * readelf.c: Add support for wasm32 ELF format WebAssembly files. (guess_is_rela): Likewise. (dump_relocations): Likewise. (is_32bit_abs_reloc): Likewise. (is_none_reloc_): Likewise. * NEWS: Mention the new support. * testsuite/lib/binutils-common.exp (is_elf_format): Mark wasm32 as ELF target. (supports_gnu_unique): Mark wasm32 as supporting STB_GNU_UNIQUE. * testsuite/binutils-all/nm.exp: Mark wasm32 as requiring .size annotations. * testsuite/binutils-all/wasm32: New directory. * testsuite/binutils-all/wasm32/create-wasm.d: New file. * testsuite/binutils-all/wasm32/create-wasm.s: Likewise. * testsuite/binutils-all/wasm32/custom-section.d: Likewise. * testsuite/binutils-all/wasm32/custom-section.s: Likewise. * testsuite/binutils-all/wasm32/invalid-wasm-1.d: Likewise. * testsuite/binutils-all/wasm32/invalid-wasm-1.s: Likewise. * testsuite/binutils-all/wasm32/long-sections.d: Likewise. * testsuite/binutils-all/wasm32/long-sections.s: Likewise. * testsuite/binutils-all/wasm32/parse-wasm.d: Likewise. * testsuite/binutils-all/wasm32/parse-wasm.s: Likewise. * testsuite/binutils-all/wasm32/parse-wasm-2.d: Likewise. * testsuite/binutils-all/wasm32/parse-wasm-2.s: Likewise. * testsuite/binutils-all/wasm32/prepared-section.d: Likewise. * testsuite/binutils-all/wasm32/prepared-section.s: Likewise. * testsuite/binutils-all/wasm32/wasm32.exp: New file, run tests. gas * config/tc-wasm32.h: New file: Add WebAssembly assembler target. * config/tc-wasm32.c: New file: Add WebAssembly assembler target. * Makefile.am: Add WebAssembly assembler target. * configure.tgt: Add WebAssembly assembler target. * doc/c-wasm32.texi: New file: Start documenting WebAssembly assembler. * doc/all.texi: Define WASM32. * doc/as.texinfo: Add WebAssembly entries. * NEWS: Mention the new support. * Makefile.in: Regenerate. * po/gas.pot: Regenerate. * po/POTFILES.in: Regenerate. * testsuite/gas/wasm32: New directory. * testsuite/gas/wasm32/allinsn.d: New file. * testsuite/gas/wasm32/allinsn.s: New file. * testsuite/gas/wasm32/illegal.l: New file. * testsuite/gas/wasm32/illegal.s: New file. * testsuite/gas/wasm32/illegal-2.l: New file. * testsuite/gas/wasm32/illegal-2.s: New file. * testsuite/gas/wasm32/illegal-3.l: New file. * testsuite/gas/wasm32/illegal-3.s: New file. * testsuite/gas/wasm32/illegal-4.l: New file. * testsuite/gas/wasm32/illegal-4.s: New file. * testsuite/gas/wasm32/illegal-5.l: New file. * testsuite/gas/wasm32/illegal-5.s: New file. * testsuite/gas/wasm32/illegal-6.l: New file. * testsuite/gas/wasm32/illegal-6.s: New file. * testsuite/gas/wasm32/illegal-7.l: New file. * testsuite/gas/wasm32/illegal-7.s: New file. * testsuite/gas/wasm32/illegal-8.l: New file. * testsuite/gas/wasm32/illegal-8.s: New file. * testsuite/gas/wasm32/illegal-9.l: New file. * testsuite/gas/wasm32/illegal-9.s: New file. * testsuite/gas/wasm32/illegal-10.l: New file. * testsuite/gas/wasm32/illegal-10.s: New file. * testsuite/gas/wasm32/illegal-11.l: New file. * testsuite/gas/wasm32/illegal-11.s: New file. * testsuite/gas/wasm32/illegal-12.l: New file. * testsuite/gas/wasm32/illegal-12.s: New file. * testsuite/gas/wasm32/illegal-13.l: New file. * testsuite/gas/wasm32/illegal-13.s: New file. * testsuite/gas/wasm32/illegal-14.l: New file. * testsuite/gas/wasm32/illegal-14.s: New file. * testsuite/gas/wasm32/illegal-15.l: New file. * testsuite/gas/wasm32/illegal-15.s: New file. * testsuite/gas/wasm32/illegal-16.l: New file. * testsuite/gas/wasm32/illegal-16.s: New file. * testsuite/gas/wasm32/illegal-17.l: New file. * testsuite/gas/wasm32/illegal-17.s: New file. * testsuite/gas/wasm32/illegal-18.l: New file. * testsuite/gas/wasm32/illegal-18.s: New file. * testsuite/gas/wasm32/illegal-19.l: New file. * testsuite/gas/wasm32/illegal-19.s: New file. * testsuite/gas/wasm32/illegal-20.l: New file. * testsuite/gas/wasm32/illegal-20.s: New file. * testsuite/gas/wasm32/illegal-21.l: New file. * testsuite/gas/wasm32/illegal-21.s: New file. * testsuite/gas/wasm32/illegal-22.l: New file. * testsuite/gas/wasm32/illegal-22.s: New file. * testsuite/gas/wasm32/illegal-24.l: New file. * testsuite/gas/wasm32/illegal-24.s: New file. * testsuite/gas/wasm32/illegal-25.l: New file. * testsuite/gas/wasm32/illegal-25.s: New file. * testsuite/gas/wasm32/reloc.d: New file. * testsuite/gas/wasm32/reloc.s: New file. * testsuite/gas/wasm32/wasm32.exp: New tests for WebAssembly architecture. opcodes * configure.ac: Add (empty) bfd_wasm32_arch target. * configure: Regenerate * po/opcodes.pot: Regenerate. include * opcode/wasm.h: New file to support wasm32 architecture. * elf/wasm32.h: Add R_WASM32_32 relocation. bfd * elf32-wasm32.c: Add relocation code, two relocs. * reloc.c: Add wasm32 relocations. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate. * bfd/po/bfd.pot: Regenerate. |
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Alan Modra
|
52be03fd13 |
PowerPC -Mraw disassembly
This adds -Mraw for PowerPC objdump, a disassembler option to display the underlying machine instruction rather than aliases. For example, "rlwinm" always rather than "rotlwi" when the instruction is performing a simple rotate. binutils/ * doc/binutils.texi (objdump): Document PowerPC -M options. gas/ * config/tc-ppc.c (md_parse_option): Reject -mraw. include/ * opcode/ppc.h (PPC_OPCODE_RAW): Define. (PPC_OPCODE_*): Make them all unsigned long long constants. opcodes/ * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add "raw" option. (lookup_powerpc): Don't special case -1 dialect. Handle PPC_OPCODE_RAW. (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first lookup_powerpc call, pass it on second. |
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|
Pip Cet
|
8fb740dd30 |
Add minimal support for WebAssembly backend to the BFD library.
include * elf/wasm32.h: New file to support wasm32 architecture.
bfd * cpu-wasm32.c: New file to support wasm32 architecture.
* elf32-wasm32.c: New file to support wasm32 architecture.
* Makefile.am: Add wasm32 architecture.
* archures.c: Likewise.
* config.bfd: Likewise.
* configure.ac: Likewise.
* targets.c: Likewise.
|
||
Rinat Zelig
|
c0c31e91ad |
Implement ARC NPS-400 Ultra Ip and Miscellaneous instructions.
opcodes * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
* arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR, F_NPS_M, F_NPS_CORE, F_NPS_ALL.
(insert_nps_misc_imm_offset): New function.
(extract_nps_misc imm_offset): New function.
(arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
(arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
include * opcode/arc.h (insn_class_t): Add ULTRAIP and MISC class.
gas * testsuite/gas/arc/nps400-12.s: New file.
* testsuite/gas/arc/nps400-12.d: New file.
|
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|
Andreas Krebbel
|
2253c8f089 |
S/390: Remove vx2 facility flag
This patch removes the vx2 facility flag. It will not be used by GCC and was a misnomer anyway. Committed to mainline and 2.28 branch. include/ChangeLog: 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * opcode/s390.h (S390_INSTR_FLAG_VX2): Remove. (S390_INSTR_FLAG_FACILITY_MASK): Adjust value. gas/ChangeLog: 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config/tc-s390.c (s390_parse_cpu): Remove S390_INSTR_FLAG_VX2 from cpu_table. Remove vx2, and novx2 from cpu_flags. opcodes/ChangeLog: 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * s390-mkopc.c (main): Remove vx2 check. * s390-opc.txt: Remove vx2 instruction flags. |