which use '0', '1', and '2' instead. Specify the proper size for
a pmove immediate operand. Correct the pmovefd patterns to be
moves to a register, not from a register.
* m68k-dis.c (print_insn_arg): Replace 'P' with '0', '1', '2'.
Subsitute CFLAGS and AR. Call AC_PROG_INSTALL. Don't substitute
host_makefile_frag or frags.
* aclocal.m4: New file.
* configure: Rebuild.
* Makefile.in (INSTALL): Set to @INSTALL@.
(INSTALL_PROGRAM): Set to @INSTALL_PROGRAM@.
(INSTALL_DATA): Set to @INSTALL_DATA@.
(AR): Set to @AR@.
(AR_FLAGS): Set to rc rather than qc.
(CC): Define as @CC@.
(CFLAGS): Set to @CFLAGS@.
(@host_makefile_frag@): Remove.
(config.status): Remove dependency upon @frags@.
(reg_names): Likewise.
(print_insn_arg): Don't explicitly print % before register names.
Add % before register names in static array names. In case 'r',
print data registers as `@(Dn)', not `Dn@'. When printing a
memory address, don't print @# before it.
(print_indexed): Change base_disp and outer_disp from int to
bfd_vma. Print using MIT syntax, not mutant invalid Motorola
syntax. Sign extend 8 byte displacement correctly.
(print_base): Print using MIT syntax. Print zpc when appropriate.
Change parameter disp from int to bfd_vma.
F_REG_M, FPSCR_M, FPSCR_N, FPUL_M and FPUL_N.
* sh-opc.h (sh_arg_type): Add new operand types.
(sh_table): Add new opcodes from SH3E Floating Point ISA.
sh3e stuff. Sanitized out for now.
(opcode_bits, opcode_hash_table, sparc64_p): New variables.
(opcodes_initialized): Renamed from opcodes_sorted.
(build_hash_table): New function.
(is_delayed_branch): Use hash table.
(print_insn): Renamed from print_insn_sparc, made static.
Build and use hash table.
(print_insn_sparc, print_insn_sparc64): New functions.
(compare_opcodes): If !sparc64, move sparc64 opcodes to end,
and vice-versa if sparc64.
* sparc-opc.c (all non-v9 insns): Use flag F_NOTV9 instead of F_ALIAS.
* mips-opc.c (L1): Define.
(mips_opcodes): Add R4010 instructions: flushi, flushd, flushid,
addciu, madd, maddu, ffc, ffs, msub, msubu, selsi, selsr, waiti,
and wb.
Tue Jul 11 11:49:49 1995 Ian Lance Taylor <ian@cygnus.com>
* mips-opc.c (mips_opcodes): For the move pseudo-op, prefer daddu
if ISA 3 and addu otherwise, replacing or, since some MIPS chips
have multiple add units but only a single logical unit.
bfd_vma to unsigned long, because _print_insn_mips expects an unsigned long,
and that might be fewer words of argument storage (e.g., if bfd_vma is long
long on a 32-bit machine).
(print_insn_big_mips): Likewise with bfd_getb32 value.
(_print_insn_mips): Now static.
Call arc_get_opcode_mach to map bfd mach number to opcode value.
(print_insn_*): Pass bfd mach number, not opcode version.
* arc-opc.c (arc_get_opcode_mach): New function.
* alpha-opc.h (OSF_ASMCODE): define print pal-code names as defined in App C of
the Alpha Architecture Reference Manual
* alpha-dis.c: cleaned up output print stylized code forms as defined in App
A.4.3 of the Alpha Architecture Reference Manual
(print_insn_arc_{host,graphics,audio}): Likewise.
(print_insn): Add prototype.
Delete "+ 4" addition to relative branch address.
(arc_get_disassembler): New arg `big_p'. Return little or big
print fn accordingly.
* arc-opc.c (arc_opcode_init_tables): Init arc_operand_map once.
(arc_opcode_supported): Use ARC_OPCODE_CPU to ignore byte order.
(arc_opval_supported): Likewise.
* disassemble.c (disassembler): Pass big endian flag to
arc_get_disassembler.
