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8817 Commits

Author SHA1 Message Date
Max Filippov
c0b4cd4655 xtensa: gas: add relaxations tests 
gas/
2019-04-11  Max Filippov  <jcmvbkbc@gmail.com>

	* testsuite/gas/xtensa/loop-relax-2.d: New test definition.
	* testsuite/gas/xtensa/loop-relax.d: New test definition.
	* testsuite/gas/xtensa/loop-relax.s: New test source.
	* testsuite/gas/xtensa/text-section-literals-1a.d: New test
	definition.
	* testsuite/gas/xtensa/text-section-literals-2.d: New test
	definition.
	* testsuite/gas/xtensa/text-section-literals-2.s: New test
	source.
	* testsuite/gas/xtensa/text-section-literals-2a.d: New test
	definition.
	* testsuite/gas/xtensa/text-section-literals-3.d: New test
	definition.
	* testsuite/gas/xtensa/text-section-literals-3.s: New test
	source.
	* testsuite/gas/xtensa/text-section-literals-4.d: New test
	definition.
	* testsuite/gas/xtensa/text-section-literals-4.s: New test
	source.
	* testsuite/gas/xtensa/text-section-literals-4a.d: New test
	definition.
 2019-04-11 11:42:12 -07:00
Max Filippov
6f2b771531 xtensa: gas: convert tests to run_dump_tests 
gas/
2019-04-11  Max Filippov  <jcmvbkbc@gmail.com>

	* testsuite/gas/xtensa/all.exp: Remove all expect-based
	tests and all explicit run_dump_test / run_list_test
	invocations. Add run_dump_tests for all .d files in the
	test subdirectory.
	* testsuite/gas/xtensa/entry_align.d: New test definition.
	* testsuite/gas/xtensa/entry_align.l: New test output.
	* testsuite/gas/xtensa/entry_misalign.d: New test definition.
	* testsuite/gas/xtensa/entry_misalign2.d: New test definition.
	* testsuite/gas/xtensa/j_too_far.d: New test definition.
	* testsuite/gas/xtensa/j_too_far.l: New test output.
	* testsuite/gas/xtensa/loop_align.d: New test definition.
	* testsuite/gas/xtensa/loop_misalign.d: New test definition.
	* testsuite/gas/xtensa/trampoline-2.d: New test definition.
	* testsuite/gas/xtensa/trampoline-2.l: Remove empty output.
	* testsuite/gas/xtensa/xtensa-err.exp: Use positive logic.
 2019-04-11 11:41:36 -07:00
Max Filippov
f8aecf3cc9 xtensa: gas: clean up literal management code 
gas/
2019-04-11  Max Filippov  <jcmvbkbc@gmail.com>

	* config/tc-xtensa.c (xtensa_literal_pseudo): Drop code that has
	no effect.
	(get_literal_pool_location): Only search for the literal pool
	when auto litpools is used, otherwise take one recorded in the
	tc_segment_info_data.
	(xtensa_assign_litpool_addresses): New function.
	(xtensa_move_literals): Don't duplicate 'literal pool location
	required...' error message. Call xtensa_assign_litpool_addresses.
 2019-04-11 11:40:52 -07:00
Max Filippov
548791769d xtensa: gas: put .literal_position at section start 
Provide literal position at the beginning of each section for literal
space reserved by relaxations when text-section-literals or
auto-litpools options are used. Remove code that adds fill frag to the
literal section for every .literal_position directive to avoid creation
of empty literal sections.

Fix auto-litpools tests that got literal pool address changes.

gas/
2019-04-11  Max Filippov  <jcmvbkbc@gmail.com>

	* config/tc-xtensa.c (xtensa_is_init_fini): Add declaration.
	(xtensa_mark_literal_pool_location): Don't add fill frag to literal
	section that records literal pool location.
	(md_begin): Call xtensa_mark_literal_pool_location when text
	section literals or auto litpools are used.
	(xtensa_elf_section_change_hook): Call
	xtensa_mark_literal_pool_location when text section literals or
	auto litpools are used, there's no literal pool location defined
	for the current section and it's not .init or .fini.
	* testsuite/gas/xtensa/auto-litpools-first1.d: Fix up addresses.
	* testsuite/gas/xtensa/auto-litpools-first2.d: Likewise.
	* testsuite/gas/xtensa/auto-litpools.d: Likewise.
 2019-04-11 11:40:07 -07:00
Sudakshina Das
bd7ceb8d26 [BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructions 
This patch updates the Store allocation tags instructions in
Armv8.5-A Memory Tagging Extension. This is part of the changes
that have been introduced recently in the 00bet10 release

All of these instructions have an updated register operand (Xt -> <Xt|SP>)

- STG <Xt|SP>, [<Xn|SP>, #<simm>]
- STG <Xt|SP>, [<Xn|SP>, #<simm>]!
- STG <Xt|SP>, [<Xn|SP>], #<simm>
- STZG <Xt|SP>, [<Xn|SP>, #<simm>]
- STZG <Xt|SP>, [<Xn|SP>, #<simm>]!
- STZG <Xt|SP>, [<Xn|SP>], #<simm>
- ST2G <Xt|SP>, [<Xn|SP>, #<simm>]
- ST2G <Xt|SP>, [<Xn|SP>, #<simm>]!
- ST2G <Xt|SP>, [<Xn|SP>], #<simm>
- STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]
- STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]!
- STZ2G <Xt|SP>, [<Xn|SP>], #<simm>

In order to accept <Rt|SP> a new operand type Rt_SP is introduced which has
the same field as FLD_Rt but follows other semantics of Rn_SP.

*** gas/ChangeLog ***

2019-04-11  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-aarch64.c (process_omitted_operand): Add case for
	AARCH64_OPND_Rt_SP.
	(parse_operands): Likewise.
	* testsuite/gas/aarch64/armv8_5-a-memtag.d: Update tests.
	* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.s: Likewise.

*** include/ChangeLog ***

2019-04-11  Sudakshina Das  <sudi.das@arm.com>

	* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rt_SP.

*** opcodes/ChangeLog ***

2019-04-11  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-opc.c (aarch64_print_operand): Add case for
	AARCH64_OPND_Rt_SP.
	(verify_constraints): Likewise.
	* aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
	(struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
	to accept Rt|SP as first operand.
	(AARCH64_OPERANDS): Add new Rt_SP.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.
 2019-04-11 10:19:37 +01:00
Sudakshina Das
e54010f1ae [BINUTILS, AArch64, 1/2] Add new LDGM/STGM instruction 
This patch adds the new LDGM/STGM instructions of the
Armv8.5-A Memory Tagging Extension. This is part of the changes
that have been introduced recently in the 00bet10 release

The instructions are as follows:
LDGM Xt, [<Xn|SP>]
STGM Xt, [<Xn|SP>]

*** gas/ChangeLog ***

2019-04-11  Sudakshina Das  <sudi.das@arm.com>

	* testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for ldgm and stgm.
	* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.s: Likewise.

*** opcodes/ChangeLog ***

2019-04-11  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Likewise.
	* aarch64-opc-2.c: Likewise.
	* aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 2019-04-11 10:13:23 +01:00
Rainer Orth
a5def729be Disable R_X86_64_PLT32 generation as branch marker on Solaris/x86 
The fix H.J. implemented for PR gas/22791 in the thread starting at

	[PATCH] x86-64: Treat PC32 relocation with branch as PLT32
	https://sourceware.org/ml/binutils/2018-02/msg00065.html

is causing problems on Solaris/x86.  The native linker is strongly
preferred there, and there's no intention of implementing the linker
optimization he plans there.  Besides, the kernel runtime linker,
otherwise has no need to deal with that reloc at all, and instead of
adding (possibly even more) workarounds with no benefit, it seems
appropriate to disable the R_X86_64_PLT32 generation as branch marker on
Solaris/x86 in the first place.

The patch itself is trivial, the only complication is adapting the
testsuite.  Since I've found no way to have conditional sections in the
.d files, I've instead used the solution already found elsewhere of
having separate .d files for the affected tests in an i386/solaris
subdirectory and skipping the original ones.

Tested on amd64-pc-solaris2.11 and x86_64-pc-linux-gnu without
regressions.

	* config/tc-i386.c (need_plt32_p) [TE_SOLARIS]: Return FALSE.
	* testsuite/gas/i386/solaris/solaris.exp: New driver.
	* testsuite/gas/i386/solaris/reloc64.d,
	testsuite/gas/i386/solaris/x86-64-jump.d,
	testsuite/gas/i386/solaris/x86-64-mpx-branch-1.d,
	testsuite/gas/i386/solaris/x86-64-mpx-branch-2.d,
	testsuite/gas/i386/solaris/x86-64-nop-3.d,
	testsuite/gas/i386/solaris/x86-64-nop-4.d,
	testsuite/gas/i386/solaris/x86-64-nop-5.d,
	testsuite/gas/i386/solaris/x86-64-relax-2.d,
	testsuite/gas/i386/solaris/x86-64-relax-3.d: New tests.
	* testsuite/gas/i386/reloc64.d,
	testsuite/gas/i386/x86-64-jump.d,
	testsuite/gas/i386/x86-64-mpx-branch-1.d,
	testsuite/gas/i386/x86-64-mpx-branch-2.d,
	testsuite/gas/i386/x86-64-nop-3.d,
	testsuite/gas/i386/x86-64-nop-4.d,
	testsuite/gas/i386/x86-64-nop-5.d,
	testsuite/gas/i386/x86-64-relax-2.d,
	testsuite/gas/i386/x86-64-relax-3.d: Skip on *-*-solaris*.
 2019-04-10 09:48:43 +02:00
Alan Modra
12400dcc0f te-cloudabi.h 
This patch is aimed a fixing large numbers of x86_64-cloudabi failures
caused by gas selecting the wrong target name.

	* config/te-cloudabi.h: New file.
	* config/tc-aarch64.c (aarch64_after_parse_args): Use TE_CLOUDABI
	rather than TARGET_OS to select cloudabi.
	* config/tc-i386.h (ELF_TARGET_FORMAT64): Define for TE_CLOUDABI.
	* configure.tgt (*-*-cloudabi*): Set em=cloudabi.
 2019-04-10 13:27:29 +09:30
Robert Suchanek
7e96e219a4 [MIPS] Add RDHWR with the SEL field for MIPS R6. 
In Release 6 of the MIPS architecture [1], instruction RDHWR supports
a 3rd operand to serve as the 3-bit select field for the hardware
register.

[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
    Instruction Set Manual", Imagination Technologies Ltd., Document
    Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
    "Alphabetical List of Instructions", pp. 332-334

opcodes/
	* mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.

gas/
	* testsuite/gas/mips/mips.exp: Run hwr-names test.
	* testsuite/gas/mips/hwr-names.s: Add test cases for RDHWR with
	the SEL field.
	* testsuite/gas/mips/mipsr6@hwr-names.d: New file.
 2019-04-09 09:56:48 +00:00
H.J. Lu
462cac5884 x86: Define GNU_PROPERTY_X86_ISA_1_AVX512_BF16 
Update assembler and readelf to support

 #define GNU_PROPERTY_X86_ISA_1_AVX512_BF16  (1U << 24)

for AVX512_BF16.

binutils/

	* readelf.c (decode_x86_isa): Handle
	GNU_PROPERTY_X86_ISA_1_AVX512_BF16.
	* testsuite/binutils-all/i386/pr21231b.d: Updated.
	* testsuite/binutils-all/x86-64/pr21231b.d: Likewise.

gas/

	* config/tc-i386.c (output_insn): Support
	GNU_PROPERTY_X86_ISA_1_AVX512_BF16.
	* testsuite/gas/i386/property-2.s: Add AVX512_BF16 test.
	* testsuite/gas/i386/property-2.d: Updated.
	* testsuite/gas/i386/x86-64-property-2.d: Likewise.

include/

	* elf/common.h (GNU_PROPERTY_X86_ISA_1_AVX512_BF16): New.
 2019-04-08 17:04:16 -07:00
H.J. Lu
3ae61bb67d x86: Remove i386-*-kaos* and i386-*-chaos targets 
Remove i386-*-kaos* and i386-*-chaos targets since they are no longer
supported by config.sub:

$ .../config.sub i386-kaos
Invalid configuration `i386-kaos': system `kaos' not recognized
$ .../config.sub i386-chaos
Invalid configuration `i386-chaos': system `chaos' not recognized
$

bfd/

	* config.bfd: Remove i[3-7]86-*-kaos* and i[3-7]86-*-chaos targets.

gas/

	* configure.tgt: Remove i386-*-kaos* and i386-*-chaos targets.
	* testsuite/gas/i386/i386.exp: Remove *-*-caos* and "*-*-kaos*
	check.

ld/

	* Makefile.am (ALL_EMULATION_SOURCES): Remove eelf_i386_chaos.c.
	(eelf_i386_chaos.c): Removed.
	* Makefile.in: Regenerated.
	* configure.tgt: Remove i[3-7]86-*-kaos*.
	* emulparams/elf_i386_chaos.sh: Removed.
 2019-04-08 11:58:51 -07:00
H.J. Lu
4ef40579f9 x86: Add assembler -mx86-used-note=yes test 
Check assembler -mx86-used-note=yes option and readelf -n output.

	* testsuite/gas/i386/i386.exp: Run -mx86-used-note=yes tests.
	* testsuite/gas/i386/property-2.d: New file.
	* testsuite/gas/i386/property-2.s: Likewise.
	* testsuite/gas/i386/x86-64-property-2.d: Likewise.
 2019-04-05 12:43:18 -07:00
Xuepeng Guo
d6aab7a11b x86: Support Intel AVX512 BF16 
Add assembler and disassembler support Intel AVX512 BF16:

https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference

gas/

2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>

	* config/tc-i386.c (cpu_arch): Add .avx512_bf16.
	(cpu_noarch): Add noavx512_bf16.
	* doc/c-i386.texi: Document avx512_bf16.
	* testsuite/gas/i386/avx512_bf16.d: New file.
	* testsuite/gas/i386/avx512_bf16.s: Likewise.
	* testsuite/gas/i386/avx512_bf16_vl-inval.l: Likewise.
	* testsuite/gas/i386/avx512_bf16_vl-inval.s: Likewise.
	* testsuite/gas/i386/avx512_bf16_vl.d: Likewise.
	* testsuite/gas/i386/avx512_bf16_vl.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512_bf16.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512_bf16.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.l: Likesie.
	* testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512_bf16_vl.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512_bf16_vl.s: Likewise.
	* testsuite/gas/i386/i386.exp: Add BF16 related tests.

opcodes/

2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>

	* i386-dis-evex.h (evex_table): Updated to support BF16
	instructions.
	* i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
	and EVEX_W_0F3872_P_3.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
	(cpu_flags): Add bitfield for CpuAVX512_BF16.
	* i386-opc.h (enum): Add CpuAVX512_BF16.
	(i386_cpu_flags): Add bitfield for cpuavx512_bf16.
	* i386-opc.tbl: Add AVX512 BF16 instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
 2019-04-05 11:03:13 -07:00
Alan Modra
bec858ea4d PowerPC conditional branch test 
Adds a new test checking conditional branch BO values.

	* testsuite/gas/ppc/bc.s,
	* testsuite/gas/ppc/bcat.d,
	* testsuite/gas/ppc/bcaterr.d,
	* testsuite/gas/ppc/bcaterr.l,
	* testsuite/gas/ppc/bcy.d,
	* testsuite/gas/ppc/bcyerr.d,
	* testsuite/gas/ppc/bcyerr.l: New tests.
	* testsuite/gas/ppc/ppc.exp: Run them.
 2019-04-05 12:20:49 +10:30
Alan Modra
c2b1c27545 PowerPC disassembler: Don't emit trailing spaces 
When an instruction has operands, the PowerPC disassembler prints
spaces after the opcode so as to line up operands.  If the operands
are all optional and all default value, then no operands are printed,
leaving trailing spaces.  This patch fixes that.

opcodes/
	* ppc-dis.c (print_insn_powerpc): Delay printing spaces after
	opcode until first operand is output.
gas/
	* testsuite/gas/ppc/476.d: Remove trailing spaces.
	* testsuite/gas/ppc/a2.d: Likewise.
	* testsuite/gas/ppc/booke.d: Likewise.
	* testsuite/gas/ppc/booke_xcoff.d: Likewise.
	* testsuite/gas/ppc/e500.d: Likewise.
	* testsuite/gas/ppc/e500mc.d: Likewise.
	* testsuite/gas/ppc/e6500.d: Likewise.
	* testsuite/gas/ppc/htm.d: Likewise.
	* testsuite/gas/ppc/power6.d: Likewise.
	* testsuite/gas/ppc/power8.d: Likewise.
	* testsuite/gas/ppc/power9.d: Likewise.
	* testsuite/gas/ppc/vle.d: Likewise.
ld/
	* testsuite/ld-powerpc/tlsexe32.d: Remove trailing spaces.
	* testsuite/ld-powerpc/tlsopt5.d: Likewise.
	* testsuite/ld-powerpc/tlsopt5_32.d: Likewise.
 2019-04-05 12:20:49 +10:30
Peter Bergner
aae9718e4d Add extended mnemonics for bctar. Fix setting of 'at' branch hints. 
opcodes/
	PR gas/24349
	* ppc-opc.c (valid_bo_pre_v2): Add comments.
	(valid_bo_post_v2): Add support for 'at' branch hints.
	(insert_bo): Only error on branch on ctr.
	(get_bo_hint_mask): New function.
	(insert_boe): Add new 'branch_taken' formal argument.  Add support
	for inserting 'at' branch hints.
	(extract_boe): Add new 'branch_taken' formal argument.  Add support
	for extracting 'at' branch hints.
	(insert_bom, extract_bom, insert_bop, extract_bop): New functions.
	(BOE): Delete operand.
	(BOM, BOP): New operands.
	(RM): Update value.
	(XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
	(powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
	bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
	(powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
	bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
	<bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
	bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
	bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
	bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
	bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
	bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
	bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
	bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
	beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
	bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
	buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
	bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
	bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
	bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
	bttarl+>: New extended mnemonics.

gas/
	PR gas/24349
	* testsuite/gas/ppc/power8.s: (bdnztar, bdnztarl, bdztar, bdztarl,
	btar, btarl, bdnztar-, bdnztarl-, bdnztar+, bdnztarl+, bdztar-,
	bdztarl-, bdztar+, bdztarl+, bgetar, bnltar, bgetarl, bnltarl,
	bletar, bngtar, bletarl, bngtarl, bnetar, bnetarl, bnstar, bnutar,
	bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-, bnltarl-, bletar-,
	bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-, bnstar-, bnutar-,
	bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+, bnltarl+, bletar+,
	bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+, bnstar+, bnutar+,
	bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl, beqtar,
	beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
	bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
	buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
	bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
	bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
	bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
	bttarl+): Add tests of extended mnemonics.
	* testsuite/gas/ppc/power8.d: Likewise.  Update previous bctar tests
	to expect new extended mnemonics.
	* testsuite/gas/ppc/a2.s: <bc, bc-, bc+, bcl, bcl-, bcl+>: Update test
	to not use illegal BO value.  Use a more convenient BI value.
	* testsuite/gas/ppc/a2.d: Update tests for new expect output.
 2019-04-04 09:00:29 -05:00
Max Filippov
403b0b61f6 gas: use literals/const16 for xtensa loop relaxation 
Loop opcode relaxation that uses addi/addmi doesn't work well with other
relaxations that may cause code movement. Instead of encoding fixed loop
end offset in the relaxed sequence use l32r or a pair of const16 to load
loop end address. This way the address of the loop end gets a relocation
record and it gets updated appropriately.

gas/
2019-04-03  Max Filippov  <jcmvbkbc@gmail.com>

	* config/tc-xtensa.c (convert_frag_immed): Drop
	convert_frag_immed_finish_loop invocation.
	(convert_frag_immed_finish_loop): Drop declaration and
	definition.
	* config/xtensa-relax.c (widen_spec_list): Replace loop
	widening that uses addi/addmi with widening that uses l32r
	and const16.
 2019-04-03 10:24:15 -07:00
Andre Vieira
34ef62f465 [GAS, Arm] CLI with architecture sensitive extensions 
This patch adds a new framework to add architecture sensitive extensions, like
GCC does.  This patch also implements all architecture extensions currently
available in GCC.

This framework works as follows.  To enable architecture sensitive extensions
for a particular architecture, that architecture must contain an ARM_ARCH_OPT2
entry in the 'arm_archs' table.  All fields here are the same as previous, with
the addition of a new extra field at the end to <name> it's extension table.
This <name>, corresponds to a <name>_ext_table of type 'struct arm_ext_table'.
This struct can be filled with three types of entries:

  ARM_ADD (string <ext>, arm_feature_set <enable_bits>), which means +<ext> will
      enable <enable_bits>
  ARM_REMOVE (string <ext>, arm_feature_set <disable_bits>), which means
      +no<ext> will disable <disable_bits>
  ARM_EXT (string <ext>, arm_feature_set <enable_bits>, arm_feature_set
      <disable_bits>), which means +<ext> will enable <enable_bits> and +no<ext>
      will disable <disable_bits> (this is to be used instead of adding an
      ARM_ADD and ARM_REMOVE for the same <ext>)

This patch does not disable the use of the old extensions, even if some of them
are duplicated in the new tables.  This is a "in-between-step" as we may want to
deprecate the old table of extensions in later patches.  For now, GAS will first
look for the +<ext> or +no<ext> in the new table and if no entry is found it
will continue searching in the old table, following old behaviour.  If only an
ARM_ADD or an ARM_REMOVE is defined for <ext> and +no<ext> or +<ext> resp. is
used then it also continues to search the old table for it.

A couple of caveats:
- This patch does not enable the use of these architecture extensions with the
'.arch_extension' directive.  This is future work that I will tend to later.
- This patch does not enable the use of these architecture extensions with the
-mcpu option.  This is future work that I will tend to later.
- This patch does not change the current behaviour when combining an
architecture extension and using -mfpu on the command-line.  The current
behaviour of GAS is to stage the union of feature bits enabled by both -march
and -mfpu.  GCC behaves differently here, so this is something we may want to
revisit on a later date.
 2019-04-01 10:43:32 +01:00
Alan Modra
96a86c01d1 PR24390, Don't decode mtfsb field as a cr field 
"mtfsb0 4*cr7+lt" doesn't make all that much sense, but unfortunately
glibc uses just that instead of "mtfsb0 28" to clear the fpscr xe bit.
So for backwards compatibility accept cr field expressions when
assembling mtfsb operands, but disassemble to a plain number.

	PR 24390
include/
	* opcode/ppc.h (PPC_OPERAND_CR_REG): Comment.
opcodes/
	* ppc-opc.c (BTF): Define.
	(powerpc_opcodes): Use for mtfsb*.
	* ppc-dis.c (print_insn_powerpc): Print fields with both
	PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
gas/
	* testsuite/gas/ppc/476.d: Update mtfsb*.
	* testsuite/gas/ppc/a2.d: Likewise.
 2019-03-28 15:21:05 +10:30
Alan Modra
86b0c8dda0 Remove strip_underscore from struct emulation 
This field is unused.  I would have liked to also remove
leading_underscore and fake_label_name but in an i386-elf/coff/aout
multi-obj setup those fields are used to select a different
fake_label_name for aout.

	* emul.h (struct emulation): Delete strip_underscore.
	* emul-target.h (emul_strip_underscore): Don't define.
	(emul_struct_name): Update initialization.
 2019-03-21 08:50:24 +10:30
Alan Modra
7553c869a9 Teach a few targets to resolve BFD_RELOC_8 
and tidy "forward" test.  I've removed some checks in d30v
md_apply_fix that have no business being there.  Any symbol problems
will be caught later in tc_gen_reloc, and overflow checking is done in
gas/write.c.

	* config/tc-d10v.c (md_apply_fix): Apply BFD_RELOC_8.
	* config/tc-pdp11.c (md_apply_fix): Likewise.
	* config/tc-d30v.c (md_apply_fix): Don't emit errors for BFD_RELOC_8,
	BFD_RELOC_16, and BFD_RELOC_64.
	* testsuite/gas/all/gas.exp: Move target exclusions for forward
	test, but not cr16, to..
	* testsuite/gas/all/forward.d: ..here, with explanation.  Remove
	d10v, d30v, and pdp11 xfails.
 2019-03-21 08:46:42 +10:30
H.J. Lu
392a59728b x86: Correct EVEX vector load/store optimization 
Update EVEX vector load/store optimization:

1. There is no need to check AVX since AVX2 is required for AVX512F.
2. We need to check both operands for ZMM register since AT&T syntax
may not set zmmword on the first operand.
3. Update Opcode_SIMD_IntD check and set.
4. Since the VEX prefix has 2 or 3 bytes, the EVEX prefix has 4 bytes,
EVEX Disp8 has 1 byte and VEX Disp32 has 4 bytes, we choose EVEX Disp8
over VEX Disp32.

	* config/tc-i386.c (optimize_encoding): Don't check AVX for
	EVEX vector load/store optimization.  Check both operands for
	ZMM register.  Update EVEX vector load/store opcode check.
	Choose EVEX Disp8 over VEX Disp32.
	* testsuite/gas/i386/optimize-1.d: Updated.
	* testsuite/gas/i386/optimize-1a.d: Likewise.
	* testsuite/gas/i386/optimize-2.d: Likewise.
	* testsuite/gas/i386/optimize-4.d: Likewise.
	* testsuite/gas/i386/optimize-5.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-2a.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-2b.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-5.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-6.d: Likewise.
	* testsuite/gas/i386/optimize-1.s: Add ZMM register load
	test.
	* testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
 2019-03-19 21:13:49 +08:00
H.J. Lu
7b1d7ca194 x86: Correct EVEX to 128-bit EVEX optimization 
Since not all AVX512F processors support AVX512VL, we can optimize
512-bit EVEX to 128-bit EVEX encoding for upper 16 vector registers
only when AVX512VL is enabled explicitly at command-line or via
".arch .avx512vl" directive.

	PR gas/24352
	* config/tc-i386.c (optimize_encoding): Check only
	cpu_arch_flags.bitfield.cpuavx512vl.
	* testsuite/gas/i386/i386.exp: Run x86-64-optimize-2b.
	* testsuite/gas/i386/x86-64-optimize-2.d: Revert the last
	change.
	* testsuite/gas/i386/x86-64-optimize-2b.d: New file.
	* testsuite/gas/i386/x86-64-optimize-2b.s: Likewise.
 2019-03-19 21:11:21 +08:00
H.J. Lu
89199bb5a0 ix86: Disable AVX512F when disabling AVX2 
Since AVX2 is required for AVX512F, we should disable AVX512F when AVX2
is disabled.

gas/

	PR gas/24359
	* testsuite/gas/i386/i386.exp: Change optimize-6a, optimize-7,
	x86-64-optimize-7a and x86-64-optimize-8 tests to run_list_test.
	Remove optimize-6c and x86-64-optimize-7c tests.
	* testsuite/gas/i386/noavx-3.l: Updated.
	* testsuite/gas/i386/noavx-4.d: Likewise.
	* testsuite/gas/i386/noavx-5.d: Likewise.
	* testsuite/gas/i386/noavx-3.s: Add AVX512F tests.
	* testsuite/gas/i386/noavx-4.s: Remove AVX512F tests.
	* testsuite/gas/i386/nosse-5.s: Likewise.
	* testsuite/gas/i386/optimize-6a.d: Removed.
	* testsuite/gas/i386/optimize-6c.d: Likewise.
	* testsuite/gas/i386/optimize-7.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-7a.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-7c.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-8.d: Likewise.
	* testsuite/gas/i386/optimize-6a.l: New file.
	* testsuite/gas/i386/optimize-6a.s: Likewise.
	* testsuite/gas/i386/optimize-7.l: Likewise.
	* testsuite/gas/i386/x86-64-optimize-7a.l: Likewise.
	* testsuite/gas/i386/x86-64-optimize-7a.s: Likewise.
	* testsuite/gas/i386/x86-64-optimize-8.l: Likewise.

opcodes/

	PR gas/24359
	* i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
	CPU_ANY_AVX2_FLAGS.
	* i386-init.h: Regenerated.
 2019-03-19 21:08:31 +08:00
Alan Modra
af60449c26 Use temp_ilp and restore_ilp in more places 
* as.c (macro_expr): Use temp_ilp and restore_ilp.
	* macro.c (buffer_and_nest): Likewise.
	* read.c (temp_ilp): Remove FIXME.
 2019-03-18 22:39:55 +10:30
Alan Modra
c6cdff46c9 Fix MRI mode testsuite failures 
These fails were introduced by git commit 2469b3c584 with the
inroduction of "input_from_string":
m68k-linux  FAIL: MRI structured for
m68k-linux  FAIL: MRI structured if
m68k-linux  FAIL: MRI structured repeat
m68k-linux  FAIL: MRI structured while

Since the m68k parser called expression() without setting
input_from_string, get_symbol_name rejected FAKE_LABEL_CHAR in names.

	* config/m68k-parse.y (yylex): Use temp_ilp and restore_ilp.
 2019-03-18 22:39:16 +10:30
H.J. Lu
a716e60cf9 x86: Pass -O0 to assembler for some tests 
* testsuite/gas/i386/att-regs.d: Pass -O0 to assembler.
	* testsuite/gas/i386/avx512bw-intel.d: Likewise.
	* testsuite/gas/i386/avx512bw.d: Likewise.
	* testsuite/gas/i386/avx512f-intel.d: Likewise.
	* testsuite/gas/i386/avx512f.d: Likewise.
	* testsuite/gas/i386/disp32.d: Likewise.
	* testsuite/gas/i386/intel-regs.d: Likewise.
	* testsuite/gas/i386/pseudos.d: Likewise.
	* testsuite/gas/i386/x86-64-disp32.d: Likewise.
	* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
 2019-03-18 09:19:45 +08:00
H.J. Lu
97ed31ae00 x86: Optimize EVEX vector load/store instructions 
When there is no write mask, we can encode lower 16 128-bit/256-bit
EVEX vector register load and store instructions as VEX vector register
load and store instructions with -O1.

gas/

	PR gas/24348
	* config/tc-i386.c (optimize_encoding): Encode 128-bit and
	256-bit EVEX vector register load/store instructions as VEX
	vector register load/store instructions for -O1.
	* doc/c-i386.texi: Update -O1 documentation.
	* testsuite/gas/i386/i386.exp: Run PR gas/24348 tests.
	* testsuite/gas/i386/optimize-1.s: Add tests for EVEX vector
	load/store instructions.
	* testsuite/gas/i386/optimize-2.s: Likewise.
	* testsuite/gas/i386/optimize-3.s: Likewise.
	* testsuite/gas/i386/optimize-5.s: Likewise.
	* testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
	* testsuite/gas/i386/x86-64-optimize-3.s: Likewise.
	* testsuite/gas/i386/x86-64-optimize-4.s: Likewise.
	* testsuite/gas/i386/x86-64-optimize-5.s: Likewise.
	* testsuite/gas/i386/x86-64-optimize-6.s: Likewise.
	* testsuite/gas/i386/optimize-1.d: Updated.
	* testsuite/gas/i386/optimize-2.d: Likewise.
	* testsuite/gas/i386/optimize-3.d: Likewise.
	* testsuite/gas/i386/optimize-4.d: Likewise.
	* testsuite/gas/i386/optimize-5.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-4.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-5.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-6.d: Likewise.
	* testsuite/gas/i386/optimize-7.d: New file.
	* testsuite/gas/i386/optimize-7.s: Likewise.
	* testsuite/gas/i386/x86-64-optimize-8.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-8.s: Likewise.

opcodes/

	PR gas/24348
	* i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
	vmovdqu16, vmovdqu32 and vmovdqu64.
	* i386-tbl.h: Regenerated.
 2019-03-18 08:58:19 +08:00
H.J. Lu
99112332cd x86: Encode 256-bit/512-bit VEX/EVEX insns with 128-bit VEX 
Since all AVX512 processors support AVX, we can encode 256-bit/512-bit
VEX/EVEX vector register clearing instructions with 128-bit VEX vector
register clearing instructions at -O1.

	* config/tc-i386.c (optimize_encoding): Encode 256-bit/512-bit
	VEX/EVEX vector register clearing instructions with 128-bit VEX
	vector register clearing instructions at -O1.
	* doc/c-i386.texi: Update -O1 and -O2 documentation.
	* testsuite/gas/i386/i386.exp: Run optimize-1a and
	x86-64-optimize-2a.
	* testsuite/gas/i386/optimize-1a.d: New file.
	* testsuite/gas/i386/x86-64-optimize-2a.d: Likewise.
 2019-03-18 03:51:50 +08:00
H.J. Lu
41fd2579f2 x86: Set optimize to INT_MAX for -Os 
Set optimize to INT_MAX, instead of -1, for -Os so that -Os will include
-O2 optimization.

	PR gas/24353
	* config/tc-i386.c (md_parse_option): Set optimize to INT_MAX
	for -Os.
	* testsuite/gas/i386/optimize-2.s: Add a test.
	* testsuite/gas/i386/x86-64-optimize-3.s: Likewise.
	* testsuite/gas/i386/optimize-2.d: Updated.
	* testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
 2019-03-17 07:49:06 +08:00
H.J. Lu
dd22218cf2 x86: Correctly optimize EVEX to 128-bit VEX/EVEX 
We can optimize 512-bit EVEX to 128-bit EVEX encoding for upper 16
vector registers only when AVX512VL is enabled.  We can't optimize
EVEX to 128-bit VEX encoding when AVX isn't enabled.

	PR gas/24352
	* config/tc-i386.c (optimize_encoding): Encode 512-bit EVEX
	with 128-bit VEX encoding only when AVX is enabled and with
	128-bit EVEX encoding only when AVX512VL is enabled.
	* testsuite/gas/i386/i386.exp: Run PR gas/24352 tests.
	* testsuite/gas/i386/optimize-6.s: New file.
	* testsuite/gas/i386/optimize-6a.d: Likewise.
	* testsuite/gas/i386/optimize-6b.d: Likewise.
	* testsuite/gas/i386/optimize-6c.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-7.s: Likewise.
	* testsuite/gas/i386/x86-64-optimize-7a.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-7b.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-7c.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-2.d: Updated.
 2019-03-17 07:25:22 +08:00
Li Hao
1c529385d9 Fix a potential illegal memory access whilt parsing an x86 insn. 
PR 24308
	* config/tc-i386.c (parse_insn): Check mnemp before using it to
	determine if a suffix can be trimmed.
 2019-03-15 11:58:05 +00:00
Christian Eggers
204f543cae dwarf2: Align relocation within .debug_line section 
All relocations specify a byte address.  As dwarf debug information is
organized in octets, some relocations may not be aligned.  While it
might be possible to define special relocations that operate at an
octet offset from their address, it's easier to ensure the relocations
are aligned by padding with "nop" statements.

In most dwarf sections this requirement is already fulfilled, only
relocations for symbol address within the .debug_line section can be
misaligned.

	* dwarf2dbg.c (out_set_addr): Align relocation within .debug_line.
 2019-03-13 13:29:35 +10:30
Christian Eggers
145c4477d2 dwarf2: Pad size of .debug_line section. 
As all dwarf debug information is organized in octets, the size of all
dwarf sections must be aligned to OCTETS_PER_BYTE.  Most DWARF sections
meet this requirement, only the .debug_line section can reach an
arbitrary octet size.

In order to align the size to a multiple of OCTETS_PER_BYTE, the section
is padded with "nop" statements at the end.

	* dwarf2dbg.c (out_debug_line): Pad size of .debug_line section.
 2019-03-13 13:29:35 +10:30
Christian Eggers
5c4e5fe61b dwarf2: Use octets for .debug_string offsets 
Like other dwarf2 offsets, also the string offsets in the .debug_info
section which points into the .debug_str section must be expressed in
octets instead of bytes.

	* dwarf2dbg.c (out_debug_str): Use octets for .debug_string pointers.
 2019-03-13 13:29:35 +10:30
Christian Eggers
38c24f42c9 dwarf2: Use octets for .debug_line prologue 
Like the u32 size field at the beginning of the section, also the
prologue size must be expressed in octets.

	* dwarf2dbg.c (out_debug_line): Use octets for .debug_line prologue.
 2019-03-13 13:29:35 +10:30
Christian Eggers
7235427998 dwarf2: Use octets for dwarf2 headers 
The content of the dwarf2 sections .debug_line, .debug_aranges and
.debug_info starts with an u32 containing the the size of the remaining
data.  According to the dwarf2 specification this value must be expressed
in octets instead of bytes.

	* dwarf2dbg.c (out_debug_line): Use octets for dwarf2 headers.
	(out_debug_aranges, out_debug_info): Likewise.
 2019-03-13 13:29:35 +10:30
Christian Eggers
d18d199917 Symbols with octets value 
Up to now, all symbol values are in units of bytes, where a "byte" can
consist of one or more octets (e.g. 8 bit or 16 bit).

Allow to specfiy that the "unit" of a newly created symbol is octets
(exactly 8 bit), instead of bytes.

	* symbols.h (symbol_temp_new_now_octets): Declare.
	(symbol_set_value_now_octets, symbol_octets_p): Declare.
	* symbols.c (struct symbol_flags): New member sy_octets.
	(symbol_temp_new_now_octets): New function.
	(resolve_symbol_value): Return octets instead of bytes if
	sy_octets is set.
	(symbol_set_value_now_octets): New function.
	(symbol_octets_p): New function.
 2019-03-13 13:29:28 +10:30
Christian Eggers
71250b94dc dwarf2: Fix calculation of line info offset 
The units of the value returned by "frag_now_fix()" and "size" do not
match. "frag_now_fix()" returns bytes (can be 8, 16 or 32 bit), while
"size" is octets (exactly 8 bit).

	* dwarf2dbg.c (dwarf2_emit_insn): Fix calculation of line info offset.
 2019-03-13 13:09:03 +10:30
Andreas Krebbel
0919bfe915 Add missing changelogs for previous commits. 2019-03-12 14:23:21 +01:00
Andreas Krebbel
40f382e88d S/390: arch13: Adjust to recent changes 
opcodes/ChangeLog:

2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>

	* s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
	from vstrszb, vstrszh, and vstrszf.

gas/ChangeLog:

2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>

	* testsuite/gas/s390/zarch-arch13.s: Adjust testcase to optable changes.
	* testsuite/gas/s390/zarch-arch13.d: Likewise.
 2019-03-12 14:13:01 +01:00
Matthew Malcomson
52d6f3ee94 Testsuite: Allow multiple lines of "as" in testsuite. 
Committed on behalf of Matthew Malcomson.

This allows checking the command line parsing more easily than before by
allowing many command line invokations from the same .d file.

Each line is used as a set of flags, and the tests are ran against the output
of the assembler with each set.
Each line of assembler is treated as another set of tests (as if the test file
were copied to another with a different #as: line).

This patch includes some example uses where multiple testcases can be merged
into one file using this new functionality.

binutils/ChangeLog:

	* testsuite/lib/binutils-common.exp: Allow multiple "as" lines.

gas/ChangeLog:

	* testsuite/gas/aarch64/dotproduct.d: Use multiple "as" lines.
	* testsuite/gas/aarch64/dotproduct_armv8_4.d: Remove.
	* testsuite/gas/aarch64/dotproduct_armv8_4.s: Remove.
	* testsuite/gas/aarch64/illegal-dotproduct.d: Use multiple "as"
	lines.
	* testsuite/gas/aarch64/ldst-rcpc-armv8_2.d: Remove.
	* testsuite/gas/aarch64/ldst-rcpc.d: Use multiple "as" lines.
 2019-02-27 13:16:14 +00:00
Alan Modra
a894d76ab1 Re: PowerPC __tls_get_addr arg parsing 
Fixes non-ELF powerpc build failure:
tc-ppc.c:3009:1: error: ‘parse_tls_arg’ defined but not used

	* config/tc-ppc.c (parse_tls_arg): Wrap in #ifdef OBJ_ELF.
 2019-02-24 18:57:13 +10:30
Alan Modra
f616c36b79 PR24144, pdp11-ld overwriting section data with zeros 
bfd/
	PR 24144
	* pdp11.c (set_section_contents): Revert 2015-02-24 change.
gas/
	PR 24144
	* config/obj-aout.c (obj_aout_frob_file_before_fix): Write to end
	of section to ensure file contents cover aligned section size.
 2019-02-24 18:57:04 +10:30
Kyrylo Tkachov
83f43c8344 [arm][gas] Add support for Neoverse N1 
This adds support for the Neoverse N1 CPU [1] to gas.
This was previously enabled under the Ares codename, which remains as
a valid option for -mcpu for compatibility reasons.

make check-gas passes on arm-none-eabi.

[1] https://community.arm.com/processors/b/blog/posts/arm-neoverse-n1-platform-accelerating-the-transformation-to-a-scalable-cloud-to-edge-infrastructure

2019-02-21  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

    * config/tc-arm.c (arm_cpus): Add neoverse-n1.
    * doc/c-arm.texi (-mcpu): Document neoverse-n1 value.
 2019-02-22 09:59:05 +00:00
Kyrylo Tkachov
516dbc4418 [AArch64][gas] Add support for Neoverse E1 
This adds support for the Neoverse E1 CPU [1] to gas.

make check-gas passes on aarch64-none-elf.

[1] https://community.arm.com/processors/b/blog/posts/arm-neoverse-e1-platform-empowering-the-infrastructure-to-meet-next-generation-throughput-demands

2019-02-21  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

    * config/tc-aarch64.c (aarch64_cpus): Add neoverse-e1.
    * doc/c-aarch64.texi (-mcpu): Document neoverse-e1 value.
 2019-02-22 09:57:45 +00:00
Kyrylo Tkachov
38e75bf223 [AArch64][gas] Add support for Neoverse N1 
This adds support for the Neoverse N1 [1] CPU to gas.
This was previously enabled under the Ares codename, which remains as
a valid option for -mcpu for compatibility reasons.

make check-gas passes on aarch64-none-elf.

[1] https://community.arm.com/processors/b/blog/posts/arm-neoverse-n1-platform-accelerating-the-transformation-to-a-scalable-cloud-to-edge-infrastructure

2019-02-21  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

    * config/tc-aarch64.c (aarch64_cpus): Add neoverse-n1.
    * doc/c-aarch64.texi (-mcpu): Document neoverse-n1 value.
 2019-02-22 09:56:50 +00:00
Alan Modra
160eba9301 PowerPC __tls_get_addr arg parsing 
The syntax we ended up with for -m32 -fPIC calls to __tls_get_addr is
rather weird.
    bl __tls_get_addr+0x8000(gd0@tlsgd)@plt
This came about by accident, probably due to requiring the arg reloc
before the call reloc.

Of course the @plt really belongs with __tls_get_addr since it affects
the call rather than the call arg, and it isn't a great deal of
trouble to ensure the relocs are emitted in the correct order.  This
patch supports a newer syntax, like so:
    bl __tls_get_addr+0x8000@plt(gd0@tlsgd)

gas/
	* config/tc-ppc.c (parse_tls_arg): New function, extracted..
	(md_assembler): ..from here.  Call it after parsing other
	suffix modifiers too.
ld/
	* testsuite/ld-powerpc/tls32.s: Test new @plt syntax.
 2019-02-21 18:05:05 +10:30
Paul Hua
6f2117ba38 Fix a potential deadlock in some older Loongson 3A1000 MIPS processors. 
* NEWS: Mention -m[no-]fix-loongson3-llsc.
	* configure.ac: Add --enable-mips-fix-loongson3-llsc.
	Define DEFAULT_MIPS_FIX_LOONGSON3_LLSC.
	* config.in: Regenerated.
	* configure: Likewise.
	* config/tc-mips.c (sync_insn, mips_fix_loongson3_llsc):
	New variables.
	(options): New OPTION_FIX_LOONGSON3_LLSC,
	OPTION_NO_FIX_LOONGSON3_LLSC.
	(md_longopts): Add -m[no-]fix-loongson3-llsc.
	(md_begin): Initialize sync insn.
	(fix_loongson3_llsc): New.
	(append_insn): Call fix_loongson3_llsc.
	(md_parse_option): Handle OPTION_FIX_LOONGSON3_LLSC,
	OPTION_NO_FIX_LOONGSON3_LLSC.
	(md_show_usage): Display -m[no-]fix-loongson3-llsc.
	* doc/c-mips.texi: Document -m[no-]fix-loongson3-llsc,
	--enable-mips-fix-loongson3-llsc=[yes|no].
 2019-02-19 17:57:16 +00:00
H.J. Lu
db22231044 gas: Pass max_bytes to TC_FRAG_INIT 
ommit 3ae729d5a4
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Wed Mar 7 04:18:45 2018 -0800

    x86: Rewrite NOP generation for fill and alignment

increased MAX_MEM_FOR_RS_ALIGN_CODE to 4095 which resulted in increase
of assembler time and memory usage by 5 times for inputs with many
.p2align directives, which is typical for LTO output.  This patch passes
max_bytes to TC_FRAG_INIT so that MAX_MEM_FOR_RS_ALIGN_CODE can be set
as needed and tracked by backend it so that HANDLE_ALIGN can check the
maximum alignment for each rs_align_code frag.  Wall time to assemble
the same cc1plus.s:

before:

423.78user 0.89system 7:05.71elapsed 99%CPU

after:

102.35user 0.27system 1:42.89elapsed 99%CPU

	PR gas/24165
	* frags.c (frag_var_init): Pass max_chars to TC_FRAG_INIT as
	max_bytes.
	* config/tc-aarch64.h (TC_FRAG_INIT): Add and pass max_bytes to
	aarch64_init_frag.
	* /config/tc-arm.h (TC_FRAG_INIT): And and pass max_bytes to
	arm_init_frag.
	* config/tc-avr.h (TC_FRAG_INIT): And and ignore max_bytes.
	* config/tc-ia64.h (TC_FRAG_INIT): Likewise.
	* config/tc-mmix.h (TC_FRAG_INIT): Likewise.
	* config/tc-nds32.h (TC_FRAG_INIT): Likewise.
	* config/tc-ns32k.h (TC_FRAG_INIT): Likewise.
	* config/tc-rl78.h (TC_FRAG_INIT): Likewise.
	* config/tc-rx.h (TC_FRAG_INIT): Likewise.
	* config/tc-score.h (TC_FRAG_INIT): Likewise.
	* config/tc-tic54x.h (TC_FRAG_INIT): Likewise.
	* config/tc-tic6x.h (TC_FRAG_INIT): Likewise.
	* config/tc-xtensa.h (TC_FRAG_INIT): Likewise.
	* config/tc-i386.h (MAX_MEM_FOR_RS_ALIGN_CODE): Set to
	(alignment ? ((1 << alignment) - 1) : 1)
	(i386_tc_frag_data): Add max_bytes.
	(TC_FRAG_INIT): Add and track max_bytes.
	(HANDLE_ALIGN): Replace MAX_MEM_FOR_RS_ALIGN_CODE with
	fragP->tc_frag_data.max_bytes.
	* doc/internals.texi: Update TC_FRAG_TYPE with max_bytes.
 2019-02-10 04:34:22 -08:00