Commit Graph

2198 Commits

Author SHA1 Message Date
Richard Sandiford
55e6e39790 bfd/
2006-08-02  Richard Sandiford  <richard@codesourcery.com>
	    Kazu Hirata  <kazu@codesourcery.com>
	    Phil Edwards  <phil@codesourcery.com>
	    Nathan Sidwell  <nathan@codesourcery.com>

	* config.bfd (sh-*-vxworks): Use bfd_elf32_shvxworks_vec and
	bfd_elf32_shlvxworks_vec.
	* configure.in (bfd_elf32_sh64_vec): Add elf-vxworks.lo.
	(bfd_elf32_sh64l_vec, bfd_elf32_sh64lin_vec): Likewise.
	(bfd_elf32_sh64blin_vec, bfd_elf32_sh64lnbsd_vec): Likewise.
	(bfd_elf32_sh64nbsd_vec, bfd_elf32_sh_vec): Likewise.
	(bfd_elf32_shblin_vec, bfd_elf32_shl_vec): Likewise.
	(bfd_elf32_shl_symbian_vec, bfd_elf32_shlin_vec): Likewise.
	(bfd_elf32_shlnbsd_vec, bfd_elf32_shnbsd_vec): Likewise.
	(bfd_elf32_shlvxworks_vec, bfd_elf32_shvxworks_vec): New stanzas.
	* configure: Regenerate.
	* Makefile.am: Regenerate dependencies.
	* Makefile.in: Regenerate.
	* elf-vxworks.c (elf_vxworks_gott_symbol_p): New function.
	(elf_vxworks_add_symbol_hook): Use it.
	(elf_vxworks_link_output_symbol_hook): Likewise.  Use the hash
	table entry to check for weak undefined symbols and to obtain
	the original bfd.
	(elf_vxworks_emit_relocs): Use target_index instead of this_idx.
	* elf32-sh-relocs.h: New file, split from elf32-sh.c.
	(R_SH_DIR32): Use SH_PARTIAL32 for the partial_inplace field,
	SH_SRC_MASK32 for the src_mask field, and SH_ELF_RELOC for the
	special_function field.
	(R_SH_REL32): Use SH_PARTIAL32 and SH_SRC_MASK32 here too.
	(R_SH_REL32, R_SH_TLS_GD_32, R_SH_TLS_LD_32): Likewise.
	(R_SH_TLS_LDO_32, R_SH_TLS_IE_32, R_SH_TLS_LE_32): Likewise.
	(R_SH_TLS_DTPMOD32, R_SH_TLS_DTPOFF32, R_SH_TLS_TPOFF32): Likewise.
	(R_SH_GOT32, R_SH_PLT32, R_SH_COPY, R_SH_GLOB_DAT): Likewise.
	(R_SH_JMP_SLOT, R_SH_RELATIVE, R_SH_GOTOFF, R_SH_GOTPC): Likewise.
	(SH_PARTIAL32, SH_SRC_MASK32, SH_ELF_RELOC): Undefine at end of file.
	* elf32-sh.c: Include elf32-vxworks.h.
	(MINUS_ONE): Define.
	(sh_elf_howto_table): Include elf32-sh-relocs.h with SH_PARTIAL32
	set to TRUE, SH_SRC_MASK32 set to 0xffffffff, and SH_ELF_RELOC set
	to sh_elf_reloc.
	(sh_vxworks_howto_table): New variable.  Include elf32-sh-relocs.h
	with SH_PARTIAL32 set to FALSE, SH_SRC_MASK32 set to 0, and
	SH_ELF_RELOC set to bfd_elf_generic_reloc.
	(vxworks_object_p, get_howto_table): New functions.
	(sh_elf_reloc_type_lookup): Fix typo.  Use get_howto_table.
	(sh_elf_info_to_howto): Use get_howto_table.
	(sh_elf_relax_section): Honor the partial_inplace field of the
	R_SH_DIR32 howto.
	(sh_elf_relax_delete_bytes): Likewise.
	(elf_sh_plt_info): New structure.
	(PLT_ENTRY_SIZE): Replace both definitions with...
	(ELF_PLT_ENTRY_SIZE): ...this new macro, with separate definitions for
	INCLUDE_SHMEDIA and !INCLUDE_SHMEDIA.
	(elf_sh_plt0_entry_be): Update sizes of both definitions accordingly.
	(elf_sh_plt0_entry_le): Likewise.
	(elf_sh_plt_entry_be, elf_sh_plt_entry_le): Likewise.
	(elf_sh_pic_plt_entry_be, elf_sh_pic_plt_entry_le): Likewise.
	(elf_sh_plts): New structure, with separate definitions for
	INCLUDE_SHMEDIA and !INCLUDE_SHMEDIA.
	(elf_sh_plt0_entry): Delete both definitions.
	(elf_sh_plt_entry, elf_sh_pic_plt_entry): Likewise.
	(elf_sh_sizeof_plt, elf_sh_plt_plt0_offset): Likewise.
	(elf_sh_plt_temp_offset, elf_sh_plt_symbol_offset): Likewise.
	(elf_sh_plt_reloc_offset): Likewise.
	(movi_shori_putval): Delete in favor of...
	(install_plt_field): ...this new function, with separate definitions
	for INCLUDE_SHMEDIA and !INCLUDE_SHMEDIA.
	(get_plt_info): New function, with separate definitions
	for INCLUDE_SHMEDIA and !INCLUDE_SHMEDIA.
	(elf_sh_plt0_linker_offset, elf_sh_plt0_gotid_offset): Delete.
	(VXWORKS_PLT_HEADER_SIZE, VXWORKS_PLT_ENTRY_SIZE): New macros.
	(vxworks_sh_plt0_entry_be, vxworks_sh_plt0_entry_le): New constants.
	(vxworks_sh_plt_entry_be, vxworks_sh_plt_entry_le): Likewise.
	(vxworks_sh_pic_plt_entry_be, vxworks_sh_pic_plt_entry_le): Likewise.
	(get_plt_index, get_plt_offset): New functions.
	(elf_sh_link_hash_table): Add srelplt2, plt_info and vxworks_p fields.
	(sh_elf_link_hash_table_create): Initialize them.
	(sh_elf_create_dynamic_sections): Call
	elf_vxworks_create_dynamic_sections for VxWorks.
	(allocate_dynrelocs): Use htab->plt_info to get the size of PLT
	entries.  Allocate relocation entries in .rela.plt.unloaded if
	generating a VxWorks executable.
	(sh_elf_always_size_sections): New function.
	(sh_elf_size_dynamic_sections): Extend .rela.plt handling to
	.rela.plt.unloaded.
	(sh_elf_relocate_section): Use get_howto_table.  Honor
	partial_inplace when calculating the addend for dynamic
	relocations.  Use get_plt_index.
	(sh_elf_finish_dynamic_symbol): Use get_plt_index, install_plt_field
	and htab->plt_info.  Fill in the bra .plt offset for VxWorks
	executables.  Populate .rela.plt.unloaded.  Do not make
	_GLOBAL_OFFSET_TABLE_ absolute on VxWorks.
	(sh_elf_finish_dynamic_sections): Use install_plt_field and
	htab->plt_info.  Handle cases where there is no special PLT header.
	Populate the first relocation in .rela.plt.unloaded and fix up
	the remaining entries.
	(sh_elf_plt_sym_val): Use get_plt_info.
	(elf_backend_always_size_sections): Define.
	(TARGET_BIG_SYM, TARGET_BIG_NAME): Override for VxWorks.
	(TARGET_LITTLE_SYM, TARGET_BIG_SYM): Likewise.
	(elf32_bed, elf_backend_want_plt_sym): Likewise.
	(elf_symbol_leading_char, elf_backend_want_got_underscore): Likewise.
	(elf_backend_grok_prstatus, elf_backend_grok_psinfo): Likewise.
	(elf_backend_add_symbol_hook): Likewise.
	(elf_backend_link_output_symbol_hook): Likewise.
	(elf_backend_emit_relocs): Likewise.
	(elf_backend_final_write_processing): Likewise.
	(ELF_MAXPAGESIZE, ELF_COMMONPAGESIZE): Likewise.
	* targets.c (bfd_elf32_shlvxworks_vec): Declare.
	(bfd_elf32_shvxworks_vec): Likewise.
	(_bfd_target_vector): Include bfd_elf32_shlvxworks_vec and
	bfd_elf32_shvxworks_vec.

gas/
	* config/tc-sh.c (apply_full_field_fix): New function.
	(md_apply_fix): Use it instead of md_number_to_chars.  Do not fill
	in fx_addnumber for BFD_RELOC_32_PLT_PCREL.
	(tc_gen_reloc): Use fx_addnumber rather than 0 as the default case.
	* config/tc-sh.h (TARGET_FORMAT): Override for TE_VXWORKS.

ld/
2006-08-02  Richard Sandiford  <richard@codesourcery.com>
	    Kazu Hirata  <kazu@codesourcery.com>
	    Phil Edwards  <phil@codesourcery.com>

	* Makefile.am (ALL_EMULATIONS): Add eshelf_vxworks.o and
	eshlelf_vxworks.o.
	(eshelf_vxworks.c, eshlelf_vxworks.c): New rules.
	* Makefile.in: Regenerate.
	* configure.tgt (sh-*-vxworks): Use shelf_vxworks and
	shlelf_vxworks.
	* emulparams/shelf_vxworks.sh: New file.
	* emulparams/shlelf_vxworks.sh: Likewise.
	* emulparams/vxworks.sh (FINI): Prefix _etext with ${SYMPREFIX}.
	(OTHER_END_SYMBOLS): Likewise _ehdr.
	(DATA_END_SYMBOLS): Likewise _edata.
	* emultempl/vxworks.em (vxworks_after_open): Check whether output_bfd
	is indeed an ELF file before dealing with --force-dynamic.

ld/testsuite/
	* ld-sh/rd-sh.exp: Treat vxworks1-static.d specially.
	* ld-sh/sh-vxworks.exp: New file.
	* ld-sh/sh.exp: Extend sh-linux SIZEOF_HEADERS handling to
	sh-*-vxworks.
	* ld-sh/vxworks1-le.dd, ld-sh/vxworks1-lib-le.dd,
	* ld-sh/vxworks1-lib.dd, ld-sh/vxworks1-lib.nd,
	* ld-sh/vxworks1-lib.rd, ld-sh/vxworks1-lib.s,
	* ld-sh/vxworks1-static.d, ld-sh/vxworks1.dd,
	* ld-sh/vxworks1.ld, ld-sh/vxworks1.rd, ld-sh/vxworks1.s,
	* ld-sh/vxworks2-static.sd, ld-sh/vxworks2.s,
	* ld-sh/vxworks2.sd, ld-sh/vxworks3-le.dd,
	* ld-sh/vxworks3-lib-le.dd, ld-sh/vxworks3-lib.dd,
	* ld-sh/vxworks3-lib.s, ld-sh/vxworks3.dd, ld-sh/vxworks3.s,
	* ld-sh/vxworks4.d, ld-sh/vxworks4a.s, ld-sh/vxworks4b.s,
	* ld-sh/reloc1.s, ld-sh/reloc1.d: New tests.
2006-08-04 13:13:56 +00:00
Joseph Myers
97f87066f6 gas:
* config/tc-arm.c (parse_operands): Handle invalid register name
	for OP_RIWR_RIWC.

gas/testsuite:
	* gas/arm/iwmmxt-bad.s: Test invalid register names for wldrw and
	wstrw.
	* gas/arm/iwmmxt-bad.l: Update.
2006-08-03 15:59:00 +00:00
Joseph Myers
41adaa5cab gas:
* config/tc-arm.c (enum operand_parse_code): Add OP_RIWC_RIWG.
	(parse_operands): Handle it.
	(insns): Use it for tmcr and tmrc.

gas/testsuite:
	* gas/arm/iwmmxt.s: Test tmcr and tmrc with wcgr registers.
	* gas/arm/iwmmxt.d: Update.
2006-08-03 15:57:04 +00:00
Nick Clifton
9d7cbccda0 PR binutils/2983
* bfd/elf64-x86-64.c: Add FreeBSD support.
  (elf64_x86_64_fbsd_post_process_headers): New function.
* bfd/targets.c (_bfd_target_vector): Add bfd_elf64_x86_64_freebsd_vec.
* bfd/config.bfd (x64_64-*-freebsd*): Add bfd_elf64_x86_64_freebsd_vec to the targ_selvecs.
* bfd/configure.in: Add entry for bfd_elf64_x86_64_freebsd_vec.
* bfd/configure: Regenerate.
* gas/config/tc-i386.c (md_parse_option): Treat any target starting with elf64_x86_64 as a viable target for the -64 switch.
  (i386_target_format): For 64-bit ELF flavoured output use ELF_TARGET_FORMAT64.
* gas/config/tc-i386.h (ELF_TARGET_FORMAT64): Define.
* ld/emulparams/elf_x86_64_fbsd.sh (OUTPUT_FORMAT): Define as elf64-x86-64-freebsd.
2006-08-02 16:25:14 +00:00
H.J. Lu
cfde7f7078 gas/
2006-08-01  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (md_assemble): Don't update
	cpu_arch_isa_flags.

gas/testsuite/

2006-08-01  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/nops-2-i386.d: Updated.
	* gas/i386/nops-2-merom.d: Likewise.
	* gas/i386/nops-2.d: Likewise.
2006-08-01 17:54:28 +00:00
Thiemo Seufer
b4c71f5629 * config/tc-mips.c (md_section_align): Check ELF-ness at runtime. 2006-08-01 07:58:22 +00:00
Thiemo Seufer
54f4ddb3c6 * config/tc-mips.c (macro_build_lui): Fix comment formatting.
(md_apply_fix): Likewise. Unify handling of BFD_RELOC_RVA,
	BFD_RELOC_32 and BFD_RELOC_16.
	(s_align, s_cpload, s_cplocal, s_cprestore, s_mips_stab,
	md_convert_frag, md_obj_end): Fix comment formatting.
2006-08-01 05:49:02 +00:00
Thiemo Seufer
d103cf6117 * config/tc-mips.c (md_apply_fix, tc_gen_reloc): Remove special
handling for BFD_RELOC_MIPS16_JMP.
2006-07-31 17:23:31 +00:00
Nick Clifton
784906c5f1 * config/tc-sh.c (md_longopts): Add -EL and -EB for use by the linker testsuite. 2006-07-21 09:46:15 +00:00
Thiemo Seufer
d5f010e93b * config/tc-mips.c (md_parse_option): Don't infer optimisation
options from debug options.
2006-07-20 16:51:38 +00:00
Thiemo Seufer
35d3d567cc [ bfd/ChangeLog ]
* elf32-mips.c (mips16_jump_reloc): Remove function.
	(elf_mips16_howto_table_rel): Use _bfd_mips_elf_generic_reloc
	instead of mips16_jump_reloc.
	* elf64_mips.c, wlfn32-mips.c (mips16_jump_reloc): Remove function.
	(elf_mips16_howto_table_rel, elf_mips16_howto_table_rela): Use
	_bfd_mips_elf_generic_reloc instead of mips16_jump_reloc.

	[ gas/ChangeLog ]
	* config/tc-mips.c (mips_fix_adjustable): Handle BFD_RELOC_MIPS16_JMP.
	(tc_gen_reloc): Handle mips16 jumps to section symbol offsets.

	[ ld/testsuite/ChangeLog ]
	* ld-mips-elf/mips16-call-global-1.s,
	ld-mips-elf/mips16-call-global-2.s,
	ld-mips-elf/mips16-call-global-3.s, ld-mips-elf/mips16-call-global.d:
	Test linking of external mips16 jumps.
	* ld-mips-elf/mips-elf.exp: Run new test.
2006-07-20 16:46:30 +00:00
Paul Brook
401a54cf6e 2006-07-19 Paul Brook <paul@codesourcery.com>
gas/
	* config/tc-arm.c (insns): Fix rbit Arm opcode.
	gas/testsuite/
	* gas/arm/archv6t2.d: Adjust expected output for rbit.
	opcodes/
	* armd-dis.c (arm_opcodes): Fix rbit opcode.
2006-07-19 12:53:33 +00:00
Paul Brook
16805f35a3 2006-07-18 Paul Brook <paul@codesourcery.com>
bfd/
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.
	* reloc.c: Add BFD_RELOC_ARM_T32_ADD_IMM.

	gas/
	* tc-arm.c (do_t_add_sub): Use addw/subw when source is PC.
	(md_convert_frag): Use correct reloc for add_pc.  Use
	BFD_RELOC_ARM_T32_ADD_IMM for normal add/sum.
	(md_apply_fix): Handle BFD_RELOC_ARM_T32_ADD_IMM.
	(arm_force_relocation): Handle BFD_RELOC_ARM_T32_ADD_IMM.

	gas/testsuite/
	* gas/arm/thumb2_add.d: New test.
	* gas/arm/thumb2_add.s: New test.
2006-07-18 16:44:47 +00:00
Thiemo Seufer
f43abd2b39 * read.c (s_struct): Use IS_ELF.
* config/tc-mips.c (md_begin, mips16_mark_labels, mips_ip,
	md_parse_option, s_change_sec, pic_need_relax, mips_fix_adjustable,
	tc_gen_reloc, mips_frob_file_after_relocs, s_mips_end, s_mips_frame,
	s_mips_mask): Likewise.
2006-07-17 10:40:11 +00:00
H.J. Lu
d32cad6576 2006-07-15 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (cpu_arch): Remove Cpu086, CpuAthlon and
	CpuAmdFam10.
	(smallest_imm_type): Remove Cpu086.
	(i386_target_format): Likewise.

	* config/tc-i386.h: Remove Cpu086, CpuAthlon and CpuAmdFam10.
	Update CpuXXX.
2006-07-15 16:32:48 +00:00
Michael Meissner
050dfa73de Add amdfam10 instructions 2006-07-13 22:25:48 +00:00
H.J. Lu
6b2de085ee 2006-07-13 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.h (Size64): Fix a typo in comment.
2006-07-13 18:13:36 +00:00
Nick Clifton
01eaea5ad2 * config/tc-sh.c (md_apply_fix): Do not allow the generic code in
fixup_segment() to repeat a range check on a value that have already
  been checked here.
* gas/sh/basic.exp: Run "too_large" dump test.
* gas/sh/too_large.s: New test file.  Check that .byte directives do not
  generate a bogus overflow message.
* gas/sh/too_large.s: New test control file.
2006-07-12 09:02:00 +00:00
Jim Wilson
1e85aad828 Add Broadcom SB-1A support.
* config/tc-mips.c (mips_cpu_info_table): Add sb1a.
2006-07-07 23:17:55 +00:00
Nick Clifton
1370e33d0d PR binutils/2877
* doc/as.texi: Fix spelling typo: branchs => branches.
* doc/c-m68hc11.texi: Likewise.
* config/tc-m68hc11.c: Likewise.
  Support old spelling of command line switch for backwards compatibility.
2006-07-06 10:34:02 +00:00
Thiemo Seufer
5f0fe04bc5 * config/tc-mips.c (s_is_linkonce): New function.
(mips16_mark_labels): Don't adjust mips16 symbol addresses for
	weak, external, and linkonce symbols.
	(pic_need_relax): Use s_is_linkonce.
2006-07-04 17:22:11 +00:00
H.J. Lu
ccc9c02779 gas/
2006-06-23  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (cpu_arch_tune_set): New.
	(cpu_arch_isa): Likewise.
	(i386_align_code): Use xchg %ax,%ax for 2 byte nop. Optimize
	nops with short or long nop sequences based on -march=/.arch
	and -mtune=.
	(set_cpu_arch): Set cpu_arch_isa.  If cpu_arch_tune_set is 0,
	set cpu_arch_tune and cpu_arch_tune_flags.
	(md_parse_option): For -march=, set cpu_arch_isa and set
	cpu_arch_tune and cpu_arch_tune_flags if cpu_arch_tune_set is
	0.  Set cpu_arch_tune_set to 1 for -mtune=.
	(i386_target_format): Don't set cpu_arch_tune.

gas/testsuite/

2006-06-23  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/i386.exp: Run nops-1, nops-1-i386, nops-1-i686,
	nops-1-merom, nops-2, nops-2-i386, nops-2-merom, x86-64-nops-1,
	x86-64-nops-1-k8, x86-64-nops-1-nocona and x86-64-nops-1-merom.

	* gas/i386/nops-1.s: New file.
	* gas/i386/nops-2.s: Likewise.
	* gas/i386/nops-1-i386.d: Likewise.
	* gas/i386/nops-1-i686.d: Likewise.
	* gas/i386/nops-1-merom.d: Likewise.
	* gas/i386/nops-1.d: Likewise.
	* gas/i386/nops-2-i386.d: Likewise.
	* gas/i386/nops-2-merom.d: Likewise.
	* gas/i386/nops-2.d: Likewise.
	* gas/i386/x86-64-nops-1.s: Likewise.
	* gas/i386/x86-64-nops-1-k8.d: Likewise.
	* gas/i386/x86-64-nops-1-merom.d: Likewise.
	* gas/i386/x86-64-nops-1-nocona.d: Likewise.
	* gas/i386/x86-64-nops-1.d: Likewise.

	* gas/i386/sse2.d: Updated to expect xchg %ax,%ax as 2 byte
	nop.
2006-06-23 21:47:36 +00:00
Thiemo Seufer
d4dc2f22f5 * config/tc-mips.c (nopic_need_relax): Handle -fdata-sections
generated .sbss.* and .gnu.linkonce.sb.*.
2006-06-23 18:31:17 +00:00
Thiemo Seufer
a8dbcb8573 * config/tc-mips.h (TC_SEGMENT_INFO_TYPE): Declare per-segment
label_list.
	* config/tc-mips.c (label_list): Define per-segment label_list.
	(mips_clear_insn_labels, mips_move_labels, mips16_mark_labels,
	append_insn, s_align, s_cons, s_float_cons, s_gpword, s_gpdword,
	mips_from_file_after_relocs, mips_define_label): Use per-segment
	label_list.
2006-06-23 16:26:13 +00:00
Thiemo Seufer
3994f87e99 * config/tc-mips.c (ISA_SUPPORTS_MIPS16E): New macro.
(append_insn): Use it.
	(md_apply_fix): Whitespace formatting.
	(md_begin, append_insn, macro, macro2, mips16_immed, mips_align,
	mips16_extended_frag): Remove register specifier.
	(md_convert_frag): Likewise. Use TRUE ans FALSE instead of numeric
	constants.
2006-06-22 14:09:40 +00:00
Mark Shinwell
fa073d6911 gas/
* config/tc-arm.c (s_arm_unwind_save_vfp_armv6): New.  Parse
	a directive saving VFP registers for ARMv6 or later.
	(s_arm_unwind_save): Add parameter arch_v6 and call
	s_arm_unwind_save_vfp or s_arm_unwind_save_vfp_armv6 as
	appropriate.
	(md_pseudo_table): Add entry for new "vsave" directive.
	* doc/c-arm.texi: Correct error in example for "save"
	directive (fstmdf -> fstmdx).  Also document "vsave" directive.
2006-06-21 14:20:25 +00:00
Denis Chertykov
026dcbd716 * config/tc-avr.c (mcu_types): Add support for atmega165p, atmega169p
and atmega644p devices. Rename atmega164/atmega324 devices to
	atmega164p/atmega324p.
	* doc/c-avr.texi: Document new mcu and arch options.
2006-06-19 16:58:29 +00:00
Nick Clifton
8b1ad4545a (enum parse_operand_result): Move outside of #ifdef OBJ_ELF so that non-ELF
targeted ARM ports can build.
2006-06-17 16:05:41 +00:00
H.J. Lu
9103f4f44a 2006-06-16 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.h (processor_type): New.
	(arch_entry): Add type.

	* config/tc-i386.c (cpu_arch_tune): New.
	(cpu_arch_tune_flags): Likewise.
	(cpu_arch_isa_flags): Likewise.
	(cpu_arch): Updated.
	(set_cpu_arch): Also update cpu_arch_isa_flags.
	(md_assemble): Update cpu_arch_isa_flags.
	(OPTION_MARCH): New.
	(OPTION_MTUNE): Likewise.
	(md_longopts): Add -march= and -mtune=.
	(md_parse_option): Support -march= and -mtune=.
	(md_show_usage): Add -march=CPU/-mtune=CPU.
	(i386_target_format): Also update cpu_arch_isa_flags,
	cpu_arch_tune and cpu_arch_tune_flags.

	* doc/as.texinfo: Add -march=CPU/-mtune=CPU.

	* doc/c-i386.texi: Document -march=CPU/-mtune=CPU.
2006-06-16 15:46:11 +00:00
Mark Shinwell
4962c51a67 * include/elf/arm.h: Correct names of R_ARM_LDC_G{0,1,2}
to R_ARM_LDC_SB_G{0,1,2} respectively.

bfd/
	* bfd-in2.h: Regenerate.
	* elf32-arm.c (R_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0,
	R_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1, R_ARM_ALU_PC_G2,
	R_ARM_LDR_PC_G1, R_ARM_LDR_PC_G2, R_ARM_LDRS_PC_G0,
	R_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G2, R_ARM_LDC_PC_G0,
	R_ARM_LDC_PC_G1, R_ARM_LDC_PC_G2, R_ARM_ALU_SB_G0_NC,
	R_ARM_ALU_SB_G0, R_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1,
	R_ARM_ALU_SB_G2, R_ARM_LDR_SB_G0, R_ARM_LDR_SB_G1,
	R_ARM_LDR_SB_G2, R_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G1,
	R_ARM_LDRS_SB_G2, R_ARM_LDC_SB_G0, R_ARM_LDC_SB_G1,
	R_ARM_LDC_SB_G2): New relocation types.
	(R_ARM_PC13): Rename to AAELF name R_ARM_LDR_PC_G0 and
	adjust HOWTO entry to be consistent with R_ARM_LDR_PC_G1
	and friends.
	(elf32_arm_howto_table_3): Delete; contents merged into
	elf32_arm_howto_table_2.
	(elf32_arm_howto_from_type): Adjust correspondingly.
	(elf32_arm_reloc_map): Extend with the above relocations.
	(calculate_group_reloc_mask): New function.
	(identify_add_or_sub): New function.
	(elf32_arm_final_link_relocate): Support for the above
	relocations.
	* reloc.c: Add enumeration entries for BFD_RELOC_ARM_...
	codes to correspond to the above relocations.

gas/
	* config/tc-arm.c (enum parse_operand_result): New.
	(struct group_reloc_table_entry): New.
	(enum group_reloc_type): New.
	(group_reloc_table): New array.
	(find_group_reloc_table_entry): New function.
	(parse_shifter_operand_group_reloc): New function.
	(parse_address_main): New function, incorporating code
	from the old parse_address function.  To be used via...
	(parse_address): wrapper for parse_address_main; and
	(parse_address_group_reloc): new function, likewise.
	(enum operand_parse_code): New codes OP_SHG, OP_ADDRGLDR,
	OP_ADDRGLDRS, OP_ADDRGLDC.
	(parse_operands): Support for these new operand codes.
	New macro po_misc_or_fail_no_backtrack.
	(encode_arm_cp_address): Preserve group relocations.
	(insns): Modify to use the above operand codes where group
	relocations are permitted.
	(md_apply_fix): Handle the group relocations
	ALU_PC_G0_NC through LDC_SB_G2.
	(tc_gen_reloc): Likewise.
	(arm_force_relocation): Leave group relocations for the linker.
	(arm_fix_adjustable): Likewise.

gas/testsuite/
	* gas/arm/group-reloc-alu.d: New test.
	* gas/arm/group-reloc-alu-encoding-bad.d: New test.
	* gas/arm/group-reloc-alu-encoding-bad.l: New test.
	* gas/arm/group-reloc-alu-encoding-bad.s: New test.
	* gas/arm/group-reloc-alu-parsing-bad.d: New test.
	* gas/arm/group-reloc-alu-parsing-bad.l: New test.
	* gas/arm/group-reloc-alu-parsing-bad.s: New test.
	* gas/arm/group-reloc-alu.s: New test.
	* gas/arm/group-reloc-ldc.d: New test.
	* gas/arm/group-reloc-ldc-encoding-bad.d: New test.
	* gas/arm/group-reloc-ldc-encoding-bad.l: New test.
	* gas/arm/group-reloc-ldc-encoding-bad.s: New test.
	* gas/arm/group-reloc-ldc-parsing-bad.d: New test.
	* gas/arm/group-reloc-ldc-parsing-bad.l: New test.
	* gas/arm/group-reloc-ldc-parsing-bad.s: New test.
	* gas/arm/group-reloc-ldc.s: New test.
	* gas/arm/group-reloc-ldr.d: New test.
	* gas/arm/group-reloc-ldr-encoding-bad.d: New test.
	* gas/arm/group-reloc-ldr-encoding-bad.l: New test.
	* gas/arm/group-reloc-ldr-encoding-bad.s: New test.
	* gas/arm/group-reloc-ldr-parsing-bad.d: New test.
	* gas/arm/group-reloc-ldr-parsing-bad.l: New test.
	* gas/arm/group-reloc-ldr-parsing-bad.s: New test.
	* gas/arm/group-reloc-ldr.s: New test.
	* gas/arm/group-reloc-ldrs.d: New test.
	* gas/arm/group-reloc-ldrs-encoding-bad.d: New test.
	* gas/arm/group-reloc-ldrs-encoding-bad.l: New test.
	* gas/arm/group-reloc-ldrs-encoding-bad.s: New test.
	* gas/arm/group-reloc-ldrs-parsing-bad.d: New test.
	* gas/arm/group-reloc-ldrs-parsing-bad.l: New test.
	* gas/arm/group-reloc-ldrs-parsing-bad.s: New test.
	* gas/arm/group-reloc-ldrs.s: New test.

ld/testsuite/
	* ld-arm/group-relocs-alu-bad.d: New test.
	* ld-arm/group-relocs-alu-bad.s: New test.
	* ld-arm/group-relocs.d: New test.
	* ld-arm/group-relocs-ldc-bad.d: New test.
	* ld-arm/group-relocs-ldc-bad.s: New test.
	* ld-arm/group-relocs-ldr-bad.d: New test.
	* ld-arm/group-relocs-ldr-bad.s: New test.
	* ld-arm/group-relocs-ldrs-bad.d: New test.
	* ld-arm/group-relocs-ldrs-bad.s: New test.
	* ld-arm/group-relocs.s: New test.
	* ld-arm/arm-elf.exp: Wire in new tests.
2006-06-15 11:03:02 +00:00
Julian Brown
cd2f129fb4 * config/tc-arm.c (do_vfp_nsyn_ldr_str): Remove, fold into...
(do_neon_ldr_str): Always defer to VFP encoding routines, which handle
	relocs properly.
2006-06-15 10:51:28 +00:00
H.J. Lu
46e883c5a9 gas/
2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (process_suffix): Don't add rex64 for
	"xchg %rax,%rax".

gas/testsuite/

2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/opcode.s: Add "xchg %ax,%ax".
	* gas/i386/opcode.d: Updated.

	* gas/i386/x86-64-opcode.s: Add xchg %ax,%ax, xchg %eax,%eax,
	xchg %rax,%rax, rex64 xchg %rax,%rax and xchg %rax,%r8.
	* gas/i386/x86-64-opcode.d: Updated.

include/opcode/

2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Update comment for 64bit NOP.

opcodes/

2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (NOP_Fixup): Removed.
	(NOP_Fixup1): New.
	(NOP_Fixup2): Likewise.
	(dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
2006-06-12 18:55:44 +00:00
Thiemo Seufer
a339155f83 Lost bit belonging to the last commit. 2006-06-09 12:55:00 +00:00
Alan Modra
96f989c24e * config/tc-iq2000.c: Include sb.h. 2006-06-09 03:42:25 +00:00
Thiemo Seufer
7c752c2afc * config/tc-mips.c (mips_pseudo_table): Add "origin" and "repeat"
aliases for better compatibility with SGI tools.
2006-06-08 15:28:26 +00:00
Julian Brown
037e874458 * config/tc-arm.c (stdarg.h): include.
(arm_it): Add uncond_value field. Add isvec and issingle to operand
	array.
	(arm_reg_type): Add REG_TYPE_VFSD (single or double VFP reg) and
	REG_TYPE_NSDQ (single, double or quad vector reg).
	(reg_expected_msgs): Update.
	(BAD_FPU): Add macro for unsupported FPU instruction error.
	(parse_neon_type): Support 'd' as an alias for .f64.
	(parse_typed_reg_or_scalar): Support REG_TYPE_VFSD, REG_TYPE_NSDQ
	sets of registers.
	(parse_vfp_reg_list): Don't update first arg on error.
	(parse_neon_mov): Support extra syntax for VFP moves.
	(operand_parse_code): Add OP_RVSD, OP_RNSDQ, OP_VRSDLST, OP_RVSD_IO,
	OP_RNSDQ_RNSC, OP_RVC_PSR, OP_APSR_RR, OP_oRNSDQ.
	(parse_operands): Support isvec, issingle operands fields, new parse
	codes above.
	(do_vfp_nsyn_mrs, do_vfp_nsyn_msr): New functions. Support VFP mrs,
	msr variants.
	(do_mrs, do_msr, do_t_mrs, do_t_msr): Add support for above.
	(NEON_ENC_TAB): Add vnmul, vnmla, vnmls, vcmp, vcmpz, vcmpe, vcmpez.
	(NEON_ENC_SINGLE, NEON_ENC_DOUBLE): Define macros.
	(NEON_SHAPE_DEF): New macro. Define table of possible instruction
	shapes.
	(neon_shape): Redefine in terms of above.
	(neon_shape_class): New enumeration, table of shape classes.
	(neon_shape_el): New enumeration. One element of a shape.
	(neon_shape_el_size): Register widths of above, where appropriate.
	(neon_shape_info): New struct. Info for shape table.
	(neon_shape_tab): New array.
	(neon_type_mask): Add N_F64, N_VFP. Update N_MAX_NONSPECIAL.
	(neon_check_shape): Rewrite as...
	(neon_select_shape): New function to classify instruction shapes,
	driven by new table neon_shape_tab array.
	(neon_quad): New function. Return 1 if shape should set Q flag in
	instructions (or equivalent), 0 otherwise.
	(type_chk_of_el_type): Support F64.
	(el_type_of_type_chk): Likewise.
	(neon_check_type): Add support for VFP type checking (VFP data
	elements fill their containing registers).
	(do_vfp_cond_or_thumb): Fill in condition field in ARM mode, or 0xE
	in thumb mode for VFP instructions.
	(do_vfp_nsyn_opcode): New function. Look up the opcode in argument,
	and encode the current instruction as if it were that opcode.
	(try_vfp_nsyn): New. If this looks like a VFP instruction with ARGS
	arguments, call function in PFN.
	(do_vfp_nsyn_add_sub, do_vfp_nsyn_mla_mls, do_vfp_nsyn_mul)
	(do_vfp_nsyn_abs_neg, do_vfp_nsyn_ldm_stm, do_vfp_nsyn_ldr_str)
	(do_vfp_nsyn_sqrt, do_vfp_nsyn_div, do_vfp_nsyn_nmul)
	(do_vfp_nsyn_cmp, nsyn_insert_sp, do_vfp_nsyn_push)
	(do_vfp_nsyn_pop, do_vfp_nsyn_cvt, do_vfp_nsyn_cvtz): New functions.
	Redirect Neon-syntax VFP instructions to VFP instruction handlers.
	(do_neon_dyadic_i_su, do_neon_dyadic_i64_su, do_neon_shl_imm)
	(do_neon_qshl_imm, do_neon_logic, do_neon_bitfield)
	(neon_dyadic_misc, neon_compare, do_neon_tst, do_neon_qdmulh)
	(do_neon_fcmp_absolute, do_neon_step, do_neon_sli, do_neon_sri)
	(do_neon_qshlu_imm, neon_move_immediate, do_neon_mvn, do_neon_ext)
	(do_neon_rev, do_neon_dup, do_neon_rshift_round_imm, do_neon_trn)
	(do_neon_zip_uzp, do_neon_sat_abs_neg, do_neon_pair_long)
	(do_neon_recip_est, do_neon_cls, do_neon_clz, do_neon_cnt)
	(do_neon_swp): Use neon_select_shape not neon_check_shape. Use
	neon_quad.
	(vfp_or_neon_is_neon): New function. Call if a mnemonic shared
	between VFP and Neon turns out to belong to Neon. Perform
	architecture check and fill in condition field if appropriate.
	(do_neon_addsub_if_i, do_neon_mac_maybe_scalar, do_neon_abs_neg)
	(do_neon_cvt): Add support for VFP variants of instructions.
	(neon_cvt_flavour): Extend to cover VFP conversions.
	(do_neon_mov): Rewrite to use neon_select_shape. Add support for VFP
	vmov variants.
	(do_neon_ldr_str): Handle single-precision VFP load/store.
	(do_neon_ld_st_interleave, do_neon_ld_st_lane, do_neon_ld_dup): Use
	NS_NULL not NS_IGNORE.
	(opcode_tag): Add OT_csuffixF for operands which either take a
	conditional suffix, or have 0xF in the condition field.
	(md_assemble): Add support for OT_csuffixF.
	(NCE): Replace macro with...
	(NCE_tag, NCE, NCEF): New macros.
	(nCE): Replace macro with...
	(nCE_tag, nCE, nCEF): New macros.
	(insns): Add support for VFP insns or VFP versions of insns msr,
	mrs, vsqrt, vdiv, vnmul, vnmla, vnmls, vcmp, vcmpe, vpush, vpop,
	vcvtz, vmul, vmla, vmls, vadd, vsub, vabs, vneg, vldm, vldmia,
	vldbdb, vstm, vstmia, vstmdb, vldr, vstr, vcvt, vmov. Group shared
	VFP/Neon insns together.
2006-06-07 14:32:28 +00:00
Alan Modra
ebd1c8757c remove some duplicate #include's. 2006-06-07 11:27:58 +00:00
Alan Modra
9622b051cf include/opcode/
* ppc.h (PPC_OPCODE_POWER6): Define.
	Adjust whitespace.
gas/
	* config/tc-ppc.c (parse_cpu): Handle "-mpower6".
	(md_show_usage): Document it.
	(ppc_setup_opcodes): Test power6 opcode flag bits.
	* doc/c-ppc.texi (PowerPC-Opts): Document "-mpower6".
opcodes/
	* ppc-dis.c (powerpc_dialect): Handle power6 option.
	(print_ppc_disassembler_options): Mention power6.
2006-06-07 05:23:59 +00:00
Thiemo Seufer
65263ce323 [ gas/ChangeLog ]
* config/tc-mips.c (ISA_SUPPORTS_DSP64): New macro.
	(CPU_HAS_MIPS3D, CPU_HAS_MDMX, CPU_HAS_DSP, CPU_HAS_MT): Delete.
	(macro_build): Update comment.
	(mips_ip): Allow DSP64 instructions for MIPS64R2.
	(mips_after_parse_args): Remove uses of CPU_HAS_MIPS3D and
	CPU_HAS_MDMX.
	(mips_cpu_info): Fix formatting. Add MIPS_CPU_ASE_MIPS3D and
	MIPS_CPU_ASE_MDMX flags for sb1.

	[ gas/testsuite/ChangeLog ]
	* gas/mips/mips64-dsp.s, gas/mips/mips64-dsp.d: New DSP64 tests.
	* gas/mips/mips.exp: Run DSP64 tests.

	[ opcodes/ChangeLog ]
	* mips-dis.c: Disassemble DSP64 instructions for MIPS64R2.
	* mips-opc.c: Add DSP64 instructions.
2006-06-06 10:49:48 +00:00
Thiemo Seufer
a9e2435482 [ gas/ChangeLog ]
* config/tc-mips.c (macro_build): Use INSERT_OPERAND wherew
	appropriate.
	(mips16_macro_build): Use MIPS16_INSERT_OPERAND where appropriate.
	(mips_ip): Make overflowed/underflowed constant arguments in DSP
	and MT instructions a fatal error. Use INSERT_OPERAND where
	appropriate. Improve warnings for break and wait code overflows.
	Use symbolic constant of OP_MASK_COPZ.
	(mips16_ip): Use MIPS16_INSERT_OPERAND where appropriate.

	[ gas/testsuite/ChangeLog ]
	* gas/mips/mips32-dsp.d, gas/mips/mips32-dsp.s, gas/mips/mips32-mt.d,
	gas/mips/mips32-mt.s: Remove instructions with invalid arguments.
	* gas/mips/mips32-dsp.l, gas/mips/mips32-mt.l: Delete file.

	[ include/opcode/ChangeLog ]
	* mips.h: Improve description of MT flags.
2006-06-05 16:28:36 +00:00
Alan Modra
12e64c2c29 * config/obj-ieee.c: Delete.
* config/obj-ieee.h: Delete.
	* Makefile.am (OBJ_FORMATS): Remove ieee.
	(OBJ_FORMAT_CFILES, OBJ_FORMAT_HFILES): Similarly.
	(obj-ieee.o): Remove rule.
	* Makefile.in: Regenerate.
	* configure.in (atof): Remove tahoe.
	(OBJ_MAYBE_IEEE): Don't define.
	* configure: Regenerate.
	* config.in: Regenerate.
	* doc/Makefile.in: Regenerate.
	* po/POTFILES.in: Regenerate.
2006-06-01 12:21:05 +00:00
Jie Zhang
f8fdc85041 * config/bfin-parse.y (check_macfunc): Loose the condition of
calling check_multiply_halfregs ().
2006-05-28 00:53:08 +00:00
Jie Zhang
a32054651a * config/bfin-parse.y (asm_1): Better check and deal with
vector and scalar Multiply 16-Bit Operands instructions.
2006-05-25 04:07:08 +00:00
Nick Clifton
9b52905e69 Add TLS support for hppa-linux 2006-05-24 11:05:42 +00:00
Nick Clifton
28c9d252b4 Add support for AVR6 family 2006-05-24 07:36:12 +00:00
Thiemo Seufer
ad3fea084d [ gas/ChangeLog ]
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
	(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
	ISA_HAS_MXHC1): New macros.
	(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
	ISA_HAS_64BIT_REGS.  Formatting fixes.  Improved comments.
	(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
	(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
	MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
	(mips_after_parse_args): Change default handling of float register
	size to account for 32bit code with 64bit FP. Better sanity checking
	of ISA/ASE/ABI option combinations.
	(s_mipsset): Support switching of GPR and FPR sizes via
	.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
	options.
	(mips_elf_final_processing): We should record the use of 64bit FP
	registers in 32bit code but we don't, because ELF header flags are
	a scarce ressource.
	(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
	extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
	24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
	(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
	* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
	missing -march options. Document .set arch=CPU. Move .set smartmips
	to ASE page. Use @code for .set FOO examples.

	[ gas/testsuite/Changelog ]
	* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
	gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
	gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
	output.
	* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
	catch assembler warnings.
2006-05-23 15:37:20 +00:00
Jie Zhang
8b64503a98 * config/tc-bfin.c (bfin_start_line_hook): Bump line counters
if needed.
2006-05-23 06:01:12 +00:00
Jie Zhang
aaceb81c03 Commit the missing bits of my last patch. 2006-05-23 04:56:56 +00:00
Jie Zhang
403022e0dc * config/bfin-defs.h (bfin_equals): Remove declaration.
* config/bfin-parse.y (asm_1): Remove "expr ASSIGN expr".
	* config/tc-bfin.c (bfin_name_is_register): Remove.
	(bfin_equals): Remove.
	* config/tc-bfin.h (TC_EQUAL_IN_INSN): Redefine as 1.
	(bfin_name_is_register): Remove declaration.
2006-05-23 04:23:41 +00:00
Thiemo Seufer
7455baf866 * config/tc-mipc.c (ISA_HAS_ODD_SINGLE_FPR): New define.
(mips_oddfpreg_ok): New function.
	(mips_ip): Use it.
-------------------------------------------------------------------
2006-05-19 13:03:06 +00:00